From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9775C433F5 for ; Tue, 17 May 2022 16:00:31 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5C05D8365B; Tue, 17 May 2022 18:00:28 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="p77m7pS8"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 23B9D839CE; Tue, 17 May 2022 18:00:26 +0200 (CEST) Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 92219811D8 for ; Tue, 17 May 2022 18:00:22 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 9D71361225; Tue, 17 May 2022 16:00:20 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AEBBEC385B8; Tue, 17 May 2022 16:00:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1652803220; bh=XF1ehD7/WTTRFmmouZadUmn4JbX9TpOJ4rrNEw/0S2k=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=p77m7pS8mtcmXD/JWHagg5CkdwjcKfXFiZg/VGy4nJlRaIsw6eWk1tZGCHENSX4/6 wcH554fub03bC+LsAz4aLTc+6Y4DL2kG+0nG1Ohg8qZpIMtZz406X5+CP0tjEAGLRW 8+IkWZ+cbtk7zP0m6YsVwvF2/HTkd3FxfSyzg+JjscdSSD5VT1c+vOYb/99XaDg7Mx sZCz+atX2Ci2uW1glbJ1iaqJdlSru5hYKw53ISeKmju3h+meOShysQdC/PFfx/ziT9 tocsBs6rdqDaDDOF5a7pEKMa50oQmIUGbznYJBz2RnxZcNaj6fWxSd5cpJZRF44lBB xGtq3R8Ax6Tbg== Received: by pali.im (Postfix) id AF1AD7DA; Tue, 17 May 2022 18:00:16 +0200 (CEST) Date: Tue, 17 May 2022 18:00:16 +0200 From: Pali =?utf-8?B?Um9ow6Fy?= To: Tom Rini Cc: Simon Glass , u-boot@lists.denx.de Subject: Re: Broken support for 4GB DDR on 32-bit platforms Message-ID: <20220517160016.ji4g3ly3rylhmfrp@pali> References: <20220513230006.ep5qdhuu6k5ado2l@pali> <20220516123143.GI3901321@bill-the-cat> <20220516215651.g4joz4p6atpv57h2@pali> <20220517155214.GS3901321@bill-the-cat> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220517155214.GS3901321@bill-the-cat> User-Agent: NeoMutt/20180716 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On Tuesday 17 May 2022 11:52:14 Tom Rini wrote: > On Mon, May 16, 2022 at 11:56:51PM +0200, Pali Rohár wrote: > > On Monday 16 May 2022 08:31:43 Tom Rini wrote: > > > On Sat, May 14, 2022 at 01:00:06AM +0200, Pali Rohár wrote: > > > > > > > Hello! I tried to enable support for 2GB+ of DDR memory (with 4GB DDR3) > > > > on powerpc P2020 board in 32-bit addressing mode and U-Boot crashed > > > > during startup. > > > > > > > > I figured out that issue is not powerpc specific, but rather generic to > > > > all 32-bit platforms. U-Boot stores memory size into phys_size_t type > > > > (gd->ram_size) and last mapped memory address increased by one byte into > > > > phys_addr_t type (gd->ram_top). > > > > > > > > Despite size 4GB fits into 32-bit addressing mode, it does not fit into > > > > above two variables, and it overflows to zero. U-Boot then see zero RAM > > > > size and crashes. > > > > > > > > I tried to workaround this issue by changing both phys_size_t and > > > > phys_addr_t types to 64-bit. But it did not helped because U-Boot on > > > > many places cast gd->ram_size or gd->ram_top to ulong type, which is > > > > 32-bit on 32-bit platforms. > > > > > > > > Next I changed ulong parameters of board_get_usable_ram_top() function > > > > to u64. > > > > > > > > This still was not enough because config value CONFIG_MAX_MEM_MAPPED is > > > > ignored on one important place -- in function get_effective_memsize(). > > > > This config value takes effect only when also CONFIG_VERY_BIG_RAM is > > > > set. > > > > > > > > Finally With this change I was able to start U-Boot with more than 2GB > > > > of DDR memory inserted in SODIMM slot on P2020. > > > > > > > > How to fix issues with gd->ram_size and gd->ram_top? That +1 byte is > > > > really stupid limitation. Changing phys_size_t and phys_addr_t types > > > > unconditionally to 64-bit? Or something else? > > > > > > > > And what is the purpose of CONFIG_VERY_BIG_RAM config option? Why is > > > > CONFIG_MAX_MEM_MAPPED check skipped in get_effective_memsize() function, > > > > but is not skipped on many more places? > > > > > > So, there's two parts to this, as I recall it all. First, even on 64bit > > > platforms we contain ourselves to 32bit address space and even then > > > something within the "old" 2GB window. We then set a CONFIG option to > > > not mess with the memory node in DT which has the real value. Second, > > > for 32bit platforms which can support 4GB memory, or more, some further > > > games need to be played, typically I believe around initializing the > > > memory controller (I'm more confident of that for dra7xx_evm, which I > > > don't have the big memory version of, just a small memory one) so that > > > Linux can do whatever needs doing to enable "36bit" typically address > > > support. Looking at the other P*36BIT* configs might give you some more > > > clues about what to do on your platform, or at least who might still be > > > able to explain and test things on the PowerPC side. > > > > I know about 36-bit addressing on e500v2 but I'm not going to enable it > > due to performance reasons (see Freescale AN4064 [1]). So I want to > > stick with 32-bit addressing for 2GB+ memory usage (around 3GB; it is > > 4GB minus memory used by peripherals; which is still more than 2GB). > > > > And due to 32-bit type for phys_size_t, phys_addr_t and casting these > > types to ulong is an issue. Plus issue with CONFIG_VERY_BIG_RAM and > > CONFIG_MAX_MEM_MAPPED as I already wrote. > > I'm not seeing the problem, sorry. You run U-Boot in the normal 2GB Ok, I will try to explain it again. I want to run U-Boot in normal 2GB area. U-Boot normally store detected RAM size into the gd->ram_size structure. And here is the issue. 32-bit unsigned C type cannot represent maximal 32-bit addressable size. U-Boot tries to store 4GB value = 0x100000000 into gd->ram_size which overflows to 0x00000000. And U-Boot then crashes because it expects that can store some data at address "gd->ram_size - few_kb" as it expects that RAM is in the area [0, gd->ram_size). It is more clear what is the problem? If I theoretically find 3.9GB RAM module (but such probably does not exist) then U-Boot should work in normal 2GB area as number 3.9GB can be stored into 32-bit unsigned type. > area and tell Linux there's 3GB available. I kinda recall now that yes, > you can do a 3:1 split in Linux instead of 2:2 split, but in that case > you still do 2:2 in U-Boot. As you have seen configuring for anything > else doesn't work. > > -- > Tom