From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 361EEC433EF for ; Wed, 18 May 2022 09:58:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234894AbiERJ6C (ORCPT ); Wed, 18 May 2022 05:58:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234897AbiERJ5q (ORCPT ); Wed, 18 May 2022 05:57:46 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42F5A3150D for ; Wed, 18 May 2022 02:57:44 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id r71so1727199pgr.0 for ; Wed, 18 May 2022 02:57:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=tc9+bvqYCqMUSJXb0nfQvcyKgjqV7Ocz6lWJsoBLOyQ=; b=am+ErBo1ZB0G/hYVBrcfY1g1WCS12VRPKU0MqxO1eFPOZMnO1PfcYkLY3tknTliDWw wBxg3LqZeg3ef3iGmyHkqn5SkRzAY1N5efuwoM7Ks+s38oDEoUJ05k6XRmLMQkuXE23j Ts51nH6G6UDl9pi4Jy0PmG8h/z4mbK/jT4Qi/3K+KzA3bYHCZ9R60zq74x+5dZidSzJ/ eWrgC3XfDdl4Mzm+4qDElEQJiU4NCV3owan7qspY8A0AndODbOwqRy2U50Dzxc/nU3as 5QpBsthosbzuJM2zWM2vnv8Db49i3VEpNpZVfEub7knFMi3uWBTIiRIJdYAeOvh0dkuN GJzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=tc9+bvqYCqMUSJXb0nfQvcyKgjqV7Ocz6lWJsoBLOyQ=; b=MYgo376JwKNQd29cgneNpbJd+xccRQy6gWxns5IwrMeVisOzlPfsSFnc1QIsk5uaio epiOx+kGWHDyl3+TrWr284X4rPultL5lzv89kKNNWS2cFkNeZkD7qmXjSs+oz5S7tEGB hVtrKxpPgjle4VXUpVS8xvtkyd9iKlbkFAbLDvLVX5W3PDw3ztaBiMwnne2fUJ4KPmVR CJMwYgurOhpWr2PNxeGV3Cm3nIug1UZ9FqIPn2eoDB+BhIkl9zsTJW5TUDgKWlCXHZ9w ZRAZGWZzCtrbP5Jgcoj5N+aozDlTpdtz2H78bAX3RIrEJi6IFHbH6rXHo5B9uyspw4ZI PsYA== X-Gm-Message-State: AOAM530PGfJda59bUHF9ZcXCWynFowAeRahzw0g/45CqzWNA9xmaz1OZ F+6E5ywVOAM4VPfwadUz1RgLVA== X-Google-Smtp-Source: ABdhPJwxN17DvvwgA27WGHd/CQU6EzFpAzCAl1BFGWWAOX6ggp1eIFb0ryL4HktPXI/Dtai14vWbIA== X-Received: by 2002:a63:5a01:0:b0:3d8:22cb:9224 with SMTP id o1-20020a635a01000000b003d822cb9224mr22960915pgb.548.1652867863321; Wed, 18 May 2022 02:57:43 -0700 (PDT) Received: from leoy-ThinkPad-X240s ([137.184.121.66]) by smtp.gmail.com with ESMTPSA id s26-20020a056a001c5a00b005180ea859d7sm1419223pfw.123.2022.05.18.02.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 May 2022 02:57:42 -0700 (PDT) Date: Wed, 18 May 2022 17:57:35 +0800 From: Leo Yan To: James Clark Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org, acme@kernel.org, german.gomez@arm.com, mathieu.poirier@linaro.org, john.garry@huawei.com, Will Deacon , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register Message-ID: <20220518095735.GB430350@leoy-ThinkPad-X240s> References: <20220517102005.3022017-1-james.clark@arm.com> <20220517102005.3022017-5-james.clark@arm.com> <20220517131952.GE153558@leoy-ThinkPad-X240s> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, May 18, 2022 at 10:44:57AM +0100, James Clark wrote: [...] > >> + if (getauxval(AT_HWCAP) & HWCAP_SVE) > >> + attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG); > >> + > >> + /* > >> + * Check if the pmu supports perf extended regs, before > >> + * returning the register mask to sample. > >> + */ > >> + if (attr.sample_regs_user != PERF_REGS_MASK) { > >> + event_attr_init(&attr); > >> + fd = sys_perf_event_open(&attr, 0, -1, -1, 0); > >> + if (fd != -1) { > >> + close(fd); > >> + return attr.sample_regs_user; > >> + } > >> + } > > > > Just curious, since we can know SVE is supported from reading > > auxiliary value, can we directly return the register mask as below? > > > > PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG); > > I was trying to cover the case where the system supports SVE, but > the kernel doesn't have my changes to add the VG register yet. > > Technically I could just attempt to open the event without checking > for SVE first and see if it works or not. But I preferred to be > explicit so it's obvious why we're doing that. Understand; LGTM. Reviewed-by: Leo Yan From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16DA6C433F5 for ; Wed, 18 May 2022 09:58:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hQXyPPhZWYVKn3nVKAvi0fBVoxMg9JE1D6nIin6ckrY=; b=pTsO9akSTW/kEI papQT4Y0syGKjnWvx6uHKQaz2k5BqNwD0btmZiBKk2Duzx/8XdLiZL8o7SyQoj0rE5ajWq9TAFn1A xD+vzcFaFMxY0JkVvctWlNJAQC+3F4aEP2+wu39EAnwImgmsZbl6Qb4SjQTL71xQe6oLZ8R2lvqzw wEWE8H33QkWfbh2LIZF/imiz7RQLeZFjiZZogAAKWB5uZnCD369s92jLdC5OSZv0pdkDfKuRVQzMs 9IV7i5Ej3/TOT3tGY4q2jIoGISrF1e5RkqRKIRTsGzLunOajFwK/ZcWjQ8umaxhDe3pqsW4SH3VOt PZZn0+Q/jAojG85LEv7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrGR9-001Dej-Sj; Wed, 18 May 2022 09:57:48 +0000 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nrGR6-001Dcz-Tn for linux-arm-kernel@lists.infradead.org; Wed, 18 May 2022 09:57:46 +0000 Received: by mail-pg1-x52a.google.com with SMTP id v10so1665213pgl.11 for ; Wed, 18 May 2022 02:57:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=tc9+bvqYCqMUSJXb0nfQvcyKgjqV7Ocz6lWJsoBLOyQ=; b=am+ErBo1ZB0G/hYVBrcfY1g1WCS12VRPKU0MqxO1eFPOZMnO1PfcYkLY3tknTliDWw wBxg3LqZeg3ef3iGmyHkqn5SkRzAY1N5efuwoM7Ks+s38oDEoUJ05k6XRmLMQkuXE23j Ts51nH6G6UDl9pi4Jy0PmG8h/z4mbK/jT4Qi/3K+KzA3bYHCZ9R60zq74x+5dZidSzJ/ eWrgC3XfDdl4Mzm+4qDElEQJiU4NCV3owan7qspY8A0AndODbOwqRy2U50Dzxc/nU3as 5QpBsthosbzuJM2zWM2vnv8Db49i3VEpNpZVfEub7knFMi3uWBTIiRIJdYAeOvh0dkuN GJzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=tc9+bvqYCqMUSJXb0nfQvcyKgjqV7Ocz6lWJsoBLOyQ=; b=MVzjBt4MlMtlLNSMHsSzTVJTMlk2QTvNTbL8lqlfi7hXPMMuHPFe0i+jceuA7IBYr5 cMXFfDnf4J5SUlcgARkUbFcj1MK1bM6s3yo+qF3b60pkzuh5fKl0kDArUVIFcZtcyS0B RqPv6LZt/EygNpkukiPPlBb1jiICEy//mMq6LJqDzUrIP2a1/mMB2auuTj3z2gf3dv+2 d7epXeZT3BmBtvpaAyZmrlcZUd3JF8I+ujFcuXl5bqngMUHPeRtUMHBj1wIjcD4MMLEK fgeQus9/CICmxPJ/dgx0sNdPmVukQKog8irLcXVzZZaepIX/z1cf5v/FVuGHUK2f++I2 Iufw== X-Gm-Message-State: AOAM532jikMGjajnA+VnhUIgoDydB7dF2neHHbTCRRBtb0eU/3sEN5E7 YreiJgP0cZzFGleEH5N7RhnDEQ== X-Google-Smtp-Source: ABdhPJwxN17DvvwgA27WGHd/CQU6EzFpAzCAl1BFGWWAOX6ggp1eIFb0ryL4HktPXI/Dtai14vWbIA== X-Received: by 2002:a63:5a01:0:b0:3d8:22cb:9224 with SMTP id o1-20020a635a01000000b003d822cb9224mr22960915pgb.548.1652867863321; Wed, 18 May 2022 02:57:43 -0700 (PDT) Received: from leoy-ThinkPad-X240s ([137.184.121.66]) by smtp.gmail.com with ESMTPSA id s26-20020a056a001c5a00b005180ea859d7sm1419223pfw.123.2022.05.18.02.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 May 2022 02:57:42 -0700 (PDT) Date: Wed, 18 May 2022 17:57:35 +0800 From: Leo Yan To: James Clark Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, broonie@kernel.org, acme@kernel.org, german.gomez@arm.com, mathieu.poirier@linaro.org, john.garry@huawei.com, Will Deacon , Mike Leach , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 4/4] perf tools: arm64: Add support for VG register Message-ID: <20220518095735.GB430350@leoy-ThinkPad-X240s> References: <20220517102005.3022017-1-james.clark@arm.com> <20220517102005.3022017-5-james.clark@arm.com> <20220517131952.GE153558@leoy-ThinkPad-X240s> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220518_025745_023850_C2F47B2D X-CRM114-Status: GOOD ( 21.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 18, 2022 at 10:44:57AM +0100, James Clark wrote: [...] > >> + if (getauxval(AT_HWCAP) & HWCAP_SVE) > >> + attr.sample_regs_user |= SMPL_REG_MASK(PERF_REG_ARM64_VG); > >> + > >> + /* > >> + * Check if the pmu supports perf extended regs, before > >> + * returning the register mask to sample. > >> + */ > >> + if (attr.sample_regs_user != PERF_REGS_MASK) { > >> + event_attr_init(&attr); > >> + fd = sys_perf_event_open(&attr, 0, -1, -1, 0); > >> + if (fd != -1) { > >> + close(fd); > >> + return attr.sample_regs_user; > >> + } > >> + } > > > > Just curious, since we can know SVE is supported from reading > > auxiliary value, can we directly return the register mask as below? > > > > PERF_REGS_MASK | SMPL_REG_MASK(PERF_REG_ARM64_VG); > > I was trying to cover the case where the system supports SVE, but > the kernel doesn't have my changes to add the VG register yet. > > Technically I could just attempt to open the event without checking > for SVE first and see if it works or not. But I preferred to be > explicit so it's obvious why we're doing that. Understand; LGTM. Reviewed-by: Leo Yan _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel