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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT019.mail.protection.outlook.com (10.13.176.158) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5273.14 via Frontend Transport; Wed, 18 May 2022 16:27:15 +0000 Received: from sp5-759chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Wed, 18 May 2022 11:27:11 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , , Suravee Suthikulpanit Subject: [PATCH v5 07/17] KVM: SVM: Adding support for configuring x2APIC MSRs interception Date: Wed, 18 May 2022 11:26:42 -0500 Message-ID: <20220518162652.100493-8-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220518162652.100493-1-suravee.suthikulpanit@amd.com> References: <20220518162652.100493-1-suravee.suthikulpanit@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d8a2bd26-1082-4298-7ab8-08da38eb4525 X-MS-TrafficTypeDiagnostic: DM5PR12MB2549:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 May 2022 16:27:15.4119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d8a2bd26-1082-4298-7ab8-08da38eb4525 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2549 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When enabling x2APIC virtualization (x2AVIC), the interception of x2APIC MSRs must be disabled to let the hardware virtualize guest MSR accesses. Current implementation keeps track of list of MSR interception state in the svm_direct_access_msrs array. Therefore, extends the array to include x2APIC MSRs. Reviewed-by: Maxim Levitsky Signed-off-by: Suravee Suthikulpanit --- arch/x86/kvm/svm/svm.c | 25 +++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 4 ++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 196bca5751a1..2cf6710333f8 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -100,6 +100,31 @@ static const struct svm_direct_access_msrs { { .index = MSR_IA32_CR_PAT, .always = false }, { .index = MSR_AMD64_SEV_ES_GHCB, .always = true }, { .index = MSR_TSC_AUX, .always = false }, + { .index = (APIC_BASE_MSR + APIC_ID), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LVR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_TASKPRI), .always = false }, + { .index = (APIC_BASE_MSR + APIC_ARBPRI), .always = false }, + { .index = (APIC_BASE_MSR + APIC_PROCPRI), .always = false }, + { .index = (APIC_BASE_MSR + APIC_EOI), .always = false }, + { .index = (APIC_BASE_MSR + APIC_RRR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LDR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_DFR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_SPIV), .always = false }, + { .index = (APIC_BASE_MSR + APIC_ISR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_TMR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_IRR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_ESR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_ICR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_ICR2), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LVTT), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LVTTHMR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LVTPC), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LVT0), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LVT1), .always = false }, + { .index = (APIC_BASE_MSR + APIC_LVTERR), .always = false }, + { .index = (APIC_BASE_MSR + APIC_TMICT), .always = false }, + { .index = (APIC_BASE_MSR + APIC_TMCCT), .always = false }, + { .index = (APIC_BASE_MSR + APIC_TDCR), .always = false }, { .index = MSR_INVALID, .always = false }, }; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 1731c1f3884b..16f1d117c98b 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -29,8 +29,8 @@ #define IOPM_SIZE PAGE_SIZE * 3 #define MSRPM_SIZE PAGE_SIZE * 2 -#define MAX_DIRECT_ACCESS_MSRS 21 -#define MSRPM_OFFSETS 16 +#define MAX_DIRECT_ACCESS_MSRS 46 +#define MSRPM_OFFSETS 32 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; extern bool npt_enabled; extern int vgif; -- 2.25.1