From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Zhengxun <zhengxunli.mxic@gmail.com>
Cc: linux-mtd@lists.infradead.org, zhengxunli@mxic.com.tw
Subject: Re: [PATCH v2 1/4] mtd: spinand: Add support continuous read mode
Date: Thu, 19 May 2022 18:08:50 +0200 [thread overview]
Message-ID: <20220519180850.2190b171@xps-13> (raw)
In-Reply-To: <20220209091022.30155-2-zhengxunli.mxic@gmail.com>
Hi Zhengxun,
zhengxunli.mxic@gmail.com wrote on Wed, 9 Feb 2022 17:10:19 +0800:
> The patch supports setting the "CONT" bit of the configuration
add support for
> register and adding a continuous read mode flag for identification.
It's not really a configuration register, it's capability flag.
>
> Signed-off-by: Zhengxun <zhengxunli.mxic@gmail.com>
> ---
> drivers/mtd/nand/spi/core.c | 11 +++++++++++
> include/linux/mtd/spinand.h | 2 ++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
> index 2c8685f1f2fa..dc2e1dc1dbee 100644
> --- a/drivers/mtd/nand/spi/core.c
> +++ b/drivers/mtd/nand/spi/core.c
> @@ -193,6 +193,17 @@ static int spinand_init_quad_enable(struct spinand_device *spinand)
> enable ? CFG_QUAD_ENABLE : 0);
> }
>
> +static int spinand_continuous_read_enable(struct spinand_device *spinand)
> +{
> + return spinand_upd_cfg(spinand, CFG_CONT_READ_ENABLE,
> + CFG_CONT_READ_ENABLE);
> +}
> +
> +static int spinand_continuous_read_disable(struct spinand_device *spinand)
> +{
> + return spinand_upd_cfg(spinand, CFG_CONT_READ_ENABLE, 0);
> +}
> +
> static int spinand_ecc_enable(struct spinand_device *spinand,
> bool enable)
> {
> diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
> index 6988956b8492..04be10ec8fb0 100644
> --- a/include/linux/mtd/spinand.h
> +++ b/include/linux/mtd/spinand.h
> @@ -154,6 +154,7 @@
> #define REG_CFG 0xb0
> #define CFG_OTP_ENABLE BIT(6)
> #define CFG_ECC_ENABLE BIT(4)
> +#define CFG_CONT_READ_ENABLE BIT(2)
> #define CFG_QUAD_ENABLE BIT(0)
>
> /* status register */
> @@ -307,6 +308,7 @@ struct spinand_ecc_info {
>
> #define SPINAND_HAS_QE_BIT BIT(0)
> #define SPINAND_HAS_CR_FEAT_BIT BIT(1)
> +#define SPINAND_HAS_CONT_READ_BIT BIT(2)
Not related to this patch.
>
> /**
> * struct spinand_ondie_ecc_conf - private SPI-NAND on-die ECC engine structure
Thanks,
Miquèl
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next prev parent reply other threads:[~2022-05-19 16:09 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 9:10 [PATCH v2 0/4] mtd: spinand: Add continuous read mode support Zhengxun
2022-02-09 9:10 ` [PATCH v2 1/4] mtd: spinand: Add support continuous read mode Zhengxun
2022-05-19 16:08 ` Miquel Raynal [this message]
2022-02-09 9:10 ` [PATCH v2 2/4] mtd: spinand: Add continuous read state Zhengxun
2022-02-09 9:10 ` [PATCH v2 3/4] mtd: spinand: Add support continuous read operation Zhengxun
2022-05-19 16:06 ` Miquel Raynal
2022-02-09 9:10 ` [PATCH v2 4/4] mtd: spinand: macronix: Add continuous read support for MX35LF2GE4AD Zhengxun
2022-05-19 16:07 ` Miquel Raynal
2023-02-09 12:08 [PATCH v2 0/4] mtd: spinand: Add continuous read mode support Jaime Liao
2023-02-09 12:08 ` [PATCH v2 1/4] mtd: spinand: Add support continuous read mode Jaime Liao
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