From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B51ACC433EF for ; Fri, 20 May 2022 01:59:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344656AbiETB7B (ORCPT ); Thu, 19 May 2022 21:59:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344647AbiETB7A (ORCPT ); Thu, 19 May 2022 21:59:00 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7041EBE88 for ; Thu, 19 May 2022 18:58:57 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id p4so10580087lfg.4 for ; Thu, 19 May 2022 18:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L3xLjgH+8H4EuxOCFISCfGIFUbJpaGjNZmkPZUl6M0Q=; b=k+kTD0BsQCqxWnJPhXthgz2W6eu3qIVt77qqLex2Bm3TCaOzDhrZtAgExVL6khTO+o oXddtjn+sECi0SDCRC2JVCSfKRZUs7HOkmVJgZ016IFRjd5WnFnyYitpJYbbbCV3CqGX 28AX8N5PBW0LTf2zhJR1OsxxigkffC+L4DGrb7QJZDGQf9gw3g0EoiYj8f55LfSOXx5Y 9ssSdZvZHdTbwJmHAkBsE/o+tasyZBit3G6wW3r6iTLvvTvwGC+bzQoL6X4YTM4/tIWh ENK19yf9cWCpI8ByxGQft4AWBf4k9702SvUjZWe0qahuhJn23lTEUCajOPgCyeZZWs1N qMKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L3xLjgH+8H4EuxOCFISCfGIFUbJpaGjNZmkPZUl6M0Q=; b=hLdYc8k7RGxfm1f/vyyLIEa3Xz53HOYb+UEibpwG84q5ezHD9S/54U4j3GMZUnQ+yC otRYRsSMs/v6D4XKdkbuDKHh0jSD/WFnJyAGf3weDNA5YXT3k6Sm7WJUM55SpKvcJAEC HdEj3a3+bo48jJby2F4s9rClLpM4mlDhSrRiCT2bopaLQgm7aoZe9o8wiAkjk5+pEcyq rXd2W6HT77LuqBIFDG5sijnLoTAt6E36Ki3Ysq6xGOI281mS4jVKTMTJKB79jWA/Z3QE 54hw5EG4M8EKxyx4dUI3ZsuWubRUAFXiHUMYtL0nStYpnAst/V9/MFsqcw1N5lq/FHQ6 slJg== X-Gm-Message-State: AOAM5317TtK8WuNIxl4d3L+h8Lg3AVFBwo8Bc2YPECl6lfwmoM8OnS/m JEi8BMa6oQVhLiLh11jEq/uH7w== X-Google-Smtp-Source: ABdhPJxPgbBdldNejWDEpLjukmM3vcPsaxAe8mGP1132d9rKDzXNSGjh6VcswmPGM0ApTWZTuHl2Sg== X-Received: by 2002:a19:c20b:0:b0:477:bec9:4f99 with SMTP id l11-20020a19c20b000000b00477bec94f99mr5352313lfc.274.1653011935961; Thu, 19 May 2022 18:58:55 -0700 (PDT) Received: from eriador.lan ([2001:470:dd84:abc0::8a5]) by smtp.gmail.com with ESMTPSA id u28-20020ac24c3c000000b0047255d21192sm467370lfq.193.2022.05.19.18.58.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 18:58:55 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org, Prasad Malisetty Subject: [PATCH v7 6/6] PCI: qcom: Drop manual pipe_clk_src handling Date: Fri, 20 May 2022 04:58:44 +0300 Message-Id: <20220520015844.1190511-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220520015844.1190511-1-dmitry.baryshkov@linaro.org> References: <20220520015844.1190511-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Manual reparenting of pipe_clk_src is being replaced with the parking of the clock with clk_disable()/clk_enable() in the phy driver. Drop redundant code switching of the pipe clock between the PHY clock source and the safe bi_tcxo. Cc: Prasad Malisetty Reviewed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 39 +------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 91e58edc7ea9..e83085e1bf4b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -164,9 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk_src; - struct clk *phy_pipe_clk; - struct clk *ref_clk_src; }; union qcom_pcie_resources { @@ -192,7 +189,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; unsigned int has_aggre0_clk:1; @@ -1158,20 +1154,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->cfg->pipe_clk_need_muxing) { - res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); - if (IS_ERR(res->pipe_clk_src)) - return PTR_ERR(res->pipe_clk_src); - - res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe"); - if (IS_ERR(res->phy_pipe_clk)) - return PTR_ERR(res->phy_pipe_clk); - - res->ref_clk_src = devm_clk_get(dev, "ref"); - if (IS_ERR(res->ref_clk_src)) - return PTR_ERR(res->ref_clk_src); - } - return 0; } @@ -1189,10 +1171,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1254,18 +1232,8 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; clk_bulk_disable_unprepare(res->num_clks, res->clks); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -} -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - - return 0; + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } static int qcom_pcie_link_up(struct dw_pcie *pci) @@ -1441,7 +1409,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1450,7 +1417,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, }; @@ -1488,7 +1454,6 @@ static const struct qcom_pcie_cfg sm8250_cfg = { static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre0_clk = true, .has_aggre1_clk = true, }; @@ -1496,14 +1461,12 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, - .pipe_clk_need_muxing = true, }; static const struct qcom_pcie_cfg sc8180x_cfg = { -- 2.35.1