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* [PATCH v6 0/6] RZN1 USB Host support
@ 2022-05-20  9:41 Herve Codina
  2022-05-20  9:41 ` [PATCH v6 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
                   ` (7 more replies)
  0 siblings, 8 replies; 13+ messages in thread
From: Herve Codina @ 2022-05-20  9:41 UTC (permalink / raw)
  To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński
  Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
	linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
	Miquel Raynal, Herve Codina

Hi,

This series add support for the USB Host controllers available on
RZN1 (r9a06g032) SOC.

These USB Host controllers are PCI OHCI/EHCI controllers located
behind a bridge.

Regards,
Herve

Changes v2:
- Convert bindings to json-schema
- Update clocks description
- Remove unneeded '.compatible = "renesas,pci-r9a06g032"'

Changes v3:
- Remove the unneeded patch that calls clk_bulk_prepare_enable()
- Rework the device tree binding (conversion from .txt and RZ/N1 support)
- Use the RZ/N1 SOCs family only in the driver match compatible string.
- Enable PM and PM_GENERIC_DOMAIN for RZ/N1 and add the missing
  '#power-domain-cells' in sysctrl node.

Changes v4:
- Remove patches related to PM enable and #pwower-domain-cells as they
  will be handle out of this series.
- Add Bob's reviewed-by on patch 1
- Add Geert's reviewed by on patch 1 and 6
- Rename clocks and make the 'resets' property optional on RZ/N1 family
- Reword some commit logs and titles
- Fix dst node location (sort by node names or unit addresses)
- Fix the USB PHY node name

Changes v5:
- Rename clocks ("usb_" prefix removed)
- Add Geert's reviewed-by on patch 2, 3, 4 and 5

Changes v6:
- Include schema optionnal part (ie 'if:') in a 'allOf:' block
- Modify commit log on commit 2/6

Herve Codina (6):
  dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
  dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for
    r9a06g032
  PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
  ARM: dts: r9a06g032: Add internal PCI bridge node
  ARM: dts: r9a06g032: Add USB PHY DT support
  ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY

 .../devicetree/bindings/pci/pci-rcar-gen2.txt |  84 --------
 .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 186 ++++++++++++++++++
 arch/arm/boot/dts/r9a06g032.dtsi              |  47 +++++
 drivers/pci/controller/pci-rcar-gen2.c        |   1 +
 4 files changed, 234 insertions(+), 84 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
 create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml

-- 
2.35.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [PATCH v6 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
@ 2022-05-20  9:41 ` Herve Codina
  2022-05-20  9:41 ` [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 13+ messages in thread
From: Herve Codina @ 2022-05-20  9:41 UTC (permalink / raw)
  To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński
  Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
	linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
	Miquel Raynal, Herve Codina

Convert Renesas PCI bridge bindings documentation to json-schema.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 .../devicetree/bindings/pci/pci-rcar-gen2.txt |  84 ----------
 .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 156 ++++++++++++++++++
 2 files changed, 156 insertions(+), 84 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
 create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml

diff --git a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt b/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
deleted file mode 100644
index aeba38f0a387..000000000000
--- a/Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-Renesas AHB to PCI bridge
--------------------------
-
-This is the bridge used internally to connect the USB controllers to the
-AHB. There is one bridge instance per USB port connected to the internal
-OHCI and EHCI controllers.
-
-Required properties:
-- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
-	      "renesas,pci-r8a7743" for the R8A7743 SoC;
-	      "renesas,pci-r8a7744" for the R8A7744 SoC;
-	      "renesas,pci-r8a7745" for the R8A7745 SoC;
-	      "renesas,pci-r8a7790" for the R8A7790 SoC;
-	      "renesas,pci-r8a7791" for the R8A7791 SoC;
-	      "renesas,pci-r8a7793" for the R8A7793 SoC;
-	      "renesas,pci-r8a7794" for the R8A7794 SoC;
-	      "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
-				      RZ/G1 compatible device.
-
-
-	      When compatible with the generic version, nodes must list the
-	      SoC-specific version corresponding to the platform first
-	      followed by the generic version.
-
-- reg:	A list of physical regions to access the device: the first is
-	the operational registers for the OHCI/EHCI controllers and the
-	second is for the bridge configuration and control registers.
-- interrupts: interrupt for the device.
-- clocks: The reference to the device clock.
-- bus-range: The PCI bus number range; as this is a single bus, the range
-	     should be specified as the same value twice.
-- #address-cells: must be 3.
-- #size-cells: must be 2.
-- #interrupt-cells: must be 1.
-- interrupt-map: standard property used to define the mapping of the PCI
-  interrupts to the GIC interrupts.
-- interrupt-map-mask: standard property that helps to define the interrupt
-  mapping.
-
-Optional properties:
-- dma-ranges: a single range for the inbound memory region. If not supplied,
-  defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
-  allowed combinations of address and size.
-
-Example SoC configuration:
-
-	pci0: pci@ee090000  {
-		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
-		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
-		reg = <0x0 0xee090000 0x0 0xc00>,
-		      <0x0 0xee080000 0x0 0x1100>;
-		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
-		status = "disabled";
-
-		bus-range = <0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		#interrupt-cells = <1>;
-		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
-		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
-
-		usb@1,0 {
-			reg = <0x800 0 0 0 0>;
-			phys = <&usb0 0>;
-			phy-names = "usb";
-		};
-
-		usb@2,0 {
-			reg = <0x1000 0 0 0 0>;
-			phys = <&usb0 0>;
-			phy-names = "usb";
-		};
-	};
-
-Example board setup:
-
-&pci0 {
-	status = "okay";
-	pinctrl-0 = <&usb0_pins>;
-	pinctrl-names = "default";
-};
diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
new file mode 100644
index 000000000000..494eb975c146
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas AHB to PCI bridge
+
+maintainers:
+  - Marek Vasut <marek.vasut+renesas@gmail.com>
+  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+description: |
+  This is the bridge used internally to connect the USB controllers to the
+  AHB. There is one bridge instance per USB port connected to the internal
+  OHCI and EHCI controllers.
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - renesas,pci-r8a7742      # RZ/G1H
+              - renesas,pci-r8a7743      # RZ/G1M
+              - renesas,pci-r8a7744      # RZ/G1N
+              - renesas,pci-r8a7745      # RZ/G1E
+              - renesas,pci-r8a7790      # R-Car H2
+              - renesas,pci-r8a7791      # R-Car M2-W
+              - renesas,pci-r8a7793      # R-Car M2-N
+              - renesas,pci-r8a7794      # R-Car E2
+          - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+
+  reg:
+    items:
+      - description: Operational registers for the OHCI/EHCI controllers.
+      - description: Bridge configuration and control registers.
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Device clock
+
+  clock-names:
+    items:
+      - const: pclk
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  bus-range:
+    description: |
+      The PCI bus number range; as this is a single bus, the range
+      should be specified as the same value twice.
+
+  dma-ranges:
+    description: |
+      A single range for the inbound memory region. If not supplied,
+      defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
+      the allowed combinations of address and size.
+    maxItems: 1
+
+patternProperties:
+  'usb@[0-1],0':
+    type: object
+
+    description:
+      This a USB controller PCI device
+
+    properties:
+      reg:
+        description:
+          Identify the correct bus, device and function number in the
+          form <bdf 0 0 0 0>.
+
+        items:
+          minItems: 5
+          maxItems: 5
+
+      phys:
+        description:
+          Reference to the USB phy
+        maxItems: 1
+
+      phy-names:
+        maxItems: 1
+
+    required:
+      - reg
+      - phys
+      - phy-names
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-map
+  - interrupt-map-mask
+  - clocks
+  - resets
+  - power-domains
+  - bus-range
+  - "#address-cells"
+  - "#size-cells"
+  - "#interrupt-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+    #include <dt-bindings/power/r8a7790-sysc.h>
+
+    pci@ee090000  {
+        compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+        device_type = "pci";
+        reg = <0xee090000 0xc00>,
+              <0xee080000 0x1100>;
+        clocks = <&cpg CPG_MOD 703>;
+        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+        resets = <&cpg 703>;
+        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+        bus-range = <0 0>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>;
+        dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>;
+        interrupt-map-mask = <0xf800 0 0 0x7>;
+        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+        usb@1,0 {
+            reg = <0x800 0 0 0 0>;
+            phys = <&usb0 0>;
+            phy-names = "usb";
+        };
+
+        usb@2,0 {
+            reg = <0x1000 0 0 0 0>;
+            phys = <&usb0 0>;
+            phy-names = "usb";
+        };
+    };
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
  2022-05-20  9:41 ` [PATCH v6 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
@ 2022-05-20  9:41 ` Herve Codina
  2022-05-26 20:54   ` Rob Herring
  2022-05-20  9:41 ` [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Herve Codina
                   ` (5 subsequent siblings)
  7 siblings, 1 reply; 13+ messages in thread
From: Herve Codina @ 2022-05-20  9:41 UTC (permalink / raw)
  To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński
  Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
	linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
	Miquel Raynal, Herve Codina

Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
present in the R-Car Gen2 family.
Compared to the R-Car Gen2 family, it needs three clocks instead of
one.

The 'resets' property for the RZ/N1 family is not required.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 50 +++++++++++++++----
 1 file changed, 40 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
index 494eb975c146..0f18cceba3d5 100644
--- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
@@ -15,9 +15,6 @@ description: |
   AHB. There is one bridge instance per USB port connected to the internal
   OHCI and EHCI controllers.
 
-allOf:
-  - $ref: /schemas/pci/pci-bus.yaml#
-
 properties:
   compatible:
     oneOf:
@@ -32,6 +29,10 @@ properties:
               - renesas,pci-r8a7793      # R-Car M2-N
               - renesas,pci-r8a7794      # R-Car E2
           - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+      - items:
+          - enum:
+              - renesas,pci-r9a06g032     # RZ/N1D
+          - const: renesas,pci-rzn1       # RZ/N1
 
   reg:
     items:
@@ -41,13 +42,9 @@ properties:
   interrupts:
     maxItems: 1
 
-  clocks:
-    items:
-      - description: Device clock
+  clocks: true
 
-  clock-names:
-    items:
-      - const: pclk
+  clock-names: true
 
   resets:
     maxItems: 1
@@ -106,13 +103,46 @@ required:
   - interrupt-map
   - interrupt-map-mask
   - clocks
-  - resets
   - power-domains
   - bus-range
   - "#address-cells"
   - "#size-cells"
   - "#interrupt-cells"
 
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,pci-rzn1
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Internal bus clock (AHB) for HOST
+            - description: Internal bus clock (AHB) Power Management
+            - description: PCI clock for USB subsystem
+        clock-names:
+          items:
+            - const: hclkh
+            - const: hclkpm
+            - const: pciclk
+      required:
+        - clock-names
+    else:
+      properties:
+        clocks:
+          items:
+            - description: Device clock
+        clock-names:
+          items:
+            - const: pclk
+      required:
+        - resets
+
 unevaluatedProperties: false
 
 examples:
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
  2022-05-20  9:41 ` [PATCH v6 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
  2022-05-20  9:41 ` [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
@ 2022-05-20  9:41 ` Herve Codina
  2022-05-26 20:55   ` Rob Herring
  2022-05-20  9:41 ` [PATCH v6 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
                   ` (4 subsequent siblings)
  7 siblings, 1 reply; 13+ messages in thread
From: Herve Codina @ 2022-05-20  9:41 UTC (permalink / raw)
  To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński
  Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
	linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
	Miquel Raynal, Herve Codina

Add the Renesas RZ/N1 SOCs family support to the Renesas R-Car Gen2
PCI bridge driver.

The Renesas RZ/N1 SOCs internal PCI bridge is compatible with the one
available in the R-Car Gen2 family.

Tested with the RZ/N1D (R9A06G032) SOC.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pci/controller/pci-rcar-gen2.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/pci-rcar-gen2.c b/drivers/pci/controller/pci-rcar-gen2.c
index 35804ea394fd..839695791757 100644
--- a/drivers/pci/controller/pci-rcar-gen2.c
+++ b/drivers/pci/controller/pci-rcar-gen2.c
@@ -328,6 +328,7 @@ static const struct of_device_id rcar_pci_of_match[] = {
 	{ .compatible = "renesas,pci-r8a7791", },
 	{ .compatible = "renesas,pci-r8a7794", },
 	{ .compatible = "renesas,pci-rcar-gen2", },
+	{ .compatible = "renesas,pci-rzn1", },
 	{ },
 };
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [PATCH v6 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
                   ` (2 preceding siblings ...)
  2022-05-20  9:41 ` [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Herve Codina
@ 2022-05-20  9:41 ` Herve Codina
  2022-05-20  9:41 ` [PATCH v6 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
                   ` (3 subsequent siblings)
  7 siblings, 0 replies; 13+ messages in thread
From: Herve Codina @ 2022-05-20  9:41 UTC (permalink / raw)
  To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński
  Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
	linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
	Miquel Raynal, Herve Codina

Add the device node for the r9a06g032 internal PCI bridge device.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 20286433d3c6..45944f849190 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -94,6 +94,35 @@ sysctrl: system-controller@4000c000 {
 			clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
 		};
 
+		pci_usb: pci@40030000 {
+			compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
+			device_type = "pci";
+			clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+				 <&sysctrl R9A06G032_HCLK_USBPM>,
+				 <&sysctrl R9A06G032_CLK_PCI_USB>;
+			clock-names = "hclkh", "hclkpm", "pciclk";
+			power-domains = <&sysctrl>;
+			reg = <0x40030000 0xc00>,
+			      <0x40020000 0x1100>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+
+			bus-range = <0 0>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
+			/* Should map all possible DDR as inbound ranges, but
+			 * the IP only supports a 256MB, 512MB, or 1GB window.
+			 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
+			 */
+			dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
+			interrupt-map-mask = <0xf800 0 0 0x7>;
+			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+					 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
+					 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		uart0: serial@40060000 {
 			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
 			reg = <0x40060000 0x400>;
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [PATCH v6 5/6] ARM: dts: r9a06g032: Add USB PHY DT support
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
                   ` (3 preceding siblings ...)
  2022-05-20  9:41 ` [PATCH v6 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
@ 2022-05-20  9:41 ` Herve Codina
  2022-05-20  9:41 ` [PATCH v6 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 13+ messages in thread
From: Herve Codina @ 2022-05-20  9:41 UTC (permalink / raw)
  To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński
  Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
	linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
	Miquel Raynal, Herve Codina

Define the r9a06g032 generic part of the USB PHY device node.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 45944f849190..8cedc08ba3b9 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -255,4 +255,10 @@ timer {
 			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	usbphy: usb-phy {
+		#phy-cells = <0>;
+		compatible = "usb-nop-xceiv";
+		status = "disabled";
+	};
 };
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [PATCH v6 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
                   ` (4 preceding siblings ...)
  2022-05-20  9:41 ` [PATCH v6 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
@ 2022-05-20  9:41 ` Herve Codina
  2022-05-20 12:12 ` [PATCH v6 0/6] RZN1 USB Host support Geert Uytterhoeven
  2022-06-23 22:39 ` Bjorn Helgaas
  7 siblings, 0 replies; 13+ messages in thread
From: Herve Codina @ 2022-05-20  9:41 UTC (permalink / raw)
  To: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński
  Cc: Rob Herring, linux-pci, linux-renesas-soc, devicetree,
	linux-kernel, Sergey Shtylyov, Thomas Petazzoni, Clement Leger,
	Miquel Raynal, Herve Codina

Describe the PCI USB devices that are behind the PCI bridge, adding
necessary links to the USB PHY device.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 8cedc08ba3b9..db1e35381d9b 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -121,6 +121,18 @@ pci_usb: pci@40030000 {
 			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
 					 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
 					 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+			usb@1,0 {
+				reg = <0x800 0 0 0 0>;
+				phys = <&usbphy>;
+				phy-names = "usb";
+			};
+
+			usb@2,0 {
+				reg = <0x1000 0 0 0 0>;
+				phys = <&usbphy>;
+				phy-names = "usb";
+			};
 		};
 
 		uart0: serial@40060000 {
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* Re: [PATCH v6 0/6] RZN1 USB Host support
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
                   ` (5 preceding siblings ...)
  2022-05-20  9:41 ` [PATCH v6 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
@ 2022-05-20 12:12 ` Geert Uytterhoeven
  2022-05-20 12:40   ` Herve Codina
  2022-06-23 22:39 ` Bjorn Helgaas
  7 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2022-05-20 12:12 UTC (permalink / raw)
  To: Herve Codina
  Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
	linux-pci, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
	Clement Leger, Miquel Raynal

Hi Hervé,

On Fri, May 20, 2022 at 11:42 AM Herve Codina <herve.codina@bootlin.com> wrote:
> This series add support for the USB Host controllers available on
> RZN1 (r9a06g032) SOC.
>
> These USB Host controllers are PCI OHCI/EHCI controllers located
> behind a bridge.

Thanks for your series!

> Herve Codina (6):
>   dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
>   dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for
>     r9a06g032
>   PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
>   ARM: dts: r9a06g032: Add internal PCI bridge node
>   ARM: dts: r9a06g032: Add USB PHY DT support
>   ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY

As I had applied v5 of the last 3 patches to renesas-devel, and they
are already present in soc/for-next, there is no need to resend them.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v6 0/6] RZN1 USB Host support
  2022-05-20 12:12 ` [PATCH v6 0/6] RZN1 USB Host support Geert Uytterhoeven
@ 2022-05-20 12:40   ` Herve Codina
  0 siblings, 0 replies; 13+ messages in thread
From: Herve Codina @ 2022-05-20 12:40 UTC (permalink / raw)
  To: Geert Uytterhoeven
  Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
	linux-pci, Linux-Renesas,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	Linux Kernel Mailing List, Sergey Shtylyov, Thomas Petazzoni,
	Clement Leger, Miquel Raynal

On Fri, 20 May 2022 14:12:10 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:

> Hi Hervé,
> 
> On Fri, May 20, 2022 at 11:42 AM Herve Codina <herve.codina@bootlin.com> wrote:
> > This series add support for the USB Host controllers available on
> > RZN1 (r9a06g032) SOC.
> >
> > These USB Host controllers are PCI OHCI/EHCI controllers located
> > behind a bridge.  
> 
> Thanks for your series!
> 
> > Herve Codina (6):
> >   dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
> >   dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for
> >     r9a06g032
> >   PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
> >   ARM: dts: r9a06g032: Add internal PCI bridge node
> >   ARM: dts: r9a06g032: Add USB PHY DT support
> >   ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY  
> 
> As I had applied v5 of the last 3 patches to renesas-devel, and they
> are already present in soc/for-next, there is no need to resend them.

Thanks. I note that for the next version of this series if needed.

Regards,
Hervé

-- 
Hervé Codina, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032
  2022-05-20  9:41 ` [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
@ 2022-05-26 20:54   ` Rob Herring
  0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2022-05-26 20:54 UTC (permalink / raw)
  To: Herve Codina
  Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński, linux-pci,
	linux-renesas-soc, devicetree, linux-kernel, Sergey Shtylyov,
	Thomas Petazzoni, Clement Leger, Miquel Raynal

On Fri, May 20, 2022 at 11:41:51AM +0200, Herve Codina wrote:
> Add internal PCI bridge support for the r9a06g032 SOC. The Renesas
> RZ/N1D (R9A06G032) internal PCI bridge is compatible with the one
> present in the R-Car Gen2 family.
> Compared to the R-Car Gen2 family, it needs three clocks instead of
> one.
> 
> The 'resets' property for the RZ/N1 family is not required.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 50 +++++++++++++++----
>  1 file changed, 40 insertions(+), 10 deletions(-)

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
  2022-05-20  9:41 ` [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Herve Codina
@ 2022-05-26 20:55   ` Rob Herring
  0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2022-05-26 20:55 UTC (permalink / raw)
  To: Herve Codina
  Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński, linux-pci,
	linux-renesas-soc, devicetree, linux-kernel, Sergey Shtylyov,
	Thomas Petazzoni, Clement Leger, Miquel Raynal

On Fri, May 20, 2022 at 11:41:52AM +0200, Herve Codina wrote:
> Add the Renesas RZ/N1 SOCs family support to the Renesas R-Car Gen2
> PCI bridge driver.
> 
> The Renesas RZ/N1 SOCs internal PCI bridge is compatible with the one
> available in the R-Car Gen2 family.
> 
> Tested with the RZ/N1D (R9A06G032) SOC.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/pci/controller/pci-rcar-gen2.c | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v6 0/6] RZN1 USB Host support
  2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
                   ` (6 preceding siblings ...)
  2022-05-20 12:12 ` [PATCH v6 0/6] RZN1 USB Host support Geert Uytterhoeven
@ 2022-06-23 22:39 ` Bjorn Helgaas
  2022-06-23 22:40   ` Bjorn Helgaas
  7 siblings, 1 reply; 13+ messages in thread
From: Bjorn Helgaas @ 2022-06-23 22:39 UTC (permalink / raw)
  To: Herve Codina
  Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
	linux-pci, linux-renesas-soc, devicetree, linux-kernel,
	Sergey Shtylyov, Thomas Petazzoni, Clement Leger, Miquel Raynal

On Fri, May 20, 2022 at 11:41:49AM +0200, Herve Codina wrote:
> Hi,
> 
> This series add support for the USB Host controllers available on
> RZN1 (r9a06g032) SOC.
> 
> These USB Host controllers are PCI OHCI/EHCI controllers located
> behind a bridge.
> 
> Regards,
> Herve
> 
> Changes v2:
> - Convert bindings to json-schema
> - Update clocks description
> - Remove unneeded '.compatible = "renesas,pci-r9a06g032"'
> 
> Changes v3:
> - Remove the unneeded patch that calls clk_bulk_prepare_enable()
> - Rework the device tree binding (conversion from .txt and RZ/N1 support)
> - Use the RZ/N1 SOCs family only in the driver match compatible string.
> - Enable PM and PM_GENERIC_DOMAIN for RZ/N1 and add the missing
>   '#power-domain-cells' in sysctrl node.
> 
> Changes v4:
> - Remove patches related to PM enable and #pwower-domain-cells as they
>   will be handle out of this series.
> - Add Bob's reviewed-by on patch 1
> - Add Geert's reviewed by on patch 1 and 6
> - Rename clocks and make the 'resets' property optional on RZ/N1 family
> - Reword some commit logs and titles
> - Fix dst node location (sort by node names or unit addresses)
> - Fix the USB PHY node name
> 
> Changes v5:
> - Rename clocks ("usb_" prefix removed)
> - Add Geert's reviewed-by on patch 2, 3, 4 and 5
> 
> Changes v6:
> - Include schema optionnal part (ie 'if:') in a 'allOf:' block
> - Modify commit log on commit 2/6
> 
> Herve Codina (6):
>   dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
>   dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for
>     r9a06g032
>   PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string

Applied the first three patches (above) to pci/ctrl/rcar-gen2 for
v5.20, thank you!

>   ARM: dts: r9a06g032: Add internal PCI bridge node
>   ARM: dts: r9a06g032: Add USB PHY DT support
>   ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
> 
>  .../devicetree/bindings/pci/pci-rcar-gen2.txt |  84 --------
>  .../bindings/pci/renesas,pci-rcar-gen2.yaml   | 186 ++++++++++++++++++
>  arch/arm/boot/dts/r9a06g032.dtsi              |  47 +++++
>  drivers/pci/controller/pci-rcar-gen2.c        |   1 +
>  4 files changed, 234 insertions(+), 84 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt
>  create mode 100644 Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml
> 
> -- 
> 2.35.1
> 

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH v6 0/6] RZN1 USB Host support
  2022-06-23 22:39 ` Bjorn Helgaas
@ 2022-06-23 22:40   ` Bjorn Helgaas
  0 siblings, 0 replies; 13+ messages in thread
From: Bjorn Helgaas @ 2022-06-23 22:40 UTC (permalink / raw)
  To: Herve Codina
  Cc: Marek Vasut, Yoshihiro Shimoda, Bjorn Helgaas, Rob Herring,
	Krzysztof Kozlowski, Geert Uytterhoeven, Magnus Damm,
	Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
	linux-pci, linux-renesas-soc, devicetree, linux-kernel,
	Sergey Shtylyov, Thomas Petazzoni, Clement Leger, Miquel Raynal

On Thu, Jun 23, 2022 at 05:39:14PM -0500, Bjorn Helgaas wrote:
> On Fri, May 20, 2022 at 11:41:49AM +0200, Herve Codina wrote:
> > Hi,
> > 
> > This series add support for the USB Host controllers available on
> > RZN1 (r9a06g032) SOC.
> > 
> > These USB Host controllers are PCI OHCI/EHCI controllers located
> > behind a bridge.
> > 
> > Regards,
> > Herve
> > 
> > Changes v2:
> > - Convert bindings to json-schema
> > - Update clocks description
> > - Remove unneeded '.compatible = "renesas,pci-r9a06g032"'
> > 
> > Changes v3:
> > - Remove the unneeded patch that calls clk_bulk_prepare_enable()
> > - Rework the device tree binding (conversion from .txt and RZ/N1 support)
> > - Use the RZ/N1 SOCs family only in the driver match compatible string.
> > - Enable PM and PM_GENERIC_DOMAIN for RZ/N1 and add the missing
> >   '#power-domain-cells' in sysctrl node.
> > 
> > Changes v4:
> > - Remove patches related to PM enable and #pwower-domain-cells as they
> >   will be handle out of this series.
> > - Add Bob's reviewed-by on patch 1
> > - Add Geert's reviewed by on patch 1 and 6
> > - Rename clocks and make the 'resets' property optional on RZ/N1 family
> > - Reword some commit logs and titles
> > - Fix dst node location (sort by node names or unit addresses)
> > - Fix the USB PHY node name
> > 
> > Changes v5:
> > - Rename clocks ("usb_" prefix removed)
> > - Add Geert's reviewed-by on patch 2, 3, 4 and 5
> > 
> > Changes v6:
> > - Include schema optionnal part (ie 'if:') in a 'allOf:' block
> > - Modify commit log on commit 2/6
> > 
> > Herve Codina (6):
> >   dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
> >   dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for
> >     r9a06g032
> >   PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string
> 
> Applied the first three patches (above) to pci/ctrl/rcar-gen2 for
> v5.20, thank you!

Oh, just noticed there's no ack from Marek or Yoshihiro, the
maintainers of drivers/pci/controller/pci-rcar-gen2.c.  Let me know if
you object!  If you can ack it, I will amend the commits to reflect
that.

Bjorn

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2022-06-23 22:40 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-20  9:41 [PATCH v6 0/6] RZN1 USB Host support Herve Codina
2022-05-20  9:41 ` [PATCH v6 1/6] dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema Herve Codina
2022-05-20  9:41 ` [PATCH v6 2/6] dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for r9a06g032 Herve Codina
2022-05-26 20:54   ` Rob Herring
2022-05-20  9:41 ` [PATCH v6 3/6] PCI: rcar-gen2: Add RZ/N1 SOCs family compatible string Herve Codina
2022-05-26 20:55   ` Rob Herring
2022-05-20  9:41 ` [PATCH v6 4/6] ARM: dts: r9a06g032: Add internal PCI bridge node Herve Codina
2022-05-20  9:41 ` [PATCH v6 5/6] ARM: dts: r9a06g032: Add USB PHY DT support Herve Codina
2022-05-20  9:41 ` [PATCH v6 6/6] ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY Herve Codina
2022-05-20 12:12 ` [PATCH v6 0/6] RZN1 USB Host support Geert Uytterhoeven
2022-05-20 12:40   ` Herve Codina
2022-06-23 22:39 ` Bjorn Helgaas
2022-06-23 22:40   ` Bjorn Helgaas

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