* [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
@ 2022-04-27 20:31 Samuel Holland
2022-04-27 20:31 ` [PATCH 01/12] dt-bindings: sunxi: Update clock/reset binding headers Samuel Holland
` (13 more replies)
0 siblings, 14 replies; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
This series brings all of our devicetrees up to date with Linux.
Older SoCs (before A83T) have not been synchronized in over 3 years.
And I don't have any of this hardware to test. But there are not major
changes to those devicetrees either.
The big motivation for including older SoCs in this update is converting
the USB PHY driver to get its VBUS detection GPIO/regulator from the
devicetree instead of from a pin name in Kconfig. Many older boards had
those properties added or fixed since the last devicetree sync. This PHY
driver change is necessary to complete the DM_GPIO migration.
A couple of breaking changes were made to several SoCs' devicetrees in
Linux relating to the "r_intc" interrupt controller. New kernels support
old devicetrees, but not the other way around. So to be most compatible
and avoid regressions, those changes are skipped here.
Samuel Holland (12):
dt-bindings: sunxi: Update clock/reset binding headers
ARM: dts: sunxi: Remove unused devicetree headers
ARM: dts: sun4i: Sync from Linux v5.18-rc1
ARM: dts: sun7i: Sync from Linux v5.18-rc1
ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1
ARM: dts: sun9i: Sync from Linux v5.18-rc1
ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1
ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1
ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1
ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1
ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1
ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1
arch/arm/dts/Makefile | 25 +-
arch/arm/dts/axp209.dtsi | 6 +-
arch/arm/dts/axp22x.dtsi | 11 +-
arch/arm/dts/axp803.dtsi | 10 +-
arch/arm/dts/axp81x.dtsi | 15 +-
arch/arm/dts/sun4i-a10-a1000.dts | 31 +-
arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 20 +-
arch/arm/dts/sun4i-a10-cubieboard.dts | 16 +-
arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 21 +-
arch/arm/dts/sun4i-a10-hackberry.dts | 2 +-
arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 20 +-
arch/arm/dts/sun4i-a10-inet1.dts | 21 +-
arch/arm/dts/sun4i-a10-inet97fv2.dts | 22 +-
arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 74 ++--
.../dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +-
arch/arm/dts/sun4i-a10-jesurun-q5.dts | 4 +-
arch/arm/dts/sun4i-a10-marsboard.dts | 22 +-
arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 33 +-
arch/arm/dts/sun4i-a10-pcduino.dts | 20 +-
arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 21 +-
arch/arm/dts/sun4i-a10-topwise-a721.dts | 242 +++++++++++++
arch/arm/dts/sun4i-a10.dtsi | 135 ++++++-
arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 2 +-
arch/arm/dts/sun50i-a64-orangepi-win.dts | 2 +-
arch/arm/dts/sun50i-a64-pinebook.dts | 1 +
arch/arm/dts/sun50i-a64-pinephone.dtsi | 27 ++
arch/arm/dts/sun50i-a64-pinetab.dts | 29 +-
arch/arm/dts/sun50i-a64-teres-i.dts | 4 +-
arch/arm/dts/sun50i-a64.dtsi | 93 +++--
arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 2 +-
arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +-
arch/arm/dts/sun50i-h5.dtsi | 6 +-
arch/arm/dts/sun50i-h6-beelink-gs1.dts | 38 +-
arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 2 +-
arch/arm/dts/sun50i-h6-orangepi-3.dts | 14 +-
arch/arm/dts/sun50i-h6-orangepi.dtsi | 22 +-
arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 51 +++
arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts | 15 +
arch/arm/dts/sun50i-h6-tanix-tx6.dts | 115 +-----
arch/arm/dts/sun50i-h6-tanix.dtsi | 189 ++++++++++
arch/arm/dts/sun50i-h6.dtsi | 26 +-
arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 16 +-
arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 35 +-
arch/arm/dts/sun5i-a10s-mk802.dts | 31 +-
arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 68 +---
arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +-
arch/arm/dts/sun5i-a10s-wobo-i5.dts | 34 +-
arch/arm/dts/sun5i-a10s.dtsi | 30 +-
arch/arm/dts/sun5i-a13-ampe-a76.dts | 2 +-
.../dts/sun5i-a13-empire-electronix-d709.dts | 41 +--
arch/arm/dts/sun5i-a13-hsg-h702.dts | 37 +-
arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +-
...common.dtsi => sun5i-a13-licheepi-one.dts} | 146 +++++---
arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 50 +--
arch/arm/dts/sun5i-a13-olinuxino.dts | 56 +--
.../dts/sun5i-a13-pocketbook-touch-lux-3.dts | 258 ++++++++++++++
arch/arm/dts/sun5i-a13-q8-tablet.dts | 18 +-
arch/arm/dts/sun5i-a13-utoo-p66.dts | 26 +-
arch/arm/dts/sun5i-a13.dtsi | 23 +-
arch/arm/dts/sun5i-gr8-chip-pro.dts | 38 +-
arch/arm/dts/sun5i-gr8-evb.dts | 333 ++++++++++++++++++
arch/arm/dts/sun5i-gr8.dtsi | 12 +-
arch/arm/dts/sun5i-r8-chip.dts | 52 +--
.../dts/sun5i-reference-design-tablet.dtsi | 57 +--
arch/arm/dts/sun5i.dtsi | 209 +++++++----
arch/arm/dts/sun6i-a31-app4-evb1.dts | 10 +-
arch/arm/dts/sun6i-a31-colombus.dts | 57 +--
arch/arm/dts/sun6i-a31-hummingbird.dts | 75 +---
arch/arm/dts/sun6i-a31-i7.dts | 47 +--
arch/arm/dts/sun6i-a31-m9.dts | 46 +--
arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts | 46 +--
arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 6 +-
arch/arm/dts/sun6i-a31.dtsi | 218 +++++++-----
arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts | 2 +-
arch/arm/dts/sun6i-a31s-cs908.dts | 17 +-
arch/arm/dts/sun6i-a31s-inet-q972.dts | 8 +-
arch/arm/dts/sun6i-a31s-primo81.dts | 32 +-
arch/arm/dts/sun6i-a31s-sina31s-core.dtsi | 4 +-
arch/arm/dts/sun6i-a31s-sina31s.dts | 39 +-
arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 144 +++++---
.../sun6i-a31s-yones-toptech-bs1078-v2.dts | 22 +-
.../dts/sun6i-reference-design-tablet.dtsi | 22 +-
arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 16 +-
arch/arm/dts/sun7i-a20-bananapi.dts | 41 +--
arch/arm/dts/sun7i-a20-bananapro.dts | 16 +-
arch/arm/dts/sun7i-a20-cubieboard2.dts | 28 +-
arch/arm/dts/sun7i-a20-cubietruck.dts | 20 +-
arch/arm/dts/sun7i-a20-haoyu-marsboard.dts | 182 ++++++++++
arch/arm/dts/sun7i-a20-hummingbird.dts | 21 +-
arch/arm/dts/sun7i-a20-i12-tvbox.dts | 16 +-
arch/arm/dts/sun7i-a20-icnova-swac.dts | 15 +-
arch/arm/dts/sun7i-a20-itead-ibox.dts | 8 +-
arch/arm/dts/sun7i-a20-lamobo-r1.dts | 16 +-
.../dts/sun7i-a20-linutronix-testbox-v2.dts | 47 +++
arch/arm/dts/sun7i-a20-m3.dts | 14 +-
arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 14 +-
arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 30 +-
.../arm/dts/sun7i-a20-olinuxino-lime-emmc.dts | 32 ++
arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 32 +-
arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 46 +--
arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 32 +-
arch/arm/dts/sun7i-a20-orangepi-mini.dts | 28 +-
arch/arm/dts/sun7i-a20-orangepi.dts | 26 +-
arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 32 +-
arch/arm/dts/sun7i-a20-pcduino3.dts | 28 +-
arch/arm/dts/sun7i-a20-wexler-tab7200.dts | 13 +-
arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts | 24 +-
arch/arm/dts/sun7i-a20.dtsi | 254 +++++++++++--
arch/arm/dts/sun8i-a23-a33.dtsi | 308 ++++++++++++----
arch/arm/dts/sun8i-a23-evb.dts | 20 +-
arch/arm/dts/sun8i-a23-gt90h-v4.dts | 2 +-
...ommon.dtsi => sun8i-a23-ippo-q8h-v1.2.dts} | 54 ++-
arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts | 73 ++++
.../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 15 +-
.../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 15 +-
arch/arm/dts/sun8i-a23-q8-tablet.dts | 10 +
arch/arm/dts/sun8i-a23.dtsi | 26 +-
...c-edition.dts => sun8i-a33-et-q8-v1.6.dts} | 32 +-
arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 4 +-
arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 14 +-
arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts | 57 +++
arch/arm/dts/sun8i-a33-olinuxino.dts | 12 +-
arch/arm/dts/sun8i-a33-q8-tablet.dts | 7 +
arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 34 +-
arch/arm/dts/sun8i-a33.dtsi | 270 +++++---------
.../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 +
arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 55 ++-
arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 77 +++-
arch/arm/dts/sun8i-a83t-tbs-a711.dts | 101 +++++-
arch/arm/dts/sun8i-a83t.dtsi | 311 ++++++++++++++--
.../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 28 +-
arch/arm/dts/sun8i-h3-beelink-x2.dts | 27 +-
arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 28 ++
arch/arm/dts/sun8i-h3-nanopi-r1.dts | 169 +++++++++
arch/arm/dts/sun8i-h3-nanopi.dtsi | 1 +
arch/arm/dts/sun8i-h3-orangepi-2.dts | 3 +-
arch/arm/dts/sun8i-h3-orangepi-pc.dts | 3 +-
arch/arm/dts/sun8i-h3.dtsi | 10 +-
arch/arm/dts/sun8i-q8-common.dtsi | 31 +-
arch/arm/dts/sun8i-r16-bananapi-m2m.dts | 55 ++-
.../dts/sun8i-r16-nintendo-nes-classic.dts | 54 +++
.../sun8i-r16-nintendo-super-nes-classic.dts | 11 +
arch/arm/dts/sun8i-r16-parrot.dts | 62 +---
arch/arm/dts/sun8i-r40-feta40i.dtsi | 106 ++++++
arch/arm/dts/sun8i-r40-oka40i-c.dts | 203 +++++++++++
arch/arm/dts/sun8i-r40.dtsi | 118 ++++++-
.../dts/sun8i-reference-design-tablet.dtsi | 33 +-
arch/arm/dts/sun8i-s3-elimo-impetus.dtsi | 44 +++
arch/arm/dts/sun8i-s3-elimo-initium.dts | 29 ++
arch/arm/dts/sun8i-s3-pinecube.dts | 13 +-
arch/arm/dts/sun8i-t3-cqa3t-bv3.dts | 226 ++++++++++++
arch/arm/dts/sun8i-v3-sl631-imx179.dts | 12 +
arch/arm/dts/sun8i-v3-sl631.dtsi | 138 ++++++++
arch/arm/dts/sun8i-v3.dtsi | 36 ++
arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 17 +-
arch/arm/dts/sun8i-v3s.dtsi | 93 ++++-
arch/arm/dts/sun9i-a80-cubieboard4.dts | 67 +++-
arch/arm/dts/sun9i-a80-optimus.dts | 50 ++-
arch/arm/dts/sun9i-a80.dtsi | 195 ++++++----
arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 18 +-
arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 4 +-
arch/arm/dts/sunxi-common-regulators.dtsi | 39 --
arch/arm/dts/sunxi-h3-h5.dtsi | 42 ++-
arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 13 +
arch/arm/dts/sunxi-libretech-all-h3-it.dtsi | 2 +-
.../dts/sunxi-reference-design-tablet.dtsi | 11 +-
arch/arm/mach-sunxi/Kconfig | 2 +-
.../Nintendo_NES_Classic_Edition_defconfig | 2 +-
include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +-
include/dt-bindings/clock/sun5i-ccu.h | 13 +-
include/dt-bindings/clock/sun6i-a31-ccu.h | 2 +
include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 2 +
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +-
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
include/dt-bindings/reset/sun5i-ccu.h | 11 +-
include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
177 files changed, 5704 insertions(+), 2683 deletions(-)
create mode 100644 arch/arm/dts/sun4i-a10-topwise-a721.dts
create mode 100644 arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
create mode 100644 arch/arm/dts/sun50i-h6-tanix.dtsi
rename arch/arm/dts/{sun5i-q8-common.dtsi => sun5i-a13-licheepi-one.dts} (62%)
create mode 100644 arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts
create mode 100644 arch/arm/dts/sun5i-gr8-evb.dts
create mode 100644 arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
create mode 100644 arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
rename arch/arm/dts/{sunxi-q8-common.dtsi => sun8i-a23-ippo-q8h-v1.2.dts} (75%)
create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
rename arch/arm/dts/{sun8i-r16-nintendo-nes-classic-edition.dts => sun8i-a33-et-q8-v1.6.dts} (81%)
create mode 100644 arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
create mode 100644 arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts
create mode 100644 arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
create mode 100644 arch/arm/dts/sun8i-r40-feta40i.dtsi
create mode 100644 arch/arm/dts/sun8i-r40-oka40i-c.dts
create mode 100644 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
create mode 100644 arch/arm/dts/sun8i-s3-elimo-initium.dts
create mode 100644 arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
create mode 100644 arch/arm/dts/sun8i-v3-sl631-imx179.dts
create mode 100644 arch/arm/dts/sun8i-v3-sl631.dtsi
--
2.35.1
^ permalink raw reply [flat|nested] 41+ messages in thread
* [PATCH 01/12] dt-bindings: sunxi: Update clock/reset binding headers
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 02/12] ARM: dts: sunxi: Remove unused devicetree headers Samuel Holland
` (12 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Some devicetree updates make use of newly-exposed clocks and resets.
To support that, copy the binding headers from the Linux v5.18-rc1 tag.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +-
include/dt-bindings/clock/sun5i-ccu.h | 13 ++-----------
include/dt-bindings/clock/sun6i-a31-ccu.h | 2 ++
include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 2 ++
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +-
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 ++++
include/dt-bindings/reset/sun5i-ccu.h | 11 +----------
include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +++
8 files changed, 16 insertions(+), 23 deletions(-)
diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
index 318eb15c41..175892189e 100644
--- a/include/dt-bindings/clock/sun50i-a64-ccu.h
+++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
@@ -113,7 +113,7 @@
#define CLK_USB_OHCI0 91
#define CLK_USB_OHCI1 93
-
+#define CLK_DRAM 94
#define CLK_DRAM_VE 95
#define CLK_DRAM_CSI 96
#define CLK_DRAM_DEINTERLACE 97
diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h
index 81f34d477a..75fe5619c3 100644
--- a/include/dt-bindings/clock/sun5i-ccu.h
+++ b/include/dt-bindings/clock/sun5i-ccu.h
@@ -1,17 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_SUN5I_H_
@@ -100,7 +91,7 @@
#define CLK_AVS 96
#define CLK_HDMI 97
#define CLK_GPU 98
-
+#define CLK_MBUS 99
#define CLK_IEP 100
#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
index c5d1334018..39878d9dce 100644
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -49,6 +49,8 @@
#define CLK_PLL_VIDEO1_2X 13
+#define CLK_PLL_MIPI 15
+
#define CLK_CPU 18
#define CLK_AHB1_MIPIDSI 23
diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
index f8222b6b2c..eb524d0bbd 100644
--- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
+++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
@@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
+#define CLK_PLL_MIPI 13
+
#define CLK_CPUX 18
#define CLK_BUS_MIPI_DSI 23
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
index 30d2d15373..5d4ada2c22 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -126,7 +126,7 @@
#define CLK_USB_OHCI1 93
#define CLK_USB_OHCI2 94
#define CLK_USB_OHCI3 95
-
+#define CLK_DRAM 96
#define CLK_DRAM_VE 97
#define CLK_DRAM_CSI 98
#define CLK_DRAM_DEINTERLACE 99
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
index c0d5d5599c..014ac6123d 100644
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -104,4 +104,8 @@
#define CLK_MIPI_CSI 73
+/* Clocks not available on V3s */
+#define CLK_BUS_I2S0 75
+#define CLK_I2S0 76
+
#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h
index c2b9726b50..40cc22ae76 100644
--- a/include/dt-bindings/reset/sun5i-ccu.h
+++ b/include/dt-bindings/reset/sun5i-ccu.h
@@ -1,17 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2016 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _RST_SUN5I_H_
diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
index b58ef21a2e..b6790173af 100644
--- a/include/dt-bindings/reset/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h
@@ -75,4 +75,7 @@
#define RST_BUS_UART1 50
#define RST_BUS_UART2 51
+/* Reset lines not available on V3s */
+#define RST_BUS_I2S0 52
+
#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 02/12] ARM: dts: sunxi: Remove unused devicetree headers
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
2022-04-27 20:31 ` [PATCH 01/12] dt-bindings: sunxi: Update clock/reset binding headers Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 03/12] ARM: dts: sun4i: Sync from Linux v5.18-rc1 Samuel Holland
` (11 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
These files are not included anywhere and do not exist in the Linux
devicetree source.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sun5i-q8-common.dtsi | 180 ------------------------------
arch/arm/dts/sunxi-q8-common.dtsi | 83 --------------
2 files changed, 263 deletions(-)
delete mode 100644 arch/arm/dts/sun5i-q8-common.dtsi
delete mode 100644 arch/arm/dts/sunxi-q8-common.dtsi
diff --git a/arch/arm/dts/sun5i-q8-common.dtsi b/arch/arm/dts/sun5i-q8-common.dtsi
deleted file mode 100644
index a78e189f66..0000000000
--- a/arch/arm/dts/sun5i-q8-common.dtsi
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-#include "sunxi-q8-common.dtsi"
-
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
- aliases {
- serial0 = &uart1;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
- brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
- default-brightness-level = <8>;
- /* TODO: backlight uses axp gpio1 as enable pin */
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-};
-
-&cpu0 {
- cpu-supply = <®_dcdc2>;
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&i2c0 {
- axp209: pmic@34 {
- reg = <0x34>;
- interrupts = <0>;
- };
-};
-
-&i2c1 {
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-};
-
-#include "axp209.dtsi"
-
-&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
- vmmc-supply = <®_vcc3v0>;
- bus-width = <4>;
- cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
- cd-inverted;
- status = "okay";
-};
-
-&otg_sram {
- status = "okay";
-};
-
-&pio {
- mmc0_cd_pin_q8: mmc0_cd_pin@0 {
- allwinner,pins = "PG0";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- allwinner,pins = "PG1";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- allwinner,pins = "PG2";
- allwinner,function = "gpio_in";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
- };
-
- usb0_vbus_pin_a: usb0_vbus_pin@0 {
- allwinner,pins = "PG12";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
-®_dcdc2 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1500000>;
- regulator-name = "vdd-cpu";
-};
-
-®_dcdc3 {
- regulator-always-on;
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1400000>;
- regulator-name = "vdd-int-pll";
-};
-
-®_ldo1 {
- regulator-name = "vdd-rtc";
-};
-
-®_ldo2 {
- regulator-always-on;
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-name = "avcc";
-};
-
-®_usb0_vbus {
- gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
- status = "okay";
-};
-
-&usb_otg {
- dr_mode = "otg";
- status = "okay";
-};
-
-&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
- usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
- usb0_vbus-supply = <®_usb0_vbus>;
- status = "okay";
-};
diff --git a/arch/arm/dts/sunxi-q8-common.dtsi b/arch/arm/dts/sunxi-q8-common.dtsi
deleted file mode 100644
index b8241462fc..0000000000
--- a/arch/arm/dts/sunxi-q8-common.dtsi
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include "sunxi-common-regulators.dtsi"
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "okay";
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "okay";
-};
-
-&lradc {
- vref-supply = <®_vcc3v0>;
- status = "okay";
-
- button@200 {
- label = "Volume Up";
- linux,code = <KEY_VOLUMEUP>;
- channel = <0>;
- voltage = <200000>;
- };
-
- button@400 {
- label = "Volume Down";
- linux,code = <KEY_VOLUMEDOWN>;
- channel = <0>;
- voltage = <400000>;
- };
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>;
- status = "okay";
-};
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 03/12] ARM: dts: sun4i: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
2022-04-27 20:31 ` [PATCH 01/12] dt-bindings: sunxi: Update clock/reset binding headers Samuel Holland
2022-04-27 20:31 ` [PATCH 02/12] ARM: dts: sunxi: Remove unused devicetree headers Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 04/12] ARM: dts: sun7i: " Samuel Holland
` (10 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=UTF-8, Size: 35290 bytes --]
Copy the devicetree source for the A10 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.
This commit also adds the following new board devicetree:
- sun4i-a10-topwise-a721.dts
While this update should not impact any existing U-Boot functionality,
the changes to the USB PHY detection GPIO properties are needed to
convert that driver to use the DM GPIO framework.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/axp209.dtsi | 6 +-
arch/arm/dts/sun4i-a10-a1000.dts | 31 ++-
arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 20 +-
arch/arm/dts/sun4i-a10-cubieboard.dts | 16 +-
arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 21 +-
arch/arm/dts/sun4i-a10-hackberry.dts | 2 +-
arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 20 +-
arch/arm/dts/sun4i-a10-inet1.dts | 21 +-
arch/arm/dts/sun4i-a10-inet97fv2.dts | 22 +-
arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 74 ++----
.../dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +-
arch/arm/dts/sun4i-a10-jesurun-q5.dts | 4 +-
arch/arm/dts/sun4i-a10-marsboard.dts | 22 +-
arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 33 +--
arch/arm/dts/sun4i-a10-pcduino.dts | 20 +-
arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 21 +-
arch/arm/dts/sun4i-a10-topwise-a721.dts | 242 ++++++++++++++++++
arch/arm/dts/sun4i-a10.dtsi | 135 +++++++++-
20 files changed, 462 insertions(+), 255 deletions(-)
create mode 100644 arch/arm/dts/sun4i-a10-topwise-a721.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ab2d0da192..48ede8888e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -539,7 +539,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-olinuxino-lime.dtb \
sun4i-a10-pcduino.dtb \
sun4i-a10-pcduino2.dtb \
- sun4i-a10-pov-protab2-ips9.dtb
+ sun4i-a10-pov-protab2-ips9.dtb \
+ sun4i-a10-topwise-a721.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi
index 0d9ff12bdf..ca240cd6f6 100644
--- a/arch/arm/dts/axp209.dtsi
+++ b/arch/arm/dts/axp209.dtsi
@@ -53,7 +53,7 @@
interrupt-controller;
#interrupt-cells = <1>;
- ac_power_supply: ac-power-supply {
+ ac_power_supply: ac-power {
compatible = "x-powers,axp202-ac-power-supply";
status = "disabled";
};
@@ -69,7 +69,7 @@
#gpio-cells = <2>;
};
- battery_power_supply: battery-power-supply {
+ battery_power_supply: battery-power {
compatible = "x-powers,axp209-battery-power-supply";
status = "disabled";
};
@@ -112,7 +112,7 @@
};
};
- usb_power_supply: usb-power-supply {
+ usb_power_supply: usb-power {
compatible = "x-powers,axp202-usb-power-supply";
status = "disabled";
};
diff --git a/arch/arm/dts/sun4i-a10-a1000.dts b/arch/arm/dts/sun4i-a10-a1000.dts
index 6c254ec4c8..20f9ed2448 100644
--- a/arch/arm/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/dts/sun4i-a10-a1000.dts
@@ -60,15 +60,26 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
- red {
+ led-0 {
label = "a1000:red:usr";
gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
};
- blue {
+ led-1 {
label = "a1000:blue:pwr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -125,7 +136,7 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
@@ -133,6 +144,20 @@
status = "okay";
};
+&de {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
index 38a2c41349..816d534ac0 100644
--- a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
+++ b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
@@ -68,7 +68,7 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
index cf7b392dff..7426298888 100644
--- a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
+++ b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
@@ -131,20 +131,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
-};
-
®_usb0_vbus {
status = "okay";
};
@@ -165,10 +151,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-cubieboard.dts b/arch/arm/dts/sun4i-a10-cubieboard.dts
index 197a1f2b75..0645d60642 100644
--- a/arch/arm/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/dts/sun4i-a10-cubieboard.dts
@@ -75,12 +75,12 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_cubieboard>;
- blue {
+ led-0 {
label = "cubieboard:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */
};
- green {
+ led-1 {
label = "cubieboard:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
linux,default-trigger = "heartbeat";
@@ -114,7 +114,7 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
@@ -184,12 +184,6 @@
function = "gpio_out";
drive-strength = <20>;
};
-
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
};
®_ahci_5v {
@@ -254,9 +248,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
index 896e27a087..63e77c05bf 100644
--- a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
+++ b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
@@ -62,6 +62,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ power-supply = <®_vcc3v3>;
};
chosen {
@@ -158,20 +159,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
-};
-
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -223,10 +210,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-hackberry.dts b/arch/arm/dts/sun4i-a10-hackberry.dts
index cc988ccd5c..47dea09225 100644
--- a/arch/arm/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/dts/sun4i-a10-hackberry.dts
@@ -80,7 +80,7 @@
};
&emac {
- phy = <&phy0>;
+ phy-handle = <&phy0>;
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
index f63767cddd..bf2044bac4 100644
--- a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
+++ b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
@@ -86,20 +86,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
-};
-
®_usb0_vbus {
status = "okay";
};
@@ -121,10 +107,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-inet1.dts b/arch/arm/dts/sun4i-a10-inet1.dts
index 26d0c1d6a0..60e432a0ef 100644
--- a/arch/arm/dts/sun4i-a10-inet1.dts
+++ b/arch/arm/dts/sun4i-a10-inet1.dts
@@ -62,6 +62,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ power-supply = <®_vcc3v3>;
};
chosen {
@@ -164,20 +165,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
-};
-
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -233,10 +220,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
diff --git a/arch/arm/dts/sun4i-a10-inet97fv2.dts b/arch/arm/dts/sun4i-a10-inet97fv2.dts
index 5d096528e7..76016f2ca2 100644
--- a/arch/arm/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/dts/sun4i-a10-inet97fv2.dts
@@ -1,7 +1,7 @@
/*
* Copyright 2014 Open Source Support GmbH
*
- * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
+ * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -150,20 +150,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -209,10 +195,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
index 221acd10f6..0a562b2cc5 100644
--- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
+++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
@@ -61,10 +61,6 @@
gpio-keys {
compatible = "gpio-keys-polled";
- pinctrl-names = "default";
- pinctrl-0 = <&key_pins_inet9f>;
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <20>;
left-joystick-left {
@@ -72,7 +68,7 @@
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
- gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
+ gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
};
left-joystick-right {
@@ -80,7 +76,7 @@
linux,code = <ABS_X>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
- gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
+ gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
};
left-joystick-up {
@@ -88,7 +84,7 @@
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
- gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
+ gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
};
left-joystick-down {
@@ -96,7 +92,7 @@
linux,code = <ABS_Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
- gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
+ gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
};
right-joystick-left {
@@ -104,7 +100,7 @@
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
- gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
+ gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
};
right-joystick-right {
@@ -112,7 +108,7 @@
linux,code = <ABS_Z>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
- gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
+ gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
};
right-joystick-up {
@@ -120,7 +116,7 @@
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
- gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
+ gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
};
right-joystick-down {
@@ -128,7 +124,7 @@
linux,code = <ABS_RZ>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
- gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
+ gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
};
dpad-left {
@@ -136,7 +132,7 @@
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
- gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
+ gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
};
dpad-right {
@@ -144,7 +140,7 @@
linux,code = <ABS_HAT0X>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
- gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
+ gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
};
dpad-up {
@@ -152,7 +148,7 @@
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <0xffffffff>; /* -1 */
- gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
+ gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
};
dpad-down {
@@ -160,55 +156,55 @@
linux,code = <ABS_HAT0Y>;
linux,input-type = <EV_ABS>;
linux,input-value = <1>;
- gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+ gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
};
x {
label = "Button X";
linux,code = <BTN_X>;
- gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
+ gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
};
y {
label = "Button Y";
linux,code = <BTN_Y>;
- gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
+ gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
};
a {
label = "Button A";
linux,code = <BTN_A>;
- gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+ gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
};
b {
label = "Button B";
linux,code = <BTN_B>;
- gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
+ gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
};
select {
label = "Select Button";
linux,code = <BTN_SELECT>;
- gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
+ gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
};
start {
label = "Start Button";
linux,code = <BTN_START>;
- gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
+ gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
};
top-left {
label = "Top Left Button";
linux,code = <BTN_TL>;
- gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
+ gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
};
top-right {
label = "Top Right Button";
linux,code = <BTN_TR>;
- gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
+ gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
};
};
};
@@ -308,30 +304,6 @@
status = "okay";
};
-&pio {
- key_pins_inet9f: key-pins {
- pins = "PA0", "PA1", "PA3", "PA4",
- "PA5", "PA6", "PA8", "PA9",
- "PA11", "PA12", "PA13",
- "PA14", "PA15", "PA16", "PA17",
- "PH22", "PH23", "PH24", "PH25", "PH26";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -377,10 +349,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
index 80ecd78247..d4e319d16a 100644
--- a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
+++ b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
@@ -58,7 +58,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
index 247fa27ef7..1aeb0bd551 100644
--- a/arch/arm/dts/sun4i-a10-jesurun-q5.dts
+++ b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
@@ -63,7 +63,7 @@
leds {
compatible = "gpio-leds";
- green {
+ led {
label = "q5:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */
};
@@ -94,7 +94,7 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-marsboard.dts b/arch/arm/dts/sun4i-a10-marsboard.dts
index 0dbf695765..81fdb217d3 100644
--- a/arch/arm/dts/sun4i-a10-marsboard.dts
+++ b/arch/arm/dts/sun4i-a10-marsboard.dts
@@ -62,22 +62,22 @@
leds {
compatible = "gpio-leds";
- red1 {
+ led-0 {
label = "marsboard:red1:usr";
gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;
};
- red2 {
+ led-1 {
label = "marsboard:red2:usr";
gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>;
};
- red3 {
+ led-2 {
label = "marsboard:red3:usr";
gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
};
- red4 {
+ led-3 {
label = "marsboard:red4:usr";
gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>;
};
@@ -105,7 +105,7 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
@@ -148,14 +148,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_usb1_vbus {
status = "okay";
};
@@ -183,9 +175,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
index b74a614965..83d283cf66 100644
--- a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
@@ -74,7 +74,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxinolime>;
- green {
+ led {
label = "a10-olinuxino-lime:green:usr";
gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -91,12 +91,11 @@
/*
* The A10-Lime is known to be unstable when running at 1008 MHz
*/
- operating-points = <
- /* kHz uV */
- 912000 1350000
- 864000 1300000
- 624000 1250000
- >;
+ operating-points =
+ /* kHz uV */
+ <912000 1350000>,
+ <864000 1300000>,
+ <624000 1250000>;
};
&de {
@@ -112,7 +111,7 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
@@ -186,18 +185,6 @@
function = "gpio_out";
drive-strength = <20>;
};
-
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
};
®_ahci_5v {
@@ -229,10 +216,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts
index b97a0f2f20..1ac82376ba 100644
--- a/arch/arm/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/dts/sun4i-a10-pcduino.dts
@@ -63,12 +63,12 @@
leds {
compatible = "gpio-leds";
- tx {
+ led-0 {
label = "pcduino:green:tx";
gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
};
- rx {
+ led-1 {
label = "pcduino:green:rx";
gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
};
@@ -76,8 +76,6 @@
gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
back {
label = "Key Back";
@@ -112,7 +110,7 @@
};
&emac {
- phy = <&phy1>;
+ phy-handle = <&phy1>;
status = "okay";
};
@@ -156,14 +154,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
#include "axp209.dtsi"
®_dcdc2 {
@@ -203,9 +193,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */
usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
index 84b25be1ac..c325969476 100644
--- a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
+++ b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -62,6 +62,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ power-supply = <®_vcc3v3>;
};
chosen {
@@ -146,20 +147,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
-};
-
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -211,10 +198,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun4i-a10-topwise-a721.dts b/arch/arm/dts/sun4i-a10-topwise-a721.dts
new file mode 100644
index 0000000000..3628f12d25
--- /dev/null
+++ b/arch/arm/dts/sun4i-a10-topwise-a721.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Pascal Roeleven <dev@pascalroeleven.nl>
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Topwise A721";
+ compatible = "topwise,a721", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>;
+ power-supply = <®_vbat>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ brightness-levels = <0 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ panel {
+ compatible = "starry,kr070pe2t";
+ backlight = <&backlight>;
+ power-supply = <®_lcd_power>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&tcon0_out_panel>;
+ };
+ };
+ };
+
+ reg_lcd_power: reg-lcd-power {
+ compatible = "regulator-fixed";
+ regulator-name = "reg-lcd-power";
+ gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+ enable-active-high;
+ };
+
+ reg_vbat: reg-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+
+ accelerometer@4c {
+ compatible = "fsl,mma7660";
+ reg = <0x4c>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
+ reg = <0x38>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-size-x = <800>;
+ touchscreen-size-y = <480>;
+ vcc-supply = <®_vcc3v3>;
+ };
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button-571 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <571428>;
+ };
+
+ button-761 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <761904>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ vcc-pb-supply = <®_vcc3v3>;
+ vcc-pf-supply = <®_vcc3v3>;
+ vcc-ph-supply = <®_vcc3v3>;
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb0_vbus {
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&tcon0_out {
+ tcon0_out_panel: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun4i-a10.dtsi b/arch/arm/dts/sun4i-a10.dtsi
index 3a1c6b45c9..51a6464aab 100644
--- a/arch/arm/dts/sun4i-a10.dtsi
+++ b/arch/arm/dts/sun4i-a10.dtsi
@@ -115,13 +115,12 @@
reg = <0x0>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
- operating-points = <
+ operating-points =
/* kHz uV */
- 1008000 1400000
- 912000 1350000
- 864000 1300000
- 624000 1250000
- >;
+ <1008000 1400000>,
+ <912000 1350000>,
+ <864000 1300000>,
+ <624000 1250000>;
#cooling-cells = <2>;
};
};
@@ -143,7 +142,7 @@
trips {
cpu_alert0: cpu-alert0 {
/* milliCelsius */
- temperature = <850000>;
+ temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
@@ -184,14 +183,34 @@
status = "disabled";
};
+ pmu {
+ compatible = "arm,cortex-a8-pmu";
+ interrupts = <3>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+ default-pool {
+ compatible = "shared-dma-pool";
+ size = <0x6000000>;
+ alloc-ranges = <0x40000000 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
- sram-controller@1c00000 {
- compatible = "allwinner,sun4i-a10-sram-controller";
+ system-control@1c00000 {
+ compatible = "allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@@ -224,6 +243,19 @@
status = "disabled";
};
};
+
+ sram_c: sram@1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0xd0000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0xd0000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x80000>;
+ };
+ };
};
dma: dma-controller@1c02000 {
@@ -234,7 +266,7 @@
#dma-cells = <2>;
};
- nfc: nand@1c03000 {
+ nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
@@ -309,6 +341,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon0-pixel-clock";
+ #clock-cells = <0>;
dmas = <&dma SUN4I_DMA_DEDICATED 14>;
ports {
@@ -358,6 +391,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon1-pixel-clock";
+ #clock-cells = <0>;
dmas = <&dma SUN4I_DMA_DEDICATED 15>;
ports {
@@ -394,6 +428,17 @@
};
};
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun4i-a10-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_VE>;
+ interrupts = <53>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun4i-a10-mmc";
reg = <0x01c0f000 0x1000>;
@@ -450,13 +495,14 @@
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
+ dr_mode = "otg";
status = "disabled";
};
usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun4i-a10-usb-phy";
- reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+ reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
reg-names = "phy_ctrl", "pmu1", "pmu2";
clocks = <&ccu CLK_USB_PHY>;
clock-names = "usb_phy";
@@ -530,8 +576,6 @@
};
hdmi_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
};
};
@@ -579,6 +623,16 @@
status = "disabled";
};
+ csi1: csi@1c1d000 {
+ compatible = "allwinner,sun4i-a10-csi1";
+ reg = <0x01c1d000 0x1000>;
+ interrupts = <43>;
+ clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "ram";
+ resets = <&ccu RST_CSI1>;
+ status = "disabled";
+ };
+
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@@ -625,6 +679,31 @@
function = "can";
};
+ /omit-if-no-ref/
+ csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+ pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+ "PG6", "PG7", "PG8", "PG9", "PG10",
+ "PG11";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH8", "PH9",
+ "PH10", "PH11", "PH12", "PH13", "PH14",
+ "PH15", "PH16", "PH17", "PH18", "PH19",
+ "PH20", "PH21", "PH22", "PH23", "PH24",
+ "PH25", "PH26", "PH27";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_clk_pg_pin: csi1-clk-pg-pin {
+ pins = "PG1";
+ function = "csi1";
+ };
+
emac_pins: emac0-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
@@ -762,13 +841,20 @@
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <22>;
+ interrupts = <22>,
+ <23>,
+ <24>,
+ <25>,
+ <67>,
+ <68>;
clocks = <&osc24M>;
};
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
+ interrupts = <24>;
+ clocks = <&osc24M>;
};
rtc: rtc@1c20d00 {
@@ -1001,6 +1087,27 @@
status = "disabled";
};
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <69>,
+ <70>,
+ <71>,
+ <72>,
+ <73>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pmu";
+ clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_GPU>;
+
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <384000000>;
+ };
+
fe0: display-frontend@1e00000 {
compatible = "allwinner,sun4i-a10-display-frontend";
reg = <0x01e00000 0x20000>;
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 04/12] ARM: dts: sun7i: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (2 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 03/12] ARM: dts: sun4i: Sync from Linux v5.18-rc1 Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 05/12] ARM: dts: sunxi: A13/A31/A23/A33: " Samuel Holland
` (9 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the A20 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.
This commit also adds the following new board devicetrees:
- sun7i-a20-haoyu-marsboard.dts
- sun7i-a20-linutronix-testbox-v2.dts
- sun7i-a20-olinuxino-lime-emmc.dts
This update includes changes to the USB PHY detection GPIO properties
which are needed to convert that driver to use the DM GPIO framework.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 3 +
arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 16 +-
arch/arm/dts/sun7i-a20-bananapi.dts | 41 ++-
arch/arm/dts/sun7i-a20-bananapro.dts | 16 +-
arch/arm/dts/sun7i-a20-cubieboard2.dts | 28 +-
arch/arm/dts/sun7i-a20-cubietruck.dts | 20 +-
arch/arm/dts/sun7i-a20-haoyu-marsboard.dts | 182 +++++++++++++
arch/arm/dts/sun7i-a20-hummingbird.dts | 21 +-
arch/arm/dts/sun7i-a20-i12-tvbox.dts | 16 +-
arch/arm/dts/sun7i-a20-icnova-swac.dts | 15 +-
arch/arm/dts/sun7i-a20-itead-ibox.dts | 8 +-
arch/arm/dts/sun7i-a20-lamobo-r1.dts | 16 +-
.../dts/sun7i-a20-linutronix-testbox-v2.dts | 47 ++++
arch/arm/dts/sun7i-a20-m3.dts | 14 +-
arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 14 +-
arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 30 ++-
.../arm/dts/sun7i-a20-olinuxino-lime-emmc.dts | 32 +++
arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 32 +--
arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 46 ++--
arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 32 +--
arch/arm/dts/sun7i-a20-orangepi-mini.dts | 28 +-
arch/arm/dts/sun7i-a20-orangepi.dts | 26 +-
arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 32 +--
arch/arm/dts/sun7i-a20-pcduino3.dts | 28 +-
arch/arm/dts/sun7i-a20-wexler-tab7200.dts | 13 +-
arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts | 24 +-
arch/arm/dts/sun7i-a20.dtsi | 254 ++++++++++++++++--
27 files changed, 707 insertions(+), 327 deletions(-)
create mode 100644 arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
create mode 100644 arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 48ede8888e..7120d6a3aa 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -583,11 +583,13 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapro.dtb \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
+ sun7i-a20-haoyu-marsboard.dtb \
sun7i-a20-hummingbird.dtb \
sun7i-a20-i12-tvbox.dtb \
sun7i-a20-icnova-swac.dtb \
sun7i-a20-itead-ibox.dtb \
sun7i-a20-lamobo-r1.dtb \
+ sun7i-a20-linutronix-testbox-v2.dtb \
sun7i-a20-m3.dtb \
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
@@ -595,6 +597,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
+ sun7i-a20-olinuxino-lime-emmc.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
sun7i-a20-olinuxino-micro.dtb \
diff --git a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
index 4dbcad1343..caa935ca4f 100644
--- a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
+++ b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -74,12 +74,12 @@
leds {
compatible = "gpio-leds";
- green {
+ led-0 {
label = "bananapi-m1-plus:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-1 {
label = "bananapi-m1-plus:pwr:usr";
gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -129,14 +129,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii-id";
phy-supply = <®_gmac_3v3>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -171,6 +167,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-bananapi.dts b/arch/arm/dts/sun7i-a20-bananapi.dts
index 33040c43bc..46ecf9db23 100644
--- a/arch/arm/dts/sun7i-a20-bananapi.dts
+++ b/arch/arm/dts/sun7i-a20-bananapi.dts
@@ -77,7 +77,7 @@
leds {
compatible = "gpio-leds";
- green {
+ led {
label = "bananapi:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
@@ -104,16 +104,15 @@
&cpu0 {
cpu-supply = <®_dcdc2>;
- operating-points = <
+ operating-points =
/* kHz uV */
- 960000 1400000
- 912000 1400000
- 864000 1350000
- 720000 1250000
- 528000 1150000
- 312000 1100000
- 144000 1050000
- >;
+ <960000 1400000>,
+ <912000 1400000>,
+ <864000 1350000>,
+ <720000 1250000>,
+ <528000 1150000>,
+ <312000 1100000>,
+ <144000 1050000>;
};
&de {
@@ -131,14 +130,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii-id";
phy-supply = <®_gmac_3v3>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -171,6 +166,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -246,12 +247,6 @@
"SPI-MISO", "SPI-CE1", "",
"IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
"", "", "", "", "", "", "", "";
-
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
};
#include "axp209.dtsi"
@@ -329,9 +324,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-bananapro.dts b/arch/arm/dts/sun7i-a20-bananapro.dts
index 8a75545e22..e22f0e8bb1 100644
--- a/arch/arm/dts/sun7i-a20-bananapro.dts
+++ b/arch/arm/dts/sun7i-a20-bananapro.dts
@@ -63,12 +63,12 @@
leds {
compatible = "gpio-leds";
- blue {
+ led-0 {
label = "bananapro:blue:usr";
gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-1 {
label = "bananapro:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
@@ -109,14 +109,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii-id";
phy-supply = <®_gmac_3v3>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -143,6 +139,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-cubieboard2.dts b/arch/arm/dts/sun7i-a20-cubieboard2.dts
index 200685b0b1..e35e6990c4 100644
--- a/arch/arm/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/dts/sun7i-a20-cubieboard2.dts
@@ -75,12 +75,12 @@
leds {
compatible = "gpio-leds";
- blue {
+ led-0 {
label = "cubieboard2:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-1 {
label = "cubieboard2:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
@@ -115,13 +115,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -161,6 +157,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&ohci0 {
status = "okay";
};
@@ -173,14 +175,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_ahci_5v {
status = "okay";
};
@@ -236,9 +230,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun7i-a20-cubietruck.dts b/arch/arm/dts/sun7i-a20-cubietruck.dts
index 46a9f4669e..52160e3683 100644
--- a/arch/arm/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/dts/sun7i-a20-cubietruck.dts
@@ -75,22 +75,22 @@
leds {
compatible = "gpio-leds";
- blue {
+ led-0 {
label = "cubietruck:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
};
- orange {
+ led-1 {
label = "cubietruck:orange:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
- white {
+ led-2 {
label = "cubietruck:white:usr";
gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-3 {
label = "cubietruck:green:usr";
gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
};
@@ -150,13 +150,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -194,6 +190,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-haoyu-marsboard.dts b/arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
new file mode 100644
index 0000000000..097e479c27
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
@@ -0,0 +1,182 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Conley Lee
+ * Conley Lee <conleylee@foxmail.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "HAOYU Electronics Marsboard A20";
+ compatible = "haoyu,a20-marsboard", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
+ phy-handle = <&phy0>;
+ phy-mode = "mii";
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
+ status = "okay";
+};
+
+&gmac_mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ gmac_txerr: gmac-txerr-pin {
+ pins = "PA17";
+ function = "gmac";
+ };
+};
+
+®_ahci_5v {
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun7i-a20-hummingbird.dts b/arch/arm/dts/sun7i-a20-hummingbird.dts
index fd0153f656..3def2a3305 100644
--- a/arch/arm/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/dts/sun7i-a20-hummingbird.dts
@@ -100,19 +100,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_vdd>;
- /* phy reset config */
- snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
- snps,reset-active-low;
- /* wait 1s after reset, otherwise fail to read phy id */
- snps,reset-delays-us = <0 10000 1000000>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -146,6 +137,16 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+ reset-assert-us = <10000>;
+ /* wait 1s after reset, otherwise fail to read phy id */
+ reset-deassert-us = <1000000>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/dts/sun7i-a20-i12-tvbox.dts
index 5f1c4f573d..b21ddd0ec1 100644
--- a/arch/arm/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/dts/sun7i-a20-i12-tvbox.dts
@@ -62,12 +62,12 @@
leds {
compatible = "gpio-leds";
- red {
+ led-0 {
label = "i12_tvbox:red:usr";
gpios = <&pio 7 9 GPIO_ACTIVE_LOW>;
};
- blue {
+ led-1 {
label = "i12_tvbox:blue:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
@@ -115,14 +115,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <®_gmac_3v3>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -145,6 +141,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-icnova-swac.dts b/arch/arm/dts/sun7i-a20-icnova-swac.dts
index 949494730a..413505f45a 100644
--- a/arch/arm/dts/sun7i-a20-icnova-swac.dts
+++ b/arch/arm/dts/sun7i-a20-icnova-swac.dts
@@ -49,7 +49,8 @@
/ {
model = "ICnova-A20 SWAC";
- compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20";
+ compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20",
+ "allwinner,sun7i-a20";
aliases {
serial0 = &uart0;
@@ -75,13 +76,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -98,6 +95,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-itead-ibox.dts b/arch/arm/dts/sun7i-a20-itead-ibox.dts
index b90a7607d0..8ff83016ff 100644
--- a/arch/arm/dts/sun7i-a20-itead-ibox.dts
+++ b/arch/arm/dts/sun7i-a20-itead-ibox.dts
@@ -53,13 +53,13 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_itead_core>;
- green {
+ led-0 {
label = "itead_core:green:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- blue {
+ led-1 {
label = "itead_core:blue:usr";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -97,10 +97,12 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
+};
+&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
diff --git a/arch/arm/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/dts/sun7i-a20-lamobo-r1.dts
index f91e1bee44..97518afe46 100644
--- a/arch/arm/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/dts/sun7i-a20-lamobo-r1.dts
@@ -75,7 +75,7 @@
leds {
compatible = "gpio-leds";
- green {
+ led {
label = "lamobo_r1:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
};
@@ -123,8 +123,6 @@
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
status = "okay";
- /delete-property/#address-cells;
- /delete-property/#size-cells;
fixed-link {
speed = <1000>;
@@ -229,14 +227,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
#include "axp209.dtsi"
&ac_power_supply {
@@ -322,9 +312,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
new file mode 100644
index 0000000000..da5a2eea4c
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2020 Linutronix GmbH
+ * Author: Benedikt Spranger <b.spranger@linutronix.de>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-lamobo-r1.dts"
+
+/ {
+ model = "Lamobo R1";
+ compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20";
+
+ leds {
+ led-opto1 {
+ label = "lamobo_r1:opto:powerswitch";
+ gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-opto2 {
+ label = "lamobo_r1:opto:relay";
+ gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ status = "okay";
+ };
+
+ atecc508a@60 {
+ compatible = "atmel,atecc508a";
+ reg = <0x60>;
+ };
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can_ph_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun7i-a20-m3.dts b/arch/arm/dts/sun7i-a20-m3.dts
index b8a1aaaf39..f161d52388 100644
--- a/arch/arm/dts/sun7i-a20-m3.dts
+++ b/arch/arm/dts/sun7i-a20-m3.dts
@@ -64,7 +64,7 @@
leds {
compatible = "gpio-leds";
- blue {
+ led {
label = "m3:blue:usr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
};
@@ -82,13 +82,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -111,6 +107,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
index f0e6a96e57..f05ee32bc9 100644
--- a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
+++ b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
@@ -75,7 +75,7 @@
leds {
compatible = "gpio-leds";
- green {
+ led {
label = "a20-olimex-som-evb:green:usr";
gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -111,13 +111,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -202,6 +198,12 @@
};
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
index 823aabce04..54af6c1807 100644
--- a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
+++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
@@ -46,19 +46,19 @@
leds {
compatible = "gpio-leds";
- stat {
+ led-0 {
label = "a20-som204-evb:green:stat";
gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- led1 {
+ led-1 {
label = "a20-som204-evb:green:led1";
gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- led2 {
+ led-2 {
label = "a20-som204-evb:yellow:led2";
gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -105,18 +105,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy3>;
+ phy-handle = <&phy3>;
phy-mode = "rgmii";
phy-supply = <®_vcc3v3>;
-
- snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 1000000>;
status = "okay";
-
- phy3: ethernet-phy@3 {
- reg = <3>;
- };
};
&hdmi {
@@ -161,6 +153,16 @@
status = "okay";
};
+&gmac_mdio {
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
+ reset-assert-us = <10000>;
+ /* wait 1s after reset, otherwise fail to read phy id */
+ reset-deassert-us = <1000000>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -314,8 +316,8 @@
};
&usbphy {
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
new file mode 100644
index 0000000000..033cab3443
--- /dev/null
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+#include "sun7i-a20-olinuxino-lime.dts"
+
+/ {
+ model = "Olimex A20-OLinuXino-LIME-eMMC";
+ compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ status = "okay";
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
index 5e411194bf..92938d0222 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
@@ -78,7 +78,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxinolime>;
- green {
+ led {
label = "a20-olinuxino-lime:green:usr";
gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -106,13 +106,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -149,6 +145,12 @@
};
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -174,18 +176,6 @@
function = "gpio_out";
drive-strength = <20>;
};
-
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
};
®_ahci_5v {
@@ -217,10 +207,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
index 996201665b..ecb91fb899 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
@@ -75,7 +75,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxinolime>;
- green {
+ led {
label = "a20-olinuxino-lime2:green:usr";
gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -111,13 +111,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -154,6 +150,12 @@
vref-supply = <®_vcc3v0>;
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -174,23 +176,17 @@
};
&pio {
+ vcc-pa-supply = <®_vcc3v3>;
+ vcc-pc-supply = <®_vcc3v3>;
+ vcc-pe-supply = <®_ldo3>;
+ vcc-pf-supply = <®_vcc3v3>;
+ vcc-pg-supply = <®_ldo4>;
+
led_pins_olinuxinolime: led-pins {
pins = "PH2";
function = "gpio_out";
drive-strength = <20>;
};
-
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
};
®_ahci_5v {
@@ -200,6 +196,14 @@
#include "axp209.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -267,10 +271,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
index 840ae1194a..a1b89b2a29 100644
--- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
@@ -82,7 +82,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxino>;
- green {
+ led {
label = "a20-olinuxino-micro:green:usr";
gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -118,13 +118,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -215,6 +211,12 @@
};
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -252,18 +254,6 @@
function = "gpio_out";
drive-strength = <20>;
};
-
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0-vbus-detect-pin {
- pins = "PH5";
- function = "gpio_in";
- bias-pull-down;
- };
};
#include "axp209.dtsi"
@@ -355,10 +345,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
- usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
+ usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/dts/sun7i-a20-orangepi-mini.dts
index 15881081ca..84efa01e7c 100644
--- a/arch/arm/dts/sun7i-a20-orangepi-mini.dts
+++ b/arch/arm/dts/sun7i-a20-orangepi-mini.dts
@@ -75,12 +75,12 @@
leds {
compatible = "gpio-leds";
- green {
+ led-0 {
label = "orangepi:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
};
- blue {
+ led-1 {
label = "orangepi:blue:usr";
gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
};
@@ -120,14 +120,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -158,6 +154,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -176,14 +178,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -239,9 +233,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-orangepi.dts b/arch/arm/dts/sun7i-a20-orangepi.dts
index d64de2e73a..5d77f1d981 100644
--- a/arch/arm/dts/sun7i-a20-orangepi.dts
+++ b/arch/arm/dts/sun7i-a20-orangepi.dts
@@ -64,7 +64,7 @@
leds {
compatible = "gpio-leds";
- green {
+ led {
label = "orangepi:green:usr";
gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
};
@@ -96,14 +96,10 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_gmac_3v3>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -124,6 +120,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -135,14 +137,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -198,9 +192,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
index 205eaae44a..e40ecb48d7 100644
--- a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Adam Sampson <ats@offog.org>
+ * Copyright 2015-2020 Adam Sampson <ats@offog.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -72,14 +72,12 @@
leds {
compatible = "gpio-leds";
- /* Marked "LED3" on the PCB. */
- usr1 {
+ led-3 {
label = "pcduino3-nano:green:usr1";
gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */
};
- /* Marked "LED4" on the PCB. */
- usr2 {
+ led-4 {
label = "pcduino3-nano:green:usr2";
gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */
};
@@ -114,13 +112,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -149,6 +143,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -168,14 +168,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_ahci_5v {
gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
status = "okay";
@@ -226,9 +218,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb1_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
index a72ed4318d..4f8d55d3ba 100644
--- a/arch/arm/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -64,12 +64,12 @@
leds {
compatible = "gpio-leds";
- tx {
+ led-0 {
label = "pcduino3:green:tx";
gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
};
- rx {
+ led-1 {
label = "pcduino3:green:rx";
gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
};
@@ -122,13 +122,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_mii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -149,6 +145,12 @@
status = "okay";
};
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -168,14 +170,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_ahci_5v {
gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>;
status = "okay";
@@ -226,9 +220,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
index ffade253d1..fef02fcbbd 100644
--- a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
+++ b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
@@ -64,6 +64,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ power-supply = <®_vcc3v3>;
};
chosen {
@@ -156,14 +157,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
@@ -223,9 +216,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
diff --git a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
index c27e56091f..3bfae98f3c 100644
--- a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
+++ b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
@@ -81,13 +81,9 @@
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
- phy = <&phy1>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
@@ -110,6 +106,12 @@
#include "axp209.dtsi"
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
@@ -145,14 +147,6 @@
status = "okay";
};
-&pio {
- usb0_id_detect_pin: usb0-id-detect-pin {
- pins = "PH4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -206,9 +200,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
index 641a8fa6d4..5574299685 100644
--- a/arch/arm/dts/sun7i-a20.dtsi
+++ b/arch/arm/dts/sun7i-a20.dtsi
@@ -47,6 +47,7 @@
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/clock/sun7i-a20-ccu.h>
#include <dt-bindings/reset/sun4i-a10-ccu.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
/ {
interrupt-parent = <&gic>;
@@ -105,16 +106,15 @@
reg = <0>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
- operating-points = <
+ operating-points =
/* kHz uV */
- 960000 1400000
- 912000 1400000
- 864000 1300000
- 720000 1200000
- 528000 1100000
- 312000 1000000
- 144000 1000000
- >;
+ <960000 1400000>,
+ <912000 1400000>,
+ <864000 1300000>,
+ <720000 1200000>,
+ <528000 1100000>,
+ <312000 1000000>,
+ <144000 1000000>;
#cooling-cells = <2>;
};
@@ -124,22 +124,21 @@
reg = <1>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
- operating-points = <
+ operating-points =
/* kHz uV */
- 960000 1400000
- 912000 1400000
- 864000 1300000
- 720000 1200000
- 528000 1100000
- 312000 1000000
- 144000 1000000
- >;
+ <960000 1400000>,
+ <912000 1400000>,
+ <864000 1300000>,
+ <720000 1200000>,
+ <528000 1100000>,
+ <312000 1000000>,
+ <144000 1000000>;
#cooling-cells = <2>;
};
};
thermal-zones {
- cpu_thermal {
+ cpu-thermal {
/* milliseconds */
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -180,7 +179,7 @@
default-pool {
compatible = "shared-dma-pool";
size = <0x6000000>;
- alloc-ranges = <0x4a000000 0x6000000>;
+ alloc-ranges = <0x40000000 0x10000000>;
reusable;
linux,cma-default;
};
@@ -333,7 +332,7 @@
#dma-cells = <2>;
};
- nfc: nand@1c03000 {
+ nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
@@ -376,6 +375,16 @@
num-cs = <1>;
};
+ csi0: csi@1c09000 {
+ compatible = "allwinner,sun7i-a20-csi0";
+ reg = <0x01c09000 0x1000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
+ clock-names = "bus", "isp", "ram";
+ resets = <&ccu RST_CSI0>;
+ status = "disabled";
+ };
+
emac: ethernet@1c0b000 {
compatible = "allwinner,sun4i-a10-emac";
reg = <0x01c0b000 0x1000>;
@@ -394,11 +403,12 @@
};
tcon0: lcd-controller@1c0c000 {
- compatible = "allwinner,sun7i-a20-tcon";
+ compatible = "allwinner,sun7i-a20-tcon0",
+ "allwinner,sun7i-a20-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_TCON0>;
- reset-names = "lcd";
+ resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
+ reset-names = "lcd", "lvds";
clocks = <&ccu CLK_AHB_LCD0>,
<&ccu CLK_TCON0_CH0>,
<&ccu CLK_TCON0_CH1>;
@@ -406,6 +416,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon0-pixel-clock";
+ #clock-cells = <0>;
dmas = <&dma SUN4I_DMA_DEDICATED 14>;
ports {
@@ -443,7 +454,8 @@
};
tcon1: lcd-controller@1c0d000 {
- compatible = "allwinner,sun7i-a20-tcon";
+ compatible = "allwinner,sun7i-a20-tcon1",
+ "allwinner,sun7i-a20-tcon";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_TCON1>;
@@ -455,6 +467,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon1-pixel-clock";
+ #clock-cells = <0>;
dmas = <&dma SUN4I_DMA_DEDICATED 15>;
ports {
@@ -586,13 +599,14 @@
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
+ dr_mode = "otg";
status = "disabled";
};
usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun7i-a20-usb-phy";
- reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+ reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
reg-names = "phy_ctrl", "pmu1", "pmu2";
clocks = <&ccu CLK_USB_PHY>;
clock-names = "usb_phy";
@@ -716,6 +730,17 @@
status = "disabled";
};
+ csi1: csi@1c1d000 {
+ compatible = "allwinner,sun7i-a20-csi1",
+ "allwinner,sun4i-a10-csi1";
+ reg = <0x01c1d000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
+ clock-names = "bus", "ram";
+ resets = <&ccu RST_CSI1>;
+ status = "disabled";
+ };
+
spi3: spi@1c1f000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c1f000 0x1000>;
@@ -751,21 +776,70 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ /omit-if-no-ref/
+ can_pa_pins: can-pa-pins {
+ pins = "PA16", "PA17";
+ function = "can";
+ };
+
+ /omit-if-no-ref/
can_ph_pins: can-ph-pins {
pins = "PH20", "PH21";
function = "can";
};
+ /omit-if-no-ref/
clk_out_a_pin: clk-out-a-pin {
pins = "PI12";
function = "clk_out_a";
};
+ /omit-if-no-ref/
clk_out_b_pin: clk-out-b-pin {
pins = "PI13";
function = "clk_out_b";
};
+ /omit-if-no-ref/
+ csi0_8bits_pins: csi-8bits-pins {
+ pins = "PE0", "PE2", "PE3", "PE4", "PE5",
+ "PE6", "PE7", "PE8", "PE9", "PE10",
+ "PE11";
+ function = "csi0";
+ };
+
+ /omit-if-no-ref/
+ csi0_clk_pin: csi-clk-pin {
+ pins = "PE1";
+ function = "csi0";
+ };
+
+ /omit-if-no-ref/
+ csi1_8bits_pg_pins: csi1-8bits-pg-pins {
+ pins = "PG0", "PG2", "PG3", "PG4", "PG5",
+ "PG6", "PG7", "PG8", "PG9", "PG10",
+ "PG11";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_24bits_ph_pins: csi1-24bits-ph-pins {
+ pins = "PH0", "PH1", "PH2", "PH3", "PH4",
+ "PH5", "PH6", "PH7", "PH8", "PH9",
+ "PH10", "PH11", "PH12", "PH13", "PH14",
+ "PH15", "PH16", "PH17", "PH18", "PH19",
+ "PH20", "PH21", "PH22", "PH23", "PH24",
+ "PH25", "PH26", "PH27";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
+ csi1_clk_pg_pin: csi1-clk-pg-pin {
+ pins = "PG1";
+ function = "csi1";
+ };
+
+ /omit-if-no-ref/
emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
@@ -775,6 +849,17 @@
function = "emac";
};
+ /omit-if-no-ref/
+ emac_ph_pins: emac-ph-pins {
+ pins = "PH8", "PH9", "PH10", "PH11",
+ "PH14", "PH15", "PH16", "PH17",
+ "PH18", "PH19", "PH20", "PH21",
+ "PH22", "PH23", "PH24", "PH25",
+ "PH26";
+ function = "emac";
+ };
+
+ /omit-if-no-ref/
gmac_mii_pins: gmac-mii-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
@@ -784,6 +869,7 @@
function = "gmac";
};
+ /omit-if-no-ref/
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
@@ -798,46 +884,69 @@
drive-strength = <40>;
};
+ /omit-if-no-ref/
i2c0_pins: i2c0-pins {
pins = "PB0", "PB1";
function = "i2c0";
};
+ /omit-if-no-ref/
i2c1_pins: i2c1-pins {
pins = "PB18", "PB19";
function = "i2c1";
};
+ /omit-if-no-ref/
i2c2_pins: i2c2-pins {
pins = "PB20", "PB21";
function = "i2c2";
};
+ /omit-if-no-ref/
i2c3_pins: i2c3-pins {
pins = "PI0", "PI1";
function = "i2c3";
};
+ /omit-if-no-ref/
ir0_rx_pin: ir0-rx-pin {
pins = "PB4";
function = "ir0";
};
+ /omit-if-no-ref/
ir0_tx_pin: ir0-tx-pin {
pins = "PB3";
function = "ir0";
};
+ /omit-if-no-ref/
ir1_rx_pin: ir1-rx-pin {
pins = "PB23";
function = "ir1";
};
+ /omit-if-no-ref/
ir1_tx_pin: ir1-tx-pin {
pins = "PB22";
function = "ir1";
};
+ /omit-if-no-ref/
+ lcd_lvds0_pins: lcd-lvds0-pins {
+ pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ "PD5", "PD6", "PD7", "PD8", "PD9";
+ function = "lvds0";
+ };
+
+ /omit-if-no-ref/
+ lcd_lvds1_pins: lcd-lvds1-pins {
+ pins = "PD10", "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD16", "PD17", "PD18", "PD19";
+ function = "lvds1";
+ };
+
+ /omit-if-no-ref/
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@@ -846,6 +955,7 @@
bias-pull-up;
};
+ /omit-if-no-ref/
mmc2_pins: mmc2-pins {
pins = "PC6", "PC7", "PC8",
"PC9", "PC10", "PC11";
@@ -854,6 +964,7 @@
bias-pull-up;
};
+ /omit-if-no-ref/
mmc3_pins: mmc3-pins {
pins = "PI4", "PI5", "PI6",
"PI7", "PI8", "PI9";
@@ -862,127 +973,206 @@
bias-pull-up;
};
+ /omit-if-no-ref/
ps2_0_pins: ps2-0-pins {
pins = "PI20", "PI21";
function = "ps2";
};
+ /omit-if-no-ref/
ps2_1_ph_pins: ps2-1-ph-pins {
pins = "PH12", "PH13";
function = "ps2";
};
+ /omit-if-no-ref/
pwm0_pin: pwm0-pin {
pins = "PB2";
function = "pwm";
};
+ /omit-if-no-ref/
pwm1_pin: pwm1-pin {
pins = "PI3";
function = "pwm";
};
+ /omit-if-no-ref/
spdif_tx_pin: spdif-tx-pin {
pins = "PB13";
function = "spdif";
bias-pull-up;
};
+ /omit-if-no-ref/
spi0_pi_pins: spi0-pi-pins {
pins = "PI11", "PI12", "PI13";
function = "spi0";
};
+ /omit-if-no-ref/
spi0_cs0_pi_pin: spi0-cs0-pi-pin {
pins = "PI10";
function = "spi0";
};
+ /omit-if-no-ref/
spi0_cs1_pi_pin: spi0-cs1-pi-pin {
pins = "PI14";
function = "spi0";
};
+ /omit-if-no-ref/
spi1_pi_pins: spi1-pi-pins {
pins = "PI17", "PI18", "PI19";
function = "spi1";
};
+ /omit-if-no-ref/
spi1_cs0_pi_pin: spi1-cs0-pi-pin {
pins = "PI16";
function = "spi1";
};
+ /omit-if-no-ref/
spi2_pb_pins: spi2-pb-pins {
pins = "PB15", "PB16", "PB17";
function = "spi2";
};
+ /omit-if-no-ref/
spi2_cs0_pb_pin: spi2-cs0-pb-pin {
pins = "PB14";
function = "spi2";
};
+ /omit-if-no-ref/
spi2_pc_pins: spi2-pc-pins {
pins = "PC20", "PC21", "PC22";
function = "spi2";
};
+ /omit-if-no-ref/
spi2_cs0_pc_pin: spi2-cs0-pc-pin {
pins = "PC19";
function = "spi2";
};
+ /omit-if-no-ref/
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
};
+ /omit-if-no-ref/
+ uart0_pf_pins: uart0-pf-pins {
+ pins = "PF2", "PF4";
+ function = "uart0";
+ };
+
+ /omit-if-no-ref/
+ uart1_pa_pins: uart1-pa-pins {
+ pins = "PA10", "PA11";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
+ pins = "PA12", "PA13";
+ function = "uart1";
+ };
+
+ /omit-if-no-ref/
+ uart2_pa_pins: uart2-pa-pins {
+ pins = "PA2", "PA3";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
+ uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
+ pins = "PA0", "PA1";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
uart2_pi_pins: uart2-pi-pins {
pins = "PI18", "PI19";
function = "uart2";
};
+ /omit-if-no-ref/
uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
pins = "PI16", "PI17";
function = "uart2";
};
+ /omit-if-no-ref/
uart3_pg_pins: uart3-pg-pins {
pins = "PG6", "PG7";
function = "uart3";
};
+ /omit-if-no-ref/
uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
pins = "PG8", "PG9";
function = "uart3";
};
+ /omit-if-no-ref/
uart3_ph_pins: uart3-ph-pins {
pins = "PH0", "PH1";
function = "uart3";
};
+ /omit-if-no-ref/
+ uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
+ pins = "PH2", "PH3";
+ function = "uart3";
+ };
+
+ /omit-if-no-ref/
uart4_pg_pins: uart4-pg-pins {
pins = "PG10", "PG11";
function = "uart4";
};
+ /omit-if-no-ref/
uart4_ph_pins: uart4-ph-pins {
pins = "PH4", "PH5";
function = "uart4";
};
+ /omit-if-no-ref/
+ uart5_ph_pins: uart5-ph-pins {
+ pins = "PH6", "PH7";
+ function = "uart5";
+ };
+
+ /omit-if-no-ref/
uart5_pi_pins: uart5-pi-pins {
pins = "PI10", "PI11";
function = "uart5";
};
+ /omit-if-no-ref/
+ uart6_pa_pins: uart6-pa-pins {
+ pins = "PA12", "PA13";
+ function = "uart6";
+ };
+
+ /omit-if-no-ref/
uart6_pi_pins: uart6-pi-pins {
pins = "PI12", "PI13";
function = "uart6";
};
+ /omit-if-no-ref/
+ uart7_pa_pins: uart7-pa-pins {
+ pins = "PA14", "PA15";
+ function = "uart7";
+ };
+
+ /omit-if-no-ref/
uart7_pi_pins: uart7-pi-pins {
pins = "PI20", "PI21";
function = "uart7";
@@ -1004,6 +1194,8 @@
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
rtc: rtc@1c20d00 {
@@ -1326,8 +1518,12 @@
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
+
+ gmac_mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
hstimer@1c60000 {
@@ -1341,7 +1537,7 @@
};
gic: interrupt-controller@1c81000 {
- compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 05/12] ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (3 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 04/12] ARM: dts: sun7i: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-20 15:34 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 06/12] ARM: dts: sun9i: " Samuel Holland
` (8 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16
SoCs and all existing boards from the Linux v5.18-rc1 tag.
These changes are combined into one commit due to interdependencies:
- The unit addresses were removed from bitbanged I2C buses, which
drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts
and sun6i-a31-colombus.dts.
- The pinctrl nodes were renamed, including some used by the shared
header sunxi-reference-design-tablet.dtsi.
To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts
to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree.
This commit also adds the following new board devicetrees:
- sun5i-a13-licheepi-one.dts
- sun5i-a13-pocketbook-touch-lux-3.dts
- sun5i-gr8-evb.dts
- sun8i-a23-ippo-q8h-v1.2.dts
- sun8i-a23-ippo-q8h-v5.dts
- sun8i-a33-et-q8-v1.6.dts
- sun8i-a33-ippo-q8h-v1.2.dts
- sun8i-r16-nintendo-super-nes-classic.dts
As with the other SoCs, updates of note are conversion of GPIO pull-up
from pinconf to GPIO flags and renaming the detection GPIO properties in
the USB PHY nodes.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 10 +-
arch/arm/dts/axp22x.dtsi | 11 +-
arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 16 +-
arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 35 +-
arch/arm/dts/sun5i-a10s-mk802.dts | 31 +-
arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 68 +---
arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +-
arch/arm/dts/sun5i-a10s-wobo-i5.dts | 34 +-
arch/arm/dts/sun5i-a10s.dtsi | 30 +-
arch/arm/dts/sun5i-a13-ampe-a76.dts | 2 +-
.../dts/sun5i-a13-empire-electronix-d709.dts | 41 +--
arch/arm/dts/sun5i-a13-hsg-h702.dts | 37 +-
arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +-
arch/arm/dts/sun5i-a13-licheepi-one.dts | 214 +++++++++++
arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 50 +--
arch/arm/dts/sun5i-a13-olinuxino.dts | 56 +--
.../dts/sun5i-a13-pocketbook-touch-lux-3.dts | 258 ++++++++++++++
arch/arm/dts/sun5i-a13-q8-tablet.dts | 18 +-
arch/arm/dts/sun5i-a13-utoo-p66.dts | 26 +-
arch/arm/dts/sun5i-a13.dtsi | 23 +-
arch/arm/dts/sun5i-gr8-chip-pro.dts | 38 +-
arch/arm/dts/sun5i-gr8-evb.dts | 333 ++++++++++++++++++
arch/arm/dts/sun5i-gr8.dtsi | 12 +-
arch/arm/dts/sun5i-r8-chip.dts | 52 +--
.../dts/sun5i-reference-design-tablet.dtsi | 57 +--
arch/arm/dts/sun5i.dtsi | 209 +++++++----
arch/arm/dts/sun6i-a31-app4-evb1.dts | 10 +-
arch/arm/dts/sun6i-a31-colombus.dts | 57 +--
arch/arm/dts/sun6i-a31-hummingbird.dts | 75 +---
arch/arm/dts/sun6i-a31-i7.dts | 47 +--
arch/arm/dts/sun6i-a31-m9.dts | 46 +--
arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts | 46 +--
arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 6 +-
arch/arm/dts/sun6i-a31.dtsi | 218 +++++++-----
arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts | 2 +-
arch/arm/dts/sun6i-a31s-cs908.dts | 17 +-
arch/arm/dts/sun6i-a31s-inet-q972.dts | 8 +-
arch/arm/dts/sun6i-a31s-primo81.dts | 32 +-
arch/arm/dts/sun6i-a31s-sina31s-core.dtsi | 4 +-
arch/arm/dts/sun6i-a31s-sina31s.dts | 39 +-
arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 144 +++++---
.../sun6i-a31s-yones-toptech-bs1078-v2.dts | 22 +-
.../dts/sun6i-reference-design-tablet.dtsi | 22 +-
arch/arm/dts/sun8i-a23-a33.dtsi | 308 ++++++++++++----
arch/arm/dts/sun8i-a23-evb.dts | 20 +-
arch/arm/dts/sun8i-a23-gt90h-v4.dts | 2 +-
arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts | 73 ++++
arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts | 73 ++++
.../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 15 +-
.../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 15 +-
arch/arm/dts/sun8i-a23-q8-tablet.dts | 10 +
arch/arm/dts/sun8i-a23.dtsi | 26 +-
...c-edition.dts => sun8i-a33-et-q8-v1.6.dts} | 32 +-
arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 4 +-
arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 14 +-
arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts | 57 +++
arch/arm/dts/sun8i-a33-olinuxino.dts | 12 +-
arch/arm/dts/sun8i-a33-q8-tablet.dts | 7 +
arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 34 +-
arch/arm/dts/sun8i-a33.dtsi | 270 +++++---------
arch/arm/dts/sun8i-q8-common.dtsi | 31 +-
arch/arm/dts/sun8i-r16-bananapi-m2m.dts | 55 ++-
.../dts/sun8i-r16-nintendo-nes-classic.dts | 54 +++
.../sun8i-r16-nintendo-super-nes-classic.dts | 11 +
arch/arm/dts/sun8i-r16-parrot.dts | 62 +---
.../dts/sun8i-reference-design-tablet.dtsi | 33 +-
arch/arm/dts/sunxi-common-regulators.dtsi | 39 --
.../dts/sunxi-reference-design-tablet.dtsi | 11 +-
arch/arm/mach-sunxi/Kconfig | 2 +-
.../Nintendo_NES_Classic_Edition_defconfig | 2 +-
70 files changed, 2149 insertions(+), 1603 deletions(-)
create mode 100644 arch/arm/dts/sun5i-a13-licheepi-one.dts
create mode 100644 arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts
create mode 100644 arch/arm/dts/sun5i-gr8-evb.dts
create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts
create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
rename arch/arm/dts/{sun8i-r16-nintendo-nes-classic-edition.dts => sun8i-a33-et-q8-v1.6.dts} (81%)
create mode 100644 arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
create mode 100644 arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts
create mode 100644 arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7120d6a3aa..6433f63455 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -555,11 +555,14 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-hsg-h702.dtb \
sun5i-a13-inet-86vs.dtb \
sun5i-a13-inet-98v-rev2.dtb \
+ sun5i-a13-licheepi-one.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
+ sun5i-a13-pocketbook-touch-lux-3.dtb \
sun5i-a13-q8-tablet.dtb \
sun5i-a13-utoo-p66.dtb \
sun5i-gr8-chip-pro.dtb \
+ sun5i-gr8-evb.dtb \
sun5i-r8-chip.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-app4-evb1.dtb \
@@ -614,17 +617,22 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-inet86dz.dtb \
+ sun8i-a23-ippo-q8h-v1.2.dtb \
+ sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-polaroid-mid2407pxe03.dtb \
sun8i-a23-polaroid-mid2809pxe04.dtb \
sun8i-a23-q8-tablet.dtb
dtb-$(CONFIG_MACH_SUN8I_A33) += \
+ sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-inet-d978-rev2.dtb \
+ sun8i-a33-ippo-q8h-v1.2.dtb \
sun8i-a33-olinuxino.dtb \
sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-r16-bananapi-m2m.dtb \
- sun8i-r16-nintendo-nes-classic-edition.dtb \
+ sun8i-r16-nintendo-nes-classic.dtb \
+ sun8i-r16-nintendo-super-nes-classic.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN8I_A83T) += \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
diff --git a/arch/arm/dts/axp22x.dtsi b/arch/arm/dts/axp22x.dtsi
index 87fb08e812..a020c12b28 100644
--- a/arch/arm/dts/axp22x.dtsi
+++ b/arch/arm/dts/axp22x.dtsi
@@ -52,12 +52,17 @@
interrupt-controller;
#interrupt-cells = <1>;
- ac_power_supply: ac-power-supply {
+ ac_power_supply: ac-power {
compatible = "x-powers,axp221-ac-power-supply";
status = "disabled";
};
- battery_power_supply: battery-power-supply {
+ axp_adc: adc {
+ compatible = "x-powers,axp221-adc";
+ #io-channel-cells = <1>;
+ };
+
+ battery_power_supply: battery-power {
compatible = "x-powers,axp221-battery-power-supply";
status = "disabled";
};
@@ -158,7 +163,7 @@
};
};
- usb_power_supply: usb_power_supply {
+ usb_power_supply: usb-power {
compatible = "x-powers,axp221-usb-power-supply";
status = "disabled";
};
diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t003.dts b/arch/arm/dts/sun5i-a10s-auxtek-t003.dts
index 39504d720e..04b0e6d287 100644
--- a/arch/arm/dts/sun5i-a10s-auxtek-t003.dts
+++ b/arch/arm/dts/sun5i-a10s-auxtek-t003.dts
@@ -62,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_t003>;
- red {
+ led {
label = "t003-tv-dongle:red:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
default-state = "on";
@@ -75,8 +75,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@@ -89,8 +87,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t003>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@@ -106,13 +102,7 @@
};
&pio {
- mmc0_cd_pin_t003: mmc0_cd_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-up;
- };
-
- led_pins_t003: led_pins@0 {
+ led_pins_t003: led-pin {
pins = "PB2";
function = "gpio_out";
drive-strength = <20>;
@@ -131,7 +121,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/dts/sun5i-a10s-auxtek-t004.dts
index 8d4fb93312..667bc2dc1e 100644
--- a/arch/arm/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/dts/sun5i-a10s-auxtek-t004.dts
@@ -62,7 +62,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_t004>;
- red {
+ led {
label = "t004-tv-dongle:red:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
default-state = "on";
@@ -71,8 +71,6 @@
reg_vmmc1: vmmc1 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_vcc_en_pin_t004>;
regulator-name = "vmmc1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -86,8 +84,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@@ -100,8 +96,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_t004>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@@ -109,8 +103,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <®_vmmc1>;
bus-width = <4>;
non-removable;
@@ -127,24 +119,7 @@
};
&pio {
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PG12";
- function = "gpio_in";
- bias-pull-up;
- };
-
- mmc0_cd_pin_t004: mmc0_cd_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-up;
- };
-
- mmc1_vcc_en_pin_t004: mmc1_vcc_en_pin@0 {
- pins = "PB18";
- function = "gpio_out";
- };
-
- led_pins_t004: led_pins@0 {
+ led_pins_t004: led-pin {
pins = "PB2";
function = "gpio_out";
drive-strength = <20>;
@@ -158,7 +133,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
@@ -168,9 +143,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
};
diff --git a/arch/arm/dts/sun5i-a10s-mk802.dts b/arch/arm/dts/sun5i-a10s-mk802.dts
index dd7fd5c3d7..d0219404c2 100644
--- a/arch/arm/dts/sun5i-a10s-mk802.dts
+++ b/arch/arm/dts/sun5i-a10s-mk802.dts
@@ -59,10 +59,8 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_mk802>;
- red {
+ led {
label = "mk802:red:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2 */
};
@@ -74,8 +72,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@@ -88,8 +84,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@@ -97,8 +91,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
non-removable;
@@ -113,33 +105,14 @@
status = "okay";
};
-&pio {
- led_pins_mk802: led_pins@0 {
- pins = "PB2";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_mk802: mmc0_cd_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb1_vbus_pin_mk802: usb1_vbus_pin@0 {
- pins = "PB10";
- function = "gpio_out";
- };
-};
-
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_mk802>;
gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts
index 2c902ed2c8..5832bb31fc 100644
--- a/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/dts/sun5i-a10s-olinuxino-micro.dts
@@ -79,7 +79,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxino>;
- green {
+ led {
label = "a10s-olinuxino-micro:green:usr";
gpios = <&pio 4 3 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -97,8 +97,8 @@
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_b>;
- phy = <&phy1>;
+ pinctrl-0 = <&emac_pa_pins>;
+ phy-handle = <&phy1>;
status = "okay";
};
@@ -117,8 +117,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp152: pmic@30 {
@@ -130,11 +128,9 @@
#include "axp152.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
- at24@50 {
+ eeprom@50 {
compatible = "atmel,24c16";
pagesize = <16>;
reg = <0x50>;
@@ -143,8 +139,6 @@
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@@ -152,35 +146,35 @@
vref-supply = <®_vcc3v0>;
status = "okay";
- button@191 {
+ button-191 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <191274>;
};
- button@392 {
+ button-392 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <392644>;
};
- button@601 {
+ button-601 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <601151>;
};
- button@795 {
+ button-795 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
voltage = <795090>;
};
- button@987 {
+ button-987 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
@@ -197,8 +191,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@@ -206,8 +198,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
@@ -223,34 +213,11 @@
};
&pio {
- mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-up;
- };
-
- mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
- pins = "PG13";
- function = "gpio_in";
- bias-pull-up;
- };
-
- led_pins_olinuxino: led_pins@0 {
+ led_pins_olinuxino: led-pin {
pins = "PE3";
function = "gpio_out";
drive-strength = <20>;
};
-
- usb1_vbus_pin_olinuxino_m: usb1_vbus_pin@0 {
- pins = "PB10";
- function = "gpio_out";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PG12";
- function = "gpio_in";
- bias-pull-up;
- };
};
®_usb0_vbus {
@@ -259,15 +226,14 @@
};
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_olinuxino_m>;
gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_b>,
- <&spi2_cs0_pins_b>;
+ pinctrl-0 = <&spi2_pb_pins>,
+ <&spi2_cs0_pb_pin>;
status = "okay";
};
@@ -277,19 +243,19 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins_b>;
+ pinctrl-0 = <&uart2_pc_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_a>;
+ pinctrl-0 = <&uart3_pg_pins>;
status = "okay";
};
@@ -299,9 +265,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_id_det-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts
index 034853d1c0..964360f061 100644
--- a/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts
+++ b/arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -63,7 +63,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_r7>;
- green {
+ led {
label = "r7-tv-dongle:green:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -76,8 +76,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
@@ -85,8 +83,6 @@
};
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
non-removable;
@@ -98,33 +94,21 @@
};
&pio {
- mmc0_cd_pin_r7: mmc0_cd_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-up;
- };
-
- led_pins_r7: led_pins@0 {
+ led_pins_r7: led-pin {
pins = "PB2";
function = "gpio_out";
drive-strength = <20>;
};
-
- usb1_vbus_pin_r7: usb1_vbus_pin@0 {
- pins = "PG13";
- function = "gpio_out";
- };
};
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_r7>;
gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/dts/sun5i-a10s-wobo-i5.dts
index 3f68ef5d92..ef8baa9926 100644
--- a/arch/arm/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/dts/sun5i-a10s-wobo-i5.dts
@@ -61,10 +61,8 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_wobo_i5>;
- blue {
+ led {
label = "a10s-wobo-i5:blue:usr";
gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -73,8 +71,6 @@
reg_emac_3v3: emac-3v3 {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&emac_power_pin_wobo>;
regulator-name = "emac-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -94,8 +90,8 @@
&emac {
pinctrl-names = "default";
- pinctrl-0 = <&emac_pins_a>;
- phy = <&phy1>;
+ pinctrl-0 = <&emac_pd_pins>;
+ phy-handle = <&phy1>;
status = "okay";
};
@@ -104,8 +100,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@@ -126,8 +120,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
@@ -142,24 +134,6 @@
status = "okay";
};
-&pio {
- led_pins_wobo_i5: led_pins@0 {
- pins = "PB2";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 {
- pins = "PB3";
- function = "gpio_in";
- bias-pull-up;
- };
-
- emac_power_pin_wobo: emac_power_pin@0 {
- pins = "PA02";
- function = "gpio_out";
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -206,7 +180,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi
index 316cb8b294..09c486b608 100644
--- a/arch/arm/dts/sun5i-a10s.dtsi
+++ b/arch/arm/dts/sun5i-a10s.dtsi
@@ -42,15 +42,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include "sun5i.dtsi"
#include <dt-bindings/dma/sun4i-a10.h>
/ {
- interrupt-parent = <&intc>;
-
aliases {
ethernet0 = &emac;
};
@@ -60,7 +56,7 @@
#size-cells = <1>;
ranges;
- framebuffer@2 {
+ framebuffer-lcd0-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
@@ -76,7 +72,7 @@
allwinner,pipelines = <&fe0>;
};
- soc@1c00000 {
+ soc {
hdmi: hdmi@1c16000 {
compatible = "allwinner,sun5i-a10s-hdmi";
reg = <0x01c16000 0x1000>;
@@ -104,8 +100,6 @@
};
hdmi_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
};
};
@@ -125,20 +119,25 @@
compatible = "allwinner,sun5i-a10s-ccu";
};
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+};
+
&pio {
compatible = "allwinner,sun5i-a10s-pinctrl";
- uart0_pins_a: uart0@0 {
+ uart0_pb_pins: uart0-pb-pins {
pins = "PB19", "PB20";
function = "uart0";
};
- uart2_pins_b: uart2@1 {
+ uart2_pc_pins: uart2-pc-pins {
pins = "PC18", "PC19";
function = "uart2";
};
- emac_pins_b: emac0@1 {
+ emac_pa_pins: emac-pa-pins {
pins = "PA0", "PA1", "PA2",
"PA3", "PA4", "PA5", "PA6",
"PA7", "PA8", "PA9", "PA10",
@@ -147,27 +146,24 @@
function = "emac";
};
- mmc1_pins_a: mmc1@0 {
+ mmc1_pins: mmc1-pins {
pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
function = "mmc1";
drive-strength = <30>;
};
- spi2_pins_b: spi2@1 {
+ spi2_pb_pins: spi2-pb-pins {
pins = "PB12", "PB13", "PB14";
function = "spi2";
};
- spi2_cs0_pins_b: spi2_cs0@1 {
+ spi2_cs0_pb_pin: spi2-cs0-pb-pin {
pins = "PB11";
function = "spi2";
};
};
-&sram_a {
-};
-
&tcon0_out {
tcon0_out_hdmi: endpoint@2 {
reg = <2>;
diff --git a/arch/arm/dts/sun5i-a13-ampe-a76.dts b/arch/arm/dts/sun5i-a13-ampe-a76.dts
index 1bf88816c3..7bc35329a5 100644
--- a/arch/arm/dts/sun5i-a13-ampe-a76.dts
+++ b/arch/arm/dts/sun5i-a13-ampe-a76.dts
@@ -23,6 +23,6 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts
index 378214d831..d059388d72 100644
--- a/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts
+++ b/arch/arm/dts/sun5i-a13-empire-electronix-d709.dts
@@ -61,6 +61,7 @@
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
+ power-supply = <®_vcc3v3>;
/* TODO: backlight uses axp gpio1 as enable pin */
};
@@ -78,8 +79,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@@ -91,8 +90,6 @@
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
pcf8563: rtc@51 {
@@ -105,14 +102,14 @@
vref-supply = <®_ldo2>;
status = "okay";
- button@200 {
+ button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
- button@400 {
+ button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@@ -121,8 +118,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@@ -133,29 +128,9 @@
status = "okay";
};
-&pio {
- mmc0_cd_pin_d709: mmc0_cd_pin@0 {
- pins = "PG0";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-down;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PG2";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>;
+ pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
@@ -197,7 +172,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@@ -207,10 +182,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
- usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+ usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_ldo3>;
status = "okay";
diff --git a/arch/arm/dts/sun5i-a13-hsg-h702.dts b/arch/arm/dts/sun5i-a13-hsg-h702.dts
index 7ee0c3f6d7..9b9f2a5748 100644
--- a/arch/arm/dts/sun5i-a13-hsg-h702.dts
+++ b/arch/arm/dts/sun5i-a13-hsg-h702.dts
@@ -69,8 +69,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@@ -80,8 +78,6 @@
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
pcf8563: rtc@51 {
@@ -91,8 +87,6 @@
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@@ -100,14 +94,14 @@
vref-supply = <®_ldo2>;
status = "okay";
- button@200 {
+ button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
- button@400 {
+ button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@@ -116,8 +110,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@@ -132,25 +124,6 @@
status = "okay";
};
-&pio {
- mmc0_cd_pin_h702: mmc0_cd_pin@0 {
- pins = "PG0";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PG2";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- };
-};
-
#include "axp209.dtsi"
®_dcdc2 {
@@ -191,7 +164,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@@ -201,9 +174,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_ldo3>;
diff --git a/arch/arm/dts/sun5i-a13-inet-86vs.dts b/arch/arm/dts/sun5i-a13-inet-86vs.dts
index aef733b3fe..9c43a34d99 100644
--- a/arch/arm/dts/sun5i-a13-inet-86vs.dts
+++ b/arch/arm/dts/sun5i-a13-inet-86vs.dts
@@ -23,6 +23,6 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun5i-a13-licheepi-one.dts b/arch/arm/dts/sun5i-a13-licheepi-one.dts
new file mode 100644
index 0000000000..2ce361f8fe
--- /dev/null
+++ b/arch/arm/dts/sun5i-a13-licheepi-one.dts
@@ -0,0 +1,214 @@
+/*
+ * Copyright 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun5i-a13-olinuxino.dts, which is
+ * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com>
+ * Copyright 2013 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Lichee Pi One";
+ compatible = "licheepi,licheepi-one", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label ="licheepi:red:usr";
+ gpios = <&pio 2 5 GPIO_ACTIVE_LOW>;
+ };
+
+ led-1 {
+ label ="licheepi:green:usr";
+ gpios = <&pio 2 19 GPIO_ACTIVE_LOW>;
+ default-state = "on";
+ };
+
+ led-2 {
+ label ="licheepi:blue:usr";
+ gpios = <&pio 2 4 GPIO_ACTIVE_LOW>;
+ };
+
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupts = <0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+};
+
+&i2c1 {
+ status = "disabled";
+};
+
+&i2c2 {
+ status = "disabled";
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button-984 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <984126>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ broken-cd;
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pc_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ broken-cd;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+#include "axp209.dtsi"
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "csi-1.8v";
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "csi-2.8v";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pg_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/dts/sun5i-a13-olinuxino-micro.dts
index aa4b34fd91..bfe1075e62 100644
--- a/arch/arm/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/dts/sun5i-a13-olinuxino-micro.dts
@@ -64,7 +64,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxinom>;
- power {
+ led {
label = "a13-olinuxino-micro:green:power";
gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -77,26 +77,18 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@@ -112,56 +104,26 @@
};
&pio {
- mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
- pins = "PG0";
- function = "gpio_in";
- bias-pull-up;
- };
-
- led_pins_olinuxinom: led_pins@0 {
+ led_pins_olinuxinom: led-pin {
pins = "PG9";
function = "gpio_out";
drive-strength = <20>;
};
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PG2";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-down;
- };
-
- usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 {
- pins = "PG12";
- function = "gpio_out";
- };
-
- usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 {
- pins = "PG11";
- function = "gpio_out";
- };
};
®_usb0_vbus {
- pinctrl-0 = <&usb0_vbus_pin_olinuxinom>;
gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>;
status = "okay";
};
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_olinuxinom>;
gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@@ -171,10 +133,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
- usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+ usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun5i-a13-olinuxino.dts b/arch/arm/dts/sun5i-a13-olinuxino.dts
index 437ad913a3..fadeae3cd8 100644
--- a/arch/arm/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/dts/sun5i-a13-olinuxino.dts
@@ -66,7 +66,7 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pins_olinuxino>;
- power {
+ led {
gpios = <&pio 6 9 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
@@ -74,8 +74,6 @@
bridge {
compatible = "dumb-vga-dac";
- #address-cells = <1>;
- #size-cells = <0>;
ports {
#address-cells = <1>;
@@ -123,8 +121,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@@ -138,14 +134,10 @@
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@@ -153,35 +145,35 @@
vref-supply = <®_vcc3v0>;
status = "okay";
- button@191 {
+ button-191 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <191274>;
};
- button@392 {
+ button-392 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <392644>;
};
- button@601 {
+ button-601 {
label = "Menu";
linux,code = <KEY_MENU>;
channel = <0>;
voltage = <601151>;
};
- button@795 {
+ button-795 {
label = "Enter";
linux,code = <KEY_ENTER>;
channel = <0>;
voltage = <795090>;
};
- button@987 {
+ button-987 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
@@ -190,8 +182,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@@ -207,34 +197,11 @@
};
&pio {
- mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
- pins = "PG0";
- function = "gpio_in";
- bias-pull-up;
- };
-
- led_pins_olinuxino: led_pins@0 {
+ led_pins_olinuxino: led-pin {
pins = "PG9";
function = "gpio_out";
drive-strength = <20>;
};
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PG2";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-down;
- };
-
- usb1_vbus_pin_olinuxino: usb1_vbus_pin@0 {
- pins = "PG11";
- function = "gpio_out";
- };
};
®_usb0_vbus {
@@ -243,7 +210,6 @@
};
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_olinuxino>;
gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@@ -263,7 +229,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@@ -273,10 +239,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
- usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+ usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts
new file mode 100644
index 0000000000..d60407772e
--- /dev/null
+++ b/arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright 2019 Ondrej Jirman <megous@megous.com>
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "PocketBook Touch Lux 3";
+ compatible = "pocketbook,touch-lux-3", "allwinner,sun5i-a13";
+
+ aliases {
+ serial0 = &uart1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+ enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ power-supply = <®_vcc3v3>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led {
+ gpios = <&pio 4 8 GPIO_ACTIVE_LOW>; /* PE8 */
+ default-state = "on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ label = "GPIO Keys";
+
+ key-right {
+ label = "Right";
+ linux,code = <KEY_RIGHT>;
+ gpios = <&pio 6 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG9 */
+ };
+
+ key-left {
+ label = "Left";
+ linux,code = <KEY_LEFT>;
+ gpios = <&pio 6 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PG10 */
+ };
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-1v8-nor-ctp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 2 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_1v8_nor: regulator-nor {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-nor";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_1v8>;
+ regulator-always-on;
+ };
+
+ reg_1v8_ctp: regulator-ctp {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-ctp";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ gpio = <&pio 2 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ vin-supply = <®_1v8>;
+ };
+
+ reg_3v3_mmc0: regulator-mmc0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-mmc0";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&pio 4 4 GPIO_ACTIVE_LOW>; /* PE4 */
+ vin-supply = <®_vcc3v3>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ status = "okay";
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* Touchpanel is connected here. */
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button-200 {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button-400 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_3v3_mmc0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
+ status = "okay";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_4bit_pc_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd-int-pll";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+ /* We need this otherwise the LDO3 would overload */
+ regulator-soft-start;
+ regulator-ramp-delay = <1600>;
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
+ status = "okay";
+
+ epd_flash: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "macronix,mx25u4033", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pg_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_ldo3>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun5i-a13-q8-tablet.dts b/arch/arm/dts/sun5i-a13-q8-tablet.dts
index a89f29fa3e..f9fc1c8b60 100644
--- a/arch/arm/dts/sun5i-a13-q8-tablet.dts
+++ b/arch/arm/dts/sun5i-a13-q8-tablet.dts
@@ -49,19 +49,13 @@
compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
panel: panel {
- compatible = "urt,umsh-8596md-t", "simple-panel";
- #address-cells = <1>;
- #size-cells = <0>;
+ compatible = "bananapi,s070wv20-ct16";
+ power-supply = <®_vcc3v3>;
+ enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
+ backlight = <&backlight>;
- port@0 {
- reg = <0>;
- /* TODO: lcd panel uses axp gpio0 as enable pin */
- backlight = <&backlight>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- panel_input: endpoint@0 {
- reg = <0>;
+ port {
+ panel_input: endpoint {
remote-endpoint = <&tcon0_out_lcd>;
};
};
diff --git a/arch/arm/dts/sun5i-a13-utoo-p66.dts b/arch/arm/dts/sun5i-a13-utoo-p66.dts
index bfdd38d6bf..be486d28d0 100644
--- a/arch/arm/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/dts/sun5i-a13-utoo-p66.dts
@@ -58,13 +58,11 @@
/delete-property/stdout-path;
};
- i2c_lcd: i2c@0 {
+ i2c_lcd: i2c {
/* The lcd panel i2c interface is hooked up via gpios */
compatible = "i2c-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_lcd_pins>;
- gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>, /* PG12, sda */
- <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10, scl */
+ sda-gpios = <&pio 6 12 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG12 */
+ scl-gpios = <&pio 6 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG10 */
i2c-gpio,delay-us = <5>;
};
};
@@ -79,13 +77,9 @@
allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */
};
-&codec_pa_pin {
- pins = "PG3";
-};
-
&mmc2 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
+ pinctrl-0 = <&mmc2_8bit_pins>;
vmmc-supply = <®_vcc3v3>;
bus-width = <8>;
non-removable;
@@ -98,14 +92,6 @@
};
};
-&pio {
- i2c_lcd_pins: i2c_lcd_pin@0 {
- pins = "PG10", "PG12";
- function = "gpio_out";
- bias-pull-up;
- };
-};
-
®_usb0_vbus {
gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
};
@@ -128,7 +114,3 @@
/* The P66 uses the uart pins as gpios */
status = "disabled";
};
-
-&usb0_vbus_pin_a {
- pins = "PB4";
-};
diff --git a/arch/arm/dts/sun5i-a13.dtsi b/arch/arm/dts/sun5i-a13.dtsi
index b1d8277655..3325ab0709 100644
--- a/arch/arm/dts/sun5i-a13.dtsi
+++ b/arch/arm/dts/sun5i-a13.dtsi
@@ -42,17 +42,13 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include "sun5i.dtsi"
#include <dt-bindings/thermal/thermal.h>
/ {
- interrupt-parent = <&intc>;
-
thermal-zones {
- cpu_thermal {
+ cpu-thermal {
/* milliseconds */
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -88,7 +84,7 @@
allwinner,pipelines = <&fe0>;
};
- soc@1c00000 {
+ soc {
pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a13-pwm";
reg = <0x01c20e00 0xc>;
@@ -106,15 +102,14 @@
&cpu0 {
clock-latency = <244144>; /* 8 32k periods */
- operating-points = <
+ operating-points =
/* kHz uV */
- 1008000 1400000
- 912000 1350000
- 864000 1300000
- 624000 1200000
- 576000 1200000
- 432000 1200000
- >;
+ <1008000 1400000>,
+ <912000 1350000>,
+ <864000 1300000>,
+ <624000 1200000>,
+ <576000 1200000>,
+ <432000 1200000>;
#cooling-cells = <2>;
};
diff --git a/arch/arm/dts/sun5i-gr8-chip-pro.dts b/arch/arm/dts/sun5i-gr8-chip-pro.dts
index c55b11a4d3..a32cde3e32 100644
--- a/arch/arm/dts/sun5i-gr8-chip-pro.dts
+++ b/arch/arm/dts/sun5i-gr8-chip-pro.dts
@@ -79,8 +79,6 @@
mmc0_pwrseq: mmc0_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_reg_on_pin_chip_pro>;
reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
};
};
@@ -94,8 +92,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@@ -114,20 +110,16 @@
#include "axp209.dtsi"
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "disabled";
};
&i2s0 {
pinctrl-names = "default";
- pinctrl-0 = <&i2s0_mclk_pins_a>, <&i2s0_data_pins_a>;
+ pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>;
status = "disabled";
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&mmc0_pwrseq>;
bus-width = <4>;
@@ -137,12 +129,10 @@
&nfc {
pinctrl-names = "default";
- pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>;
+ pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
status = "okay";
nand@0 {
- #address-cells = <2>;
- #size-cells = <2>;
reg = <0>;
allwinner,rb = <0>;
nand-ecc-mode = "hw";
@@ -157,21 +147,9 @@
status = "okay";
};
-&pio {
- usb0_id_pin_chip_pro: usb0-id-pin@0 {
- pins = "PG2";
- function = "gpio_in";
- };
-
- wifi_reg_on_pin_chip_pro: wifi-reg-on-pin@0 {
- pins = "PB10";
- function = "gpio_out";
- };
-};
-
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
+ pinctrl-0 = <&pwm0_pin>, <&pwm1_pins>;
status = "disabled";
};
@@ -220,19 +198,19 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>, <&uart1_cts_rts_pins_a>;
+ pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins_a>, <&uart2_cts_rts_pins_a>;
+ pinctrl-0 = <&uart2_pd_pins>, <&uart2_cts_rts_pd_pins>;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_a>, <&uart3_cts_rts_pins_a>;
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>;
status = "okay";
};
@@ -253,9 +231,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_pin_chip_pro>;
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb1_vbus-supply = <®_vcc5v0>;
status = "okay";
diff --git a/arch/arm/dts/sun5i-gr8-evb.dts b/arch/arm/dts/sun5i-gr8-evb.dts
new file mode 100644
index 0000000000..f4fe258ef0
--- /dev/null
+++ b/arch/arm/dts/sun5i-gr8-evb.dts
@@ -0,0 +1,333 @@
+/*
+ * Copyright 2016 Free Electrons
+ * Copyright 2016 NextThing Co
+ *
+ * Mylène Josserand <mylene.josserand@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-gr8.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ model = "NextThing GR8-EVB";
+ compatible = "nextthing,gr8-evb", "nextthing,gr8";
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 10000 0>;
+ enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
+ power-supply = <®_vcc3v3>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+ default-brightness-level = <8>;
+ };
+
+ sound-analog {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "gr8-evb-wm8978";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,mclk-fs = <512>;
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&wm8978>;
+ };
+ };
+
+ sound-spdif {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "On-board SPDIF";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+};
+
+&be0 {
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+
+ /*
+ * The interrupt is routed through the "External Fast
+ * Interrupt Request" pin (ball G13 of the module)
+ * directly to the main interrupt controller, without
+ * any other controller interfering.
+ */
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ status = "okay";
+
+ wm8978: codec@1a {
+ #sound-dai-cells = <0>;
+ compatible = "wlf,wm8978";
+ reg = <0x1a>;
+ };
+
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2s0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_mclk_pin>, <&i2s0_data_pins>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pin>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button-190 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <190000>;
+ };
+
+ button-390 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <390000>;
+ };
+
+ button-600 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button-800 {
+ label = "Search";
+ linux,code = <KEY_SEARCH>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+
+ button-980 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <980000>;
+ };
+
+ button-1180 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1180000>;
+ };
+
+ button-1400 {
+ label = "Enter";
+ linux,code = <KEY_ENTER>;
+ channel = <0>;
+ voltage = <1400000>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
+ status = "okay";
+};
+
+&nfc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
+
+ /* MLC Support sucks for now */
+ status = "disabled";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+ regulator-always-on;
+};
+
+®_dcdc3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-sys";
+ regulator-always-on;
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+ regulator-always-on;
+};
+
+®_usb1_vbus {
+ gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&rtp {
+ allwinner,ts-attached;
+};
+
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_tx_pin>;
+ status = "okay";
+};
+
+&tve0 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ /*
+ * The GR8-EVB has a somewhat interesting design. There's a
+ * pin supposed to control VBUS, an ID pin, a VBUS detect pin,
+ * so everything should work just fine.
+ *
+ * Except that the pin supposed to control VBUS is not
+ * connected to any controllable output, neither to the SoC
+ * through a GPIO or to the PMIC, and it is pulled down,
+ * meaning that we will never be able to enable VBUS on this
+ * board.
+ */
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun5i-gr8.dtsi b/arch/arm/dts/sun5i-gr8.dtsi
index ef0b7446a9..98a8fd5e89 100644
--- a/arch/arm/dts/sun5i-gr8.dtsi
+++ b/arch/arm/dts/sun5i-gr8.dtsi
@@ -54,7 +54,7 @@
allwinner,pipelines = <&fe0>;
};
- soc@1c00000 {
+ soc {
pwm: pwm@1c20e00 {
compatible = "allwinner,sun5i-a10s-pwm";
reg = <0x01c20e00 0xc>;
@@ -98,28 +98,28 @@
&pio {
compatible = "nextthing,gr8-pinctrl";
- i2s0_data_pins_a: i2s0-data@0 {
+ i2s0_data_pins: i2s0-data-pins {
pins = "PB6", "PB7", "PB8", "PB9";
function = "i2s0";
};
- i2s0_mclk_pins_a: i2s0-mclk@0 {
+ i2s0_mclk_pin: i2s0-mclk-pin {
pins = "PB5";
function = "i2s0";
};
- pwm1_pins: pwm1 {
+ pwm1_pins: pwm1-pin {
pins = "PG13";
function = "pwm1";
};
- spdif_tx_pins_a: spdif@0 {
+ spdif_tx_pin: spdif-tx-pin {
pins = "PB10";
function = "spdif";
bias-pull-up;
};
- uart1_cts_rts_pins_a: uart1-cts-rts@0 {
+ uart1_cts_rts_pins: uart1-cts-rts-pins {
pins = "PG5", "PG6";
function = "uart1";
};
diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts
index 879a4b0f3b..4bf4943d4e 100644
--- a/arch/arm/dts/sun5i-r8-chip.dts
+++ b/arch/arm/dts/sun5i-r8-chip.dts
@@ -79,16 +79,12 @@
mmc0_pwrseq: mmc0_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&chip_wifi_reg_on_pin>;
reset-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
};
onewire {
compatible = "w1-gpio";
- gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
- pinctrl-names = "default";
- pinctrl-0 = <&chip_w1_pin>;
+ gpios = <&pio 3 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD2 */
};
};
@@ -109,8 +105,6 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
axp209: pmic@34 {
@@ -137,14 +131,10 @@
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "disabled";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
xio: gpio@38 {
@@ -161,13 +151,11 @@
};
};
-&mmc0_pins_a {
+&mmc0_pins {
bias-pull-up;
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_vcc3v3>;
mmc-pwrseq = <&mmc0_pwrseq>;
bus-width = <4>;
@@ -183,29 +171,6 @@
status = "okay";
};
-&pio {
- chip_vbus_pin: chip_vbus_pin@0 {
- pins = "PB10";
- function = "gpio_out";
- };
-
- chip_wifi_reg_on_pin: chip_wifi_reg_on_pin@0 {
- pins = "PC19";
- function = "gpio_out";
- };
-
- chip_id_det_pin: chip_id_det_pin@0 {
- pins = "PG2";
- function = "gpio_in";
- };
-
- chip_w1_pin: chip_w1_pin@0 {
- pins = "PD2";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_dcdc2 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
@@ -260,7 +225,6 @@
};
®_usb0_vbus {
- pinctrl-0 = <&chip_vbus_pin>;
vin-supply = <®_vcc5v0>;
gpio = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
status = "okay";
@@ -268,7 +232,7 @@
&spi2 {
pinctrl-names = "default";
- pinctrl-0 = <&spi2_pins_a>;
+ pinctrl-0 = <&spi2_pe_pins>;
status = "disabled";
};
@@ -282,14 +246,14 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins_a>,
- <&uart3_cts_rts_pins_a>;
+ pinctrl-0 = <&uart3_pg_pins>,
+ <&uart3_cts_rts_pg_pins>;
status = "okay";
};
@@ -303,11 +267,9 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&chip_id_det_pin>;
status = "okay";
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_id_det-gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_vcc5v0>;
diff --git a/arch/arm/dts/sun5i-reference-design-tablet.dtsi b/arch/arm/dts/sun5i-reference-design-tablet.dtsi
index 8acbaab14f..6847f66699 100644
--- a/arch/arm/dts/sun5i-reference-design-tablet.dtsi
+++ b/arch/arm/dts/sun5i-reference-design-tablet.dtsi
@@ -54,7 +54,8 @@
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
- /* TODO: backlight uses axp gpio1 as enable pin */
+ enable-gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>; /* AXP GPIO1 */
+ power-supply = <®_vcc3v0>;
};
chosen {
@@ -63,8 +64,6 @@
};
&codec {
- pinctrl-names = "default";
- pinctrl-0 = <&codec_pa_pin>;
allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */
status = "okay";
};
@@ -92,11 +91,10 @@
*/
clock-frequency = <400000>;
- touchscreen: touchscreen {
+ touchscreen: touchscreen@40 {
+ reg = <0x40>;
interrupt-parent = <&pio>;
interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
- pinctrl-names = "default";
- pinctrl-0 = <&ts_power_pin>;
power-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
/* Tablet dts must provide reg and compatible */
status = "disabled";
@@ -124,7 +122,7 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
@@ -135,43 +133,6 @@
status = "okay";
};
-&pio {
- codec_pa_pin: codec_pa_pin@0 {
- pins = "PG10";
- function = "gpio_out";
- };
-
- mmc0_cd_pin: mmc0_cd_pin@0 {
- pins = "PG0";
- function = "gpio_in";
- bias-pull-up;
- };
-
- ts_power_pin: ts_power_pin {
- pins = "PB3";
- function = "gpio_out";
- drive-strength = <10>;
- bias-disable;
- };
-
- usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
- pins = "PG1";
- function = "gpio_in";
- bias-pull-down;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PG2";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_vbus_pin_a: usb0_vbus_pin@0 {
- pins = "PG12";
- function = "gpio_out";
- };
-};
-
®_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
@@ -210,7 +171,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_b>;
+ pinctrl-0 = <&uart1_pg_pins>;
status = "okay";
};
@@ -224,10 +185,8 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
- usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
- usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
+ usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_usb0_vbus>;
usb1_vbus-supply = <®_ldo3>;
diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi
index 07f2248ed5..250d6b87ab 100644
--- a/arch/arm/dts/sun5i.dtsi
+++ b/arch/arm/dts/sun5i.dtsi
@@ -42,14 +42,14 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/clock/sun5i-ccu.h>
#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/reset/sun5i-ccu.h>
/ {
interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
cpus {
#address-cells = <1>;
@@ -68,7 +68,7 @@
#size-cells = <1>;
ranges;
- framebuffer@0 {
+ framebuffer-lcd0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
@@ -77,7 +77,7 @@
status = "disabled";
};
- framebuffer@1 {
+ framebuffer-lcd0-tve0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-tve0";
@@ -93,14 +93,14 @@
#size-cells = <1>;
ranges;
- osc24M: clk@1c20050 {
+ osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
- osc32k: clk@0 {
+ osc32k: clk-32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
@@ -108,14 +108,30 @@
};
};
- soc@1c00000 {
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
+ default-pool {
+ compatible = "shared-dma-pool";
+ size = <0x6000000>;
+ alloc-ranges = <0x40000000 0x10000000>;
+ reusable;
+ linux,cma-default;
+ };
+ };
+
+ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
+ dma-ranges;
ranges;
- sram-controller@1c00000 {
- compatible = "allwinner,sun4i-a10-sram-controller";
+ system-control@1c00000 {
+ compatible = "allwinner,sun5i-a13-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
@@ -127,12 +143,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x00000000 0xc000>;
- };
- emac_sram: sram-section@8000 {
- compatible = "allwinner,sun4i-a10-sram-a3-a4";
- reg = <0x8000 0x4000>;
- status = "disabled";
+ emac_sram: sram-section@8000 {
+ compatible = "allwinner,sun5i-a13-sram-a3-a4",
+ "allwinner,sun4i-a10-sram-a3-a4";
+ reg = <0x8000 0x4000>;
+ status = "disabled";
+ };
};
sram_d: sram@10000 {
@@ -143,11 +160,36 @@
ranges = <0 0x00010000 0x1000>;
otg_sram: sram-section@0 {
- compatible = "allwinner,sun4i-a10-sram-d";
+ compatible = "allwinner,sun5i-a13-sram-d",
+ "allwinner,sun4i-a10-sram-d";
reg = <0x0000 0x1000>;
status = "disabled";
};
};
+
+ sram_c: sram@1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0xd0000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0xd0000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun5i-a13-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x80000>;
+ };
+ };
+ };
+
+ mbus: dram-controller@1c01000 {
+ compatible = "allwinner,sun5i-a13-mbus";
+ reg = <0x01c01000 0x1000>;
+ clocks = <&ccu CLK_MBUS>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x40000000 0x20000000>;
+ #interconnect-cells = <1>;
};
dma: dma-controller@1c02000 {
@@ -158,7 +200,7 @@
#dma-cells = <2>;
};
- nfc: nand@1c03000 {
+ nfc: nand-controller@1c03000 {
compatible = "allwinner,sun4i-a10-nand";
reg = <0x01c03000 0x1000>;
interrupts = <37>;
@@ -207,11 +249,8 @@
status = "disabled";
port {
- #address-cells = <1>;
- #size-cells = <0>;
- tve0_in_tcon0: endpoint@0 {
- reg = <0>;
+ tve0_in_tcon0: endpoint {
remote-endpoint = <&tcon0_out_tve0>;
};
};
@@ -238,6 +277,7 @@
compatible = "allwinner,sun5i-a13-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <44>;
+ dmas = <&dma SUN4I_DMA_DEDICATED 14>;
resets = <&ccu RST_LCD>;
reset-names = "lcd";
clocks = <&ccu CLK_AHB_LCD>,
@@ -247,6 +287,7 @@
"tcon-ch0",
"tcon-ch1";
clock-output-names = "tcon-pixel-clock";
+ #clock-cells = <0>;
status = "disabled";
ports {
@@ -254,12 +295,9 @@
#size-cells = <0>;
tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- tcon0_in_be0: endpoint@0 {
- reg = <0>;
+ tcon0_in_be0: endpoint {
remote-endpoint = <&be0_out_tcon0>;
};
};
@@ -278,12 +316,25 @@
};
};
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun5i-a13-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_VE>;
+ interrupts = <53>;
+ allwinner,sram = <&ve_sram 1>;
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun5i-a13-mmc";
reg = <0x01c0f000 0x1000>;
clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
clock-names = "ahb", "mmc";
interrupts = <32>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -321,13 +372,14 @@
phy-names = "usb";
extcon = <&usbphy 0>;
allwinner,sram = <&otg_sram 1>;
+ dr_mode = "otg";
status = "disabled";
};
usbphy: phy@1c13400 {
#phy-cells = <1>;
compatible = "allwinner,sun5i-a13-usb-phy";
- reg = <0x01c13400 0x10 0x01c14800 0x4>;
+ reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
reg-names = "phy_ctrl", "pmu1";
clocks = <&ccu CLK_USB_PHY0>;
clock-names = "usb_phy";
@@ -404,7 +456,7 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
- emac_pins_a: emac0@0 {
+ emac_pd_pins: emac-pd-pins {
pins = "PD6", "PD7", "PD10",
"PD11", "PD12", "PD13", "PD14",
"PD15", "PD18", "PD19", "PD20",
@@ -413,27 +465,27 @@
function = "emac";
};
- i2c0_pins_a: i2c0@0 {
+ i2c0_pins: i2c0-pins {
pins = "PB0", "PB1";
function = "i2c0";
};
- i2c1_pins_a: i2c1@0 {
+ i2c1_pins: i2c1-pins {
pins = "PB15", "PB16";
function = "i2c1";
};
- i2c2_pins_a: i2c2@0 {
+ i2c2_pins: i2c2-pins {
pins = "PB17", "PB18";
function = "i2c2";
};
- ir0_rx_pins_a: ir0@0 {
+ ir0_rx_pin: ir0-rx-pin {
pins = "PB4";
function = "ir0";
};
- lcd_rgb565_pins: lcd_rgb565@0 {
+ lcd_rgb565_pins: lcd-rgb565-pins {
pins = "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD19", "PD20", "PD21", "PD22", "PD23",
@@ -441,7 +493,7 @@
function = "lcd0";
};
- lcd_rgb666_pins: lcd_rgb666@0 {
+ lcd_rgb666_pins: lcd-rgb666-pins {
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
"PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
@@ -449,7 +501,7 @@
function = "lcd0";
};
- mmc0_pins_a: mmc0@0 {
+ mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2", "PF3",
"PF4", "PF5";
function = "mmc0";
@@ -457,24 +509,24 @@
bias-pull-up;
};
- mmc2_pins_a: mmc2@0 {
+ mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
pins = "PC6", "PC7", "PC8", "PC9",
- "PC10", "PC11", "PC12", "PC13",
- "PC14", "PC15";
+ "PC10", "PC11";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
- mmc2_4bit_pins_a: mmc2-4bit@0 {
+ mmc2_8bit_pins: mmc2-8bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
- "PC10", "PC11";
+ "PC10", "PC11", "PC12", "PC13",
+ "PC14", "PC15";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
- nand_pins_a: nand-base0@0 {
+ nand_pins: nand-pins {
pins = "PC0", "PC1", "PC2",
"PC5", "PC8", "PC9", "PC10",
"PC11", "PC12", "PC13", "PC14",
@@ -482,72 +534,79 @@
function = "nand0";
};
- nand_cs0_pins_a: nand-cs@0 {
+ nand_cs0_pin: nand-cs0-pin {
pins = "PC4";
function = "nand0";
};
- nand_rb0_pins_a: nand-rb@0 {
+ nand_rb0_pin: nand-rb0-pin {
pins = "PC6";
function = "nand0";
};
- spi2_pins_a: spi2@0 {
+ pwm0_pin: pwm0-pin {
+ pins = "PB2";
+ function = "pwm";
+ };
+
+ spi2_pe_pins: spi2-pe-pins {
pins = "PE1", "PE2", "PE3";
function = "spi2";
};
- spi2_cs0_pins_a: spi2-cs0@0 {
+ spi2_cs0_pe_pin: spi2-cs0-pe-pin {
pins = "PE0";
function = "spi2";
};
- uart1_pins_a: uart1@0 {
+ uart1_pe_pins: uart1-pe-pins {
pins = "PE10", "PE11";
function = "uart1";
};
- uart1_pins_b: uart1@1 {
+ uart1_pg_pins: uart1-pg-pins {
pins = "PG3", "PG4";
function = "uart1";
};
- uart2_pins_a: uart2@0 {
+ uart2_pd_pins: uart2-pd-pins {
pins = "PD2", "PD3";
function = "uart2";
};
- uart2_cts_rts_pins_a: uart2-cts-rts@0 {
+ uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
pins = "PD4", "PD5";
function = "uart2";
};
- uart3_pins_a: uart3@0 {
+ uart3_pg_pins: uart3-pg-pins {
pins = "PG9", "PG10";
function = "uart3";
};
- uart3_cts_rts_pins_a: uart3-cts-rts@0 {
+ uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
pins = "PG11", "PG12";
function = "uart3";
};
-
- pwm0_pins: pwm0 {
- pins = "PB2";
- function = "pwm";
- };
};
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <22>;
+ interrupts = <22>,
+ <23>,
+ <24>,
+ <25>,
+ <67>,
+ <68>;
clocks = <&ccu CLK_HOSC>;
};
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
+ interrupts = <24>;
+ clocks = <&osc24M>;
};
ir0: ir@1c21800 {
@@ -636,6 +695,8 @@
reg = <0x01c2ac00 0x400>;
interrupts = <7>;
clocks = <&ccu CLK_APB1_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -646,6 +707,8 @@
reg = <0x01c2b000 0x400>;
interrupts = <8>;
clocks = <&ccu CLK_APB1_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -656,11 +719,25 @@
reg = <0x01c2b400 0x400>;
interrupts = <9>;
clocks = <&ccu CLK_APB1_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
+ mali: gpu@1c40000 {
+ compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <69>, <70>, <71>, <72>, <73>;
+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu";
+ clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_GPU>;
+ assigned-clocks = <&ccu CLK_GPU>;
+ assigned-clock-rates = <320000000>;
+ };
+
timer@1c60000 {
compatible = "allwinner,sun5i-a13-hstimer";
reg = <0x01c60000 0x1000>;
@@ -677,6 +754,8 @@
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_DE_FE>;
+ interconnects = <&mbus 19>;
+ interconnect-names = "dma-mem";
status = "disabled";
ports {
@@ -684,12 +763,9 @@
#size-cells = <0>;
fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- fe0_out_be0: endpoint@0 {
- reg = <0>;
+ fe0_out_be0: endpoint {
remote-endpoint = <&be0_in_fe0>;
};
};
@@ -705,33 +781,26 @@
clock-names = "ahb", "mod",
"ram";
resets = <&ccu RST_DE_BE>;
+ interconnects = <&mbus 18>;
+ interconnect-names = "dma-mem";
status = "disabled";
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- be0_in_fe0: endpoint@0 {
- reg = <0>;
+ be0_in_fe0: endpoint {
remote-endpoint = <&fe0_out_be0>;
};
};
be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- be0_out_tcon0: endpoint@0 {
- reg = <0>;
+ be0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_be0>;
};
};
diff --git a/arch/arm/dts/sun6i-a31-app4-evb1.dts b/arch/arm/dts/sun6i-a31-app4-evb1.dts
index 7f34323a66..32d22025ac 100644
--- a/arch/arm/dts/sun6i-a31-app4-evb1.dts
+++ b/arch/arm/dts/sun6i-a31-app4-evb1.dts
@@ -65,22 +65,14 @@
status = "okay";
};
-&pio {
- usb1_vbus_pin_a: usb1_vbus_pin@0 {
- pins = "PH27";
- function = "gpio_out";
- };
-};
-
®_usb1_vbus {
- pinctrl-0 = <&usb1_vbus_pin_a>;
gpio = <&pio 7 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31-colombus.dts b/arch/arm/dts/sun6i-a31-colombus.dts
index 939c497a6f..93a15eaaa8 100644
--- a/arch/arm/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/dts/sun6i-a31-colombus.dts
@@ -60,13 +60,11 @@
stdout-path = "serial0:115200n8";
};
- i2c_lcd: i2c@0 {
+ i2c_lcd: i2c {
/* The lcd panel i2c interface is hooked up via gpios */
compatible = "i2c-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c_lcd_pins>;
- gpios = <&pio 0 23 GPIO_ACTIVE_HIGH>, /* PA23, sda */
- <&pio 0 24 GPIO_ACTIVE_HIGH>; /* PA24, scl */
+ sda-gpios = <&pio 0 23 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA23 */
+ scl-gpios = <&pio 0 24 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA24 */
i2c-gpio,delay-us = <5>;
};
};
@@ -77,31 +75,21 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "fail";
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
mma8452: mma8452@1d {
@@ -112,48 +100,27 @@
};
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
-&mmc0_pins_a {
- bias-pull-up;
-};
-
-&pio {
- mmc0_cd_pin_colombus: mmc0_cd_pin@0 {
- pins = "PA8";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb2_vbus_pin_colombus: usb2_vbus_pin@0 {
- pins = "PH24";
- function = "gpio_out";
- };
-
- i2c_lcd_pins: i2c_lcd_pin@0 {
- pins = "PA23", "PA24";
- function = "gpio_out";
- bias-pull-up;
- };
-};
-
®_usb2_vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_vbus_pin_colombus>;
gpio = <&pio 7 24 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31-hummingbird.dts b/arch/arm/dts/sun6i-a31-hummingbird.dts
index 2c14358035..486cec6f71 100644
--- a/arch/arm/dts/sun6i-a31-hummingbird.dts
+++ b/arch/arm/dts/sun6i-a31-hummingbird.dts
@@ -86,31 +86,23 @@
vga-dac {
compatible = "dumb-vga-dac";
vdd-supply = <®_vga_3v3>;
- #address-cells = <1>;
- #size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- vga_dac_in: endpoint@0 {
- reg = <0>;
+ vga_dac_in: endpoint {
remote-endpoint = <&tcon0_out_vga>;
};
};
port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- vga_dac_out: endpoint@0 {
- reg = <0>;
+ vga_dac_out: endpoint {
remote-endpoint = <&vga_con_in>;
};
};
@@ -160,17 +152,10 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_hummingbird>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii-id";
- snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>;
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 30000>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -184,21 +169,15 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
/* pull-ups and devices require AXP221 DLDO3 */
status = "failed";
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
pcf8563: rtc@51 {
@@ -209,27 +188,27 @@
&ir {
pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+ pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
-&mmc0_pins_a {
- /* external pull-ups missing for some pins */
- bias-pull-up;
-};
-
&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_hummingbird>;
vmmc-supply = <®_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@@ -241,31 +220,13 @@
status = "okay";
};
-&pio {
- gmac_phy_reset_pin_hummingbird: gmac_phy_reset_pin@0 {
- pins = "PA21";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
- pins = "PA8";
- function = "gpio_in";
- bias-pull-up;
- };
-
- wifi_reset_pin_hummingbird: wifi_reset_pin@0 {
- pins = "PG10";
- function = "gpio_out";
- };
-};
-
&p2wi {
status = "okay";
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en;
};
@@ -354,7 +315,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
@@ -368,8 +329,8 @@
};
&usbphy {
- usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
- usb0_vbus_det-gpio = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
+ usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ usb0_vbus_det-gpios = <&pio 0 16 GPIO_ACTIVE_HIGH>; /* PA16 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_drivevbus>;
usb1_vbus-supply = <®_usb1_vbus>;
diff --git a/arch/arm/dts/sun6i-a31-i7.dts b/arch/arm/dts/sun6i-a31-i7.dts
index d659be9dbc..744723d956 100644
--- a/arch/arm/dts/sun6i-a31-i7.dts
+++ b/arch/arm/dts/sun6i-a31-i7.dts
@@ -71,10 +71,8 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_i7>;
- blue {
+ led {
label = "i7:blue:usr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
};
@@ -118,14 +116,10 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_mii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -140,48 +134,31 @@
&ir {
pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+ pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_i7>;
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
status = "okay";
};
-&pio {
- led_pins_i7: led_pins@0 {
- pins = "PH13";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_i7: mmc0_cd_pin@0 {
- pins = "PH22";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb1_vbus_pin_i7: usb1_vbus_pin@0 {
- pins = "PC27";
- function = "gpio_out";
- };
-};
-
®_usb1_vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_vbus_pin_i7>;
gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&spdif {
pinctrl-names = "default";
- pinctrl-0 = <&spdif_pins_a>;
- spdif-out = "okay";
+ pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
@@ -191,7 +168,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31-m9.dts b/arch/arm/dts/sun6i-a31-m9.dts
index 9698f6d38d..e4f3415e61 100644
--- a/arch/arm/dts/sun6i-a31-m9.dts
+++ b/arch/arm/dts/sun6i-a31-m9.dts
@@ -60,10 +60,8 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_m9>;
- blue {
+ led {
label = "m9:blue:pwr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -85,26 +83,26 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_mii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <®_dldo1>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&ir {
pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+ pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
@@ -117,31 +115,13 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
#include "axp22x.dtsi"
-&pio {
- led_pins_m9: led_pins@0 {
- pins = "PH13";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_m9: mmc0_cd_pin@0 {
- pins = "PH22";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb1_vbus_pin_m9: usb1_vbus_pin@0 {
- pins = "PC27";
- function = "gpio_out";
- };
-};
-
®_aldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -215,15 +195,13 @@
};
®_usb1_vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_vbus_pin_m9>;
gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts
index bb14b171b1..7bd4bdd66a 100644
--- a/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -60,10 +60,8 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_m9>;
- blue {
+ led {
label = "a1000g:blue:pwr";
gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
default-state = "on";
@@ -85,26 +83,26 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_mii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <®_dldo1>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&ir {
pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+ pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
@@ -117,31 +115,13 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
#include "axp22x.dtsi"
-&pio {
- led_pins_m9: led_pins@0 {
- pins = "PH13";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_m9: mmc0_cd_pin@0 {
- pins = "PH22";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb1_vbus_pin_m9: usb1_vbus_pin@0 {
- pins = "PC27";
- function = "gpio_out";
- };
-};
-
®_aldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -215,15 +195,13 @@
};
®_usb1_vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_vbus_pin_m9>;
gpio = <&pio 2 27 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
index 32ab9751c6..dde9bdf2f9 100644
--- a/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
+++ b/arch/arm/dts/sun6i-a31-mixtile-loftq.dts
@@ -31,11 +31,13 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
status = "okay";
+};
+&mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
@@ -51,6 +53,6 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31.dtsi b/arch/arm/dts/sun6i-a31.dtsi
index c72992556a..d7d920e9e4 100644
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -42,8 +42,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
@@ -52,6 +50,8 @@
/ {
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
aliases {
ethernet0 = &gmac;
@@ -62,7 +62,7 @@
#size-cells = <1>;
ranges;
- simplefb_hdmi: framebuffer@0 {
+ simplefb_hdmi: framebuffer-lcd0-hdmi {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0-hdmi";
@@ -73,7 +73,7 @@
status = "disabled";
};
- simplefb_lcd: framebuffer@1 {
+ simplefb_lcd: framebuffer-lcd0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
@@ -105,37 +105,63 @@
reg = <0>;
clocks = <&ccu CLK_CPU>;
clock-latency = <244144>; /* 8 32k periods */
- operating-points = <
+ operating-points =
/* kHz uV */
- 1008000 1200000
- 864000 1200000
- 720000 1100000
- 480000 1000000
- >;
+ <1008000 1200000>,
+ <864000 1200000>,
+ <720000 1100000>,
+ <480000 1000000>;
#cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <1>;
+ clocks = <&ccu CLK_CPU>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points =
+ /* kHz uV */
+ <1008000 1200000>,
+ <864000 1200000>,
+ <720000 1100000>,
+ <480000 1000000>;
+ #cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
+ clocks = <&ccu CLK_CPU>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points =
+ /* kHz uV */
+ <1008000 1200000>,
+ <864000 1200000>,
+ <720000 1100000>,
+ <480000 1000000>;
+ #cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
+ clocks = <&ccu CLK_CPU>;
+ clock-latency = <244144>; /* 8 32k periods */
+ operating-points =
+ /* kHz uV */
+ <1008000 1200000>,
+ <864000 1200000>,
+ <720000 1100000>,
+ <480000 1000000>;
+ #cooling-cells = <2>;
};
};
thermal-zones {
- cpu_thermal {
+ cpu-thermal {
/* milliseconds */
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -144,7 +170,10 @@
cooling-maps {
map0 {
trip = <&cpu_alert0>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
@@ -166,12 +195,8 @@
};
};
- memory {
- reg = <0x40000000 0x80000000>;
- };
-
pmu {
- compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
@@ -183,17 +208,20 @@
#size-cells = <1>;
ranges;
- osc24M: osc24M {
+ osc24M: clk-24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
+ clock-accuracy = <50000>;
+ clock-output-names = "osc24M";
};
- osc32k: clk@0 {
+ osc32k: clk-32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
- clock-output-names = "osc32k";
+ clock-accuracy = <50000>;
+ clock-output-names = "ext_osc32k";
};
/*
@@ -205,14 +233,14 @@
* The actual TX clock rate is not controlled by the
* gmac_tx clock.
*/
- mii_phy_tx_clk: clk@1 {
+ mii_phy_tx_clk: clk-mii-phy-tx {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
clock-output-names = "mii_phy_tx";
};
- gmac_int_tx_clk: clk@2 {
+ gmac_int_tx_clk: clk-gmac-int-tx {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <125000000>;
@@ -234,7 +262,7 @@
status = "disabled";
};
- soc@1c00000 {
+ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -253,15 +281,21 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0c000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_AHB1_LCD0>;
- reset-names = "lcd";
+ dmas = <&dma 11>;
+ resets = <&ccu RST_AHB1_LCD0>,
+ <&ccu RST_AHB1_LVDS>;
+ reset-names = "lcd",
+ "lvds";
clocks = <&ccu CLK_AHB1_LCD0>,
<&ccu CLK_LCD0_CH0>,
- <&ccu CLK_LCD0_CH1>;
+ <&ccu CLK_LCD0_CH1>,
+ <&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
- "tcon-ch1";
+ "tcon-ch1",
+ "lvds-alt";
clock-output-names = "tcon0-pixel-clock";
+ #clock-cells = <0>;
ports {
#address-cells = <1>;
@@ -301,15 +335,20 @@
compatible = "allwinner,sun6i-a31-tcon";
reg = <0x01c0d000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- resets = <&ccu RST_AHB1_LCD1>;
- reset-names = "lcd";
+ dmas = <&dma 12>;
+ resets = <&ccu RST_AHB1_LCD1>,
+ <&ccu RST_AHB1_LVDS>;
+ reset-names = "lcd", "lvds";
clocks = <&ccu CLK_AHB1_LCD1>,
<&ccu CLK_LCD1_CH0>,
- <&ccu CLK_LCD1_CH1>;
+ <&ccu CLK_LCD1_CH1>,
+ <&ccu 15>;
clock-names = "ahb",
"tcon-ch0",
- "tcon-ch1";
+ "tcon-ch1",
+ "lvds-alt";
clock-output-names = "tcon1-pixel-clock";
+ #clock-cells = <0>;
ports {
#address-cells = <1>;
@@ -359,6 +398,8 @@
resets = <&ccu RST_AHB1_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -378,6 +419,8 @@
resets = <&ccu RST_AHB1_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -431,7 +474,6 @@
<&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
resets = <&ccu RST_AHB1_HDMI>;
- reset-names = "ahb";
dma-names = "ddc-tx", "ddc-rx", "audio-tx";
dmas = <&dma 13>, <&dma 13>, <&dma 14>;
status = "disabled";
@@ -457,8 +499,6 @@
};
hdmi_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
};
};
@@ -474,6 +514,7 @@
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
+ dr_mode = "otg";
status = "disabled";
};
@@ -557,7 +598,7 @@
ccu: clock@1c20000 {
compatible = "allwinner,sun6i-a31-ccu";
reg = <0x01c20000 0x400>;
- clocks = <&osc24M>, <&osc32k>;
+ clocks = <&osc24M>, <&rtc 0>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -570,14 +611,14 @@
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
+ clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
#gpio-cells = <3>;
- gmac_pins_gmii_a: gmac_gmii@0 {
+ gmac_gmii_pins: gmac-gmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
"PA8", "PA9", "PA10", "PA11",
@@ -593,7 +634,7 @@
drive-strength = <30>;
};
- gmac_pins_mii_a: gmac_mii@0 {
+ gmac_mii_pins: gmac-mii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA8", "PA9", "PA11",
"PA12", "PA13", "PA14", "PA19",
@@ -602,7 +643,7 @@
function = "gmac";
};
- gmac_pins_rgmii_a: gmac_rgmii@0 {
+ gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA9", "PA10", "PA11",
"PA12", "PA13", "PA14", "PA19",
@@ -615,22 +656,22 @@
drive-strength = <40>;
};
- i2c0_pins_a: i2c0@0 {
+ i2c0_pins: i2c0-pins {
pins = "PH14", "PH15";
function = "i2c0";
};
- i2c1_pins_a: i2c1@0 {
+ i2c1_pins: i2c1-pins {
pins = "PH16", "PH17";
function = "i2c1";
};
- i2c2_pins_a: i2c2@0 {
+ i2c2_pins: i2c2-pins {
pins = "PH18", "PH19";
function = "i2c2";
};
- lcd0_rgb888_pins: lcd0_rgb888 {
+ lcd0_rgb888_pins: lcd0-rgb888-pins {
pins = "PD0", "PD1", "PD2", "PD3",
"PD4", "PD5", "PD6", "PD7",
"PD8", "PD9", "PD10", "PD11",
@@ -641,7 +682,7 @@
function = "lcd0";
};
- mmc0_pins_a: mmc0@0 {
+ mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
function = "mmc0";
@@ -649,7 +690,7 @@
bias-pull-up;
};
- mmc1_pins_a: mmc1@0 {
+ mmc1_pins: mmc1-pins {
pins = "PG0", "PG1", "PG2", "PG3",
"PG4", "PG5";
function = "mmc1";
@@ -657,7 +698,7 @@
bias-pull-up;
};
- mmc2_pins_a: mmc2@0 {
+ mmc2_4bit_pins: mmc2-4bit-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11";
function = "mmc2";
@@ -665,7 +706,7 @@
bias-pull-up;
};
- mmc2_8bit_emmc_pins: mmc2@1 {
+ mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
"PC13", "PC14", "PC15",
@@ -675,7 +716,7 @@
bias-pull-up;
};
- mmc3_8bit_emmc_pins: mmc3@1 {
+ mmc3_8bit_emmc_pins: mmc3-8bit-emmc-pins {
pins = "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12",
"PC13", "PC14", "PC15",
@@ -685,12 +726,12 @@
bias-pull-up;
};
- spdif_pins_a: spdif@0 {
+ spdif_tx_pin: spdif-tx-pin {
pins = "PH28";
function = "spdif";
};
- uart0_pins_a: uart0@0 {
+ uart0_ph_pins: uart0-ph-pins {
pins = "PH20", "PH21";
function = "uart0";
};
@@ -703,13 +744,16 @@
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
wdt1: watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
spdif: spdif@1c21000 {
@@ -849,6 +893,8 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB2_I2C0>;
resets = <&ccu RST_APB2_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -860,6 +906,8 @@
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB2_I2C1>;
resets = <&ccu RST_APB2_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -871,6 +919,8 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB2_I2C2>;
resets = <&ccu RST_APB2_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -900,8 +950,12 @@
snps,fixed-burst;
snps,force_sf_dma_mode;
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
crypto: crypto-engine@1c15000 {
@@ -950,6 +1004,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI0>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
spi1: spi@1c69000 {
@@ -962,6 +1018,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI1>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
spi2: spi@1c6a000 {
@@ -974,6 +1032,8 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI2>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
spi3: spi@1c6b000 {
@@ -986,10 +1046,12 @@
dma-names = "rx", "tx";
resets = <&ccu RST_AHB1_SPI3>;
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
};
gic: interrupt-controller@1c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
@@ -1073,9 +1135,6 @@
"ram";
resets = <&ccu RST_AHB1_BE1>;
- assigned-clocks = <&ccu CLK_BE1>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1119,9 +1178,6 @@
"ram";
resets = <&ccu RST_AHB1_DRC1>;
- assigned-clocks = <&ccu CLK_IEP_DRC1>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1165,9 +1221,6 @@
"ram";
resets = <&ccu RST_AHB1_BE0>;
- assigned-clocks = <&ccu CLK_BE0>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -1189,12 +1242,9 @@
};
be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- be0_out_drc0: endpoint@0 {
- reg = <0>;
+ be0_out_drc0: endpoint {
remote-endpoint = <&drc0_in_be0>;
};
};
@@ -1211,20 +1261,14 @@
"ram";
resets = <&ccu RST_AHB1_DRC0>;
- assigned-clocks = <&ccu CLK_IEP_DRC0>;
- assigned-clock-rates = <300000000>;
-
ports {
#address-cells = <1>;
#size-cells = <0>;
drc0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- drc0_in_be0: endpoint@0 {
- reg = <0>;
+ drc0_in_be0: endpoint {
remote-endpoint = <&be0_out_drc0>;
};
};
@@ -1248,13 +1292,16 @@
};
rtc: rtc@1f00000 {
+ #clock-cells = <1>;
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc32k>;
+ clock-output-names = "osc32k";
};
- nmi_intc: interrupt-controller@1f00c00 {
+ r_intc: interrupt-controller@1f00c00 {
compatible = "allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
@@ -1269,7 +1316,7 @@
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
- clocks = <&osc32k>, <&osc24M>,
+ clocks = <&rtc 0>, <&osc24M>,
<&ccu CLK_PLL_PERIPH>,
<&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
@@ -1304,7 +1351,7 @@
ir_clk: ir_clk {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
- clocks = <&osc32k>, <&osc24M>;
+ clocks = <&rtc 0>, <&osc24M>;
clock-output-names = "ir";
};
@@ -1320,7 +1367,7 @@
};
ir: ir@1f02000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
clocks = <&apb0_gates 1>, <&ir_clk>;
clock-names = "apb", "ir";
resets = <&apb0_rst 1>;
@@ -1334,21 +1381,20 @@
reg = <0x01f02c00 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb0_gates 0>, <&osc24M>, <&osc32k>;
+ clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
- #size-cells = <0>;
#gpio-cells = <3>;
- ir_pins_a: ir@0 {
+ s_ir_rx_pin: s-ir-rx-pin {
pins = "PL4";
function = "s_ir";
};
- p2wi_pins: p2wi {
+ s_p2wi_pins: s-p2wi-pins {
pins = "PL0", "PL1";
function = "s_p2wi";
};
@@ -1362,7 +1408,7 @@
clock-frequency = <100000>;
resets = <&apb0_rst 3>;
pinctrl-names = "default";
- pinctrl-0 = <&p2wi_pins>;
+ pinctrl-0 = <&s_p2wi_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts
index 882a4d89fa..a2ef7846e2 100644
--- a/arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts
+++ b/arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts
@@ -53,7 +53,7 @@
vref-supply = <®_aldo3>;
status = "okay";
- button@1000 {
+ button-1000 {
label = "Home";
linux,code = <KEY_HOMEPAGE>;
channel = <0>;
diff --git a/arch/arm/dts/sun6i-a31s-cs908.dts b/arch/arm/dts/sun6i-a31s-cs908.dts
index 75e578159c..1d15e15011 100644
--- a/arch/arm/dts/sun6i-a31s-cs908.dts
+++ b/arch/arm/dts/sun6i-a31s-cs908.dts
@@ -66,28 +66,31 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_mii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
status = "okay";
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&ir {
pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+ pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&ohci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31s-inet-q972.dts b/arch/arm/dts/sun6i-a31s-inet-q972.dts
index e584e6b186..c5e2c55cdc 100644
--- a/arch/arm/dts/sun6i-a31s-inet-q972.dts
+++ b/arch/arm/dts/sun6i-a31s-inet-q972.dts
@@ -54,8 +54,6 @@
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
ft5406ee8: touchscreen@38 {
@@ -73,21 +71,21 @@
vref-supply = <®_aldo3>;
status = "okay";
- button@200 {
+ button-200 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <200000>;
};
- button@900 {
+ button-900 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <900000>;
};
- button@1200 {
+ button-1200 {
label = "Back";
linux,code = <KEY_BACK>;
channel = <0>;
diff --git a/arch/arm/dts/sun6i-a31s-primo81.dts b/arch/arm/dts/sun6i-a31s-primo81.dts
index 4cb9664cdb..66bc6ca77a 100644
--- a/arch/arm/dts/sun6i-a31s-primo81.dts
+++ b/arch/arm/dts/sun6i-a31s-primo81.dts
@@ -90,19 +90,13 @@
&i2c0 {
/* pull-ups and device VDDIO use AXP221 DLDO3 */
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "failed";
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
ctp@5d {
- pinctrl-names = "default";
- pinctrl-0 = <>911_int_primo81>;
compatible = "goodix,gt911";
reg = <0x5d>;
interrupt-parent = <&pio>;
@@ -112,8 +106,6 @@
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
accelerometer@1c {
@@ -123,7 +115,6 @@
reg = <0x1c>;
interrupt-parent = <&pio>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; /* PA9 */
- #io-channel-cells = <1>;
};
};
@@ -131,14 +122,14 @@
vref-supply = <®_aldo3>;
status = "okay";
- button@158 {
+ button-158 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <158730>;
};
- button@349 {
+ button-349 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@@ -147,8 +138,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_primo81>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
@@ -156,22 +145,11 @@
};
&pio {
- gt911_int_primo81: gt911_int_pin@0 {
- pins = "PA3";
- function = "gpio_in";
- };
-
- mma8452_int_primo81: mma8452_int_pin@0 {
+ mma8452_int_primo81: mma8452-int-pin {
pins = "PA9";
function = "gpio_in";
bias-pull-up;
};
-
- mmc0_cd_pin_primo81: mmc0_cd_pin@0 {
- pins = "PA8";
- function = "gpio_in";
- bias-pull-up;
- };
};
&p2wi {
@@ -180,7 +158,7 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en;
};
@@ -281,7 +259,7 @@
};
&usbphy {
- usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ usb0_id_det-gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_drivevbus>;
usb1_vbus-supply = <®_dldo1>;
diff --git a/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi
index d7325bc4ee..7455c0db4a 100644
--- a/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi
+++ b/arch/arm/dts/sun6i-a31s-sina31s-core.dtsi
@@ -78,7 +78,7 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -135,7 +135,7 @@
/* UART0 pads available on core board */
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31s-sina31s.dts b/arch/arm/dts/sun6i-a31s-sina31s.dts
index da0ccf5a2c..0af48e143b 100644
--- a/arch/arm/dts/sun6i-a31s-sina31s.dts
+++ b/arch/arm/dts/sun6i-a31s-sina31s.dts
@@ -66,8 +66,6 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pin_sina31s>;
status {
label = "sina31s:status:usr";
@@ -116,15 +114,11 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_mii_a>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_mii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "mii";
phy-supply = <®_dldo1>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&hdmi {
@@ -139,7 +133,7 @@
&ir {
pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+ pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
@@ -147,14 +141,14 @@
vref-supply = <®_aldo3>;
status = "okay";
- button@158 {
+ button-158 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <158730>;
};
- button@349 {
+ button-349 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@@ -162,9 +156,13 @@
};
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina31s>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
@@ -175,19 +173,6 @@
status = "okay";
};
-&pio {
- led_pin_sina31s: led_pin@0 {
- pins = "PH13";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_sina31s: mmc0_cd_pin@0 {
- pins = "PA4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
®_dldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@@ -196,7 +181,7 @@
&spdif {
pinctrl-names = "default";
- pinctrl-0 = <&spdif_pins_a>;
+ pinctrl-0 = <&spdif_tx_pin>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index b8b79c0e9e..efb25b949f 100644
--- a/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -58,20 +58,18 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_bpi_m2>;
- blue {
+ led-0 {
label = "bpi-m2:blue:usr";
gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
};
- green {
+ led-1 {
label = "bpi-m2:green:usr";
gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */
};
- red {
+ led-2 {
label = "bpi-m2:red:usr";
gpios = <&pio 6 5 GPIO_ACTIVE_HIGH>; /* PG5 */
};
@@ -79,8 +77,6 @@
mmc2_pwrseq: mmc2_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pwrseq_pin_bpi_m2>;
reset-gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 WIFI_EN */
};
};
@@ -95,42 +91,38 @@
&gmac {
pinctrl-names = "default";
- pinctrl-0 = <&gmac_pins_rgmii_a>, <&gmac_phy_reset_pin_bpi_m2>;
- phy = <&phy1>;
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <®_dldo1>;
- snps,reset-gpio = <&pio 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
- snps,reset-active-low;
- snps,reset-delays-us = <0 10000 30000>;
status = "okay";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
};
&ir {
pinctrl-names = "default";
- pinctrl-0 = <&ir_pins_a>;
+ pinctrl-0 = <&s_ir_rx_pin>;
status = "okay";
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ reset-gpios = <&pio 0 21 GPIO_ACTIVE_LOW>; /* PA21 */
+ reset-assert-us = <10000>;
+ reset-deassert-us = <30000>;
+ };
+};
+
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m2>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
status = "okay";
};
-&mmc0_pins_a {
- bias-pull-up;
-};
-
&mmc2 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc2_pins_a>;
+ pinctrl-0 = <&mmc2_4bit_pins>;
vmmc-supply = <®_aldo1>;
mmc-pwrseq = <&mmc2_pwrseq>;
bus-width = <4>;
@@ -146,10 +138,6 @@
};
};
-&mmc2_pins_a {
- bias-pull-up;
-};
-
&ohci0 {
status = "okay";
};
@@ -160,38 +148,13 @@
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <®_dcdc1>;
x-powers,drive-vbus-en;
};
};
-&pio {
- gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 {
- pins = "PA21";
- function = "gpio_out";
- };
-
- led_pins_bpi_m2: led_pins@0 {
- pins = "PG5", "PG10", "PG11";
- function = "gpio_out";
- };
-
- mmc0_cd_pin_bpi_m2: mmc0_cd_pin@0 {
- pins = "PA4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
-&r_pio {
- mmc2_pwrseq_pin_bpi_m2: mmc2_pwrseq_pin@0 {
- pins = "PL8";
- function = "gpio_out";
- };
-};
-
#include "axp22x.dtsi"
®_aldo1 {
@@ -291,10 +254,81 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
&usbphy {
status = "okay";
};
+
+&pio {
+ gpio-line-names =
+ /* PA */
+ "ETXD0", "ETXD1", "ETXD2", "ETXD3", "SDC0-DET", "", "",
+ "", "ETXCLK", "ETXEN", "EGTXCLK", "ERXD0", "ERXD1",
+ "ERXD2", "ERXD3", "", "", "", "", "ERXDV", "ERXCK",
+ "ETXERR", "ERXERR", "ECOL", "ECRS", "ECLKIN", "EMDC",
+ "EMDIO", "", "", "", "",
+
+ /* PB */
+ "CN7-P29", "CN7-P31", "CN7-P33", "CN7-P35", "CN7-P37",
+ "CN7-P28", "CN7-P27", "CN7-P32", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "",
+
+ /* PC */
+ "", "", "", "", "", "", "WL-SDIO-CMD", "WL-SDIO-CLK",
+ "WL-SDIO-D0", "WL-SDIO-D2", "WL-SDIO-D2", "WL-SDIO-D3",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "USB-DRV", "", "", "", "",
+
+ /* PD */
+ "CN9-P09", "CN9-P11", "CN9-P13", "CN9-P15", "CN9-P17",
+ "CN9-P19", "CN9-P21", "CN9-P23", "CN9-P25", "CN9-P27",
+ "CN9-P29", "CN9-P31", "CN9-P33", "CN9-P35", "CN9-P37",
+ "CN9-P39", "CN9-P40", "CN9-P38", "CN9-P36", "CN9-P34",
+ "CN9-P32", "CN9-P30", "CN9-P28", "CN9-P26", "CN9-P22",
+ "CN9-P14", "CN9-P18", "CN9-P16", "", "", "", "",
+
+ /* PE */
+ "CN6-P20", "CN6-P24", "CN6-P30", "CN6-P28", "CN7-P08",
+ "CN7-P10", "CN7-P36", "CN7-P38", "CN6-P17", "CN6-P19",
+ "CN6-P21", "CN6-P23", "CN6-P25", "CN6-P27", "CN6-P29",
+ "CN6-P31", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "",
+
+ /* PF */
+ "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
+ "SDC0-D2", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "",
+
+ /* PG */
+ "CN9-P06", "CN9-P08", "CN9-P20", "CN9-P12", "CN9-P07",
+ "LED-PWR", "CN7-P13", "CN7-P11", "CN7-P22", "CN7-P15",
+ "LED-G", "LED-B", "CN7-P26", "CN7-P24", "CN7-P23",
+ "CN7-P19", "CN7-P21", "HCEC", "CN6-P22", "", "", "", "",
+ "", "", "", "", "", "", "", "", "",
+
+ /* PH */
+ "", "", "", "", "", "", "", "", "", "CN7-P07",
+ "CN7-P12", "CN7-P16", "CN7-P18", "CN9-P10", "CN6-P16",
+ "CN6-P14", "CN9-P04", "CN9-P02", "CN7-P05", "CN7-P03",
+ "CN8-P03", "CN8-P02", "", "", "CN6-P34", "CN6-P32",
+ "CN6-P26", "CN6-P18", "", "", "", "";
+};
+
+&r_pio {
+ gpio-line-names =
+ /* PL */
+ "PMU-SCK", "PMU-SDA", "VBAT-EN", "", "IR-RX",
+ "WL-WAKE-HOST", "BT-WAKE_HOST", "BT-ENABLE",
+ "WL-PMU-EN", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "",
+
+ /* PM */
+ "CN6-P12", "CN6-P35", "CN7-P40", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "";
+};
diff --git a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
index aab6c1720e..cadc45255d 100644
--- a/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
+++ b/arch/arm/dts/sun6i-a31s-yones-toptech-bs1078-v2.dts
@@ -62,14 +62,10 @@
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
status = "okay";
};
@@ -89,34 +85,20 @@
status = "okay";
};
-&pio {
- mmc0_cd_pin_bs1078v2: mmc0_cd_pin@0 {
- pins = "PA8";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bs1078v2>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
-&mmc0_pins_a {
- bias-pull-up;
-};
-
&p2wi {
status = "okay";
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
@@ -189,7 +171,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
+ pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/dts/sun6i-reference-design-tablet.dtsi
index 4e72e4f3ef..6bf3fbdd73 100644
--- a/arch/arm/dts/sun6i-reference-design-tablet.dtsi
+++ b/arch/arm/dts/sun6i-reference-design-tablet.dtsi
@@ -66,34 +66,20 @@
&mmc0 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>;
+ pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
status = "okay";
};
-&pio {
- mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 {
- pins = "PA8";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PA15";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
&p2wi {
status = "okay";
axp22x: pmic@68 {
compatible = "x-powers,axp221";
reg = <0x68>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
drivevbus-supply = <®_vcc5v0>;
x-powers,drive-vbus-en;
@@ -179,9 +165,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */
+ usb0_id_det-gpios = <&pio 0 15 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PA15 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_drivevbus>;
usb1_vbus-supply = <®_dldo1>;
diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi
index 44f3cad3de..a42fac676b 100644
--- a/arch/arm/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/dts/sun8i-a23-a33.dtsi
@@ -42,8 +42,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "skeleton.dtsi"
-
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
@@ -51,13 +49,15 @@
/ {
interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
chosen {
#address-cells = <1>;
#size-cells = <1>;
ranges;
- simplefb_lcd: framebuffer@0 {
+ simplefb_lcd: framebuffer-lcd0 {
compatible = "allwinner,simple-framebuffer",
"simple-framebuffer";
allwinner,pipeline = "de_be0-lcd0";
@@ -68,6 +68,12 @@
};
};
+ de: display-engine {
+ /* compatible gets set in SoC specific dtsi file */
+ allwinner,pipelines = <&fe0>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -118,12 +124,34 @@
};
};
- soc@1c00000 {
+ soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
+ system-control@1c00000 {
+ compatible = "allwinner,sun8i-a23-system-control";
+ reg = <0x01c00000 0x30>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@1d00000 {
+ compatible = "mmio-sram";
+ reg = <0x01d00000 0x80000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x01d00000 0x80000>;
+
+ ve_sram: sram-section@0 {
+ compatible = "allwinner,sun8i-a23-sram-c1",
+ "allwinner,sun4i-a10-sram-c1";
+ reg = <0x000000 0x80000>;
+ };
+ };
+ };
+
dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-a23-dma";
reg = <0x01c02000 0x1000>;
@@ -133,6 +161,60 @@
#dma-cells = <1>;
};
+ nfc: nand-controller@1c03000 {
+ compatible = "allwinner,sun8i-a23-nand-controller";
+ reg = <0x01c03000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_NAND>;
+ reset-names = "ahb";
+ dmas = <&dma 5>;
+ dma-names = "rxtx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ tcon0: lcd-controller@1c0c000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01c0c000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma 12>;
+ clocks = <&ccu CLK_BUS_LCD>,
+ <&ccu CLK_LCD_CH0>,
+ <&ccu 13>;
+ clock-names = "ahb",
+ "tcon-ch0",
+ "lvds-alt";
+ clock-output-names = "tcon-pixel-clock";
+ #clock-cells = <0>;
+ resets = <&ccu RST_BUS_LCD>,
+ <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd",
+ "lvds";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ reg = <0>;
+
+ tcon0_in_drc0: endpoint {
+ remote-endpoint = <&drc0_out_tcon0>;
+ };
+ };
+
+ tcon0_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun7i-a20-mmc";
reg = <0x01c0f000 0x1000>;
@@ -147,6 +229,8 @@
resets = <&ccu RST_BUS_MMC0>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -190,21 +274,6 @@
#size-cells = <0>;
};
- nfc: nand@1c03000 {
- compatible = "allwinner,sun4i-a10-nand";
- reg = <0x01c03000 0x1000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
- clock-names = "ahb", "mod";
- resets = <&ccu RST_BUS_NAND>;
- reset-names = "ahb";
- pinctrl-names = "default";
- pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
usb_otg: usb@1c19000 {
/* compatible gets set in SoC specific dtsi file */
reg = <0x01c19000 0x0400>;
@@ -215,6 +284,7 @@
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
+ dr_mode = "otg";
status = "disabled";
};
@@ -276,22 +346,30 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
- uart0_pins_a: uart0@0 {
- pins = "PF2", "PF4";
- function = "uart0";
+ i2c0_pins: i2c0-pins {
+ pins = "PH2", "PH3";
+ function = "i2c0";
};
- uart1_pins_a: uart1@0 {
- pins = "PG6", "PG7";
- function = "uart1";
+ i2c1_pins: i2c1-pins {
+ pins = "PH4", "PH5";
+ function = "i2c1";
};
- uart1_pins_cts_rts_a: uart1-cts-rts@0 {
- pins = "PG8", "PG9";
- function = "uart1";
+ i2c2_pins: i2c2-pins {
+ pins = "PE12", "PE13";
+ function = "i2c2";
};
- mmc0_pins_a: mmc0@0 {
+ lcd_rgb666_pins: lcd-rgb666-pins {
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+ "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+ "PD24", "PD25", "PD26", "PD27";
+ function = "lcd0";
+ };
+
+ mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
function = "mmc0";
@@ -299,7 +377,7 @@
bias-pull-up;
};
- mmc1_pins_a: mmc1@0 {
+ mmc1_pg_pins: mmc1-pg-pins {
pins = "PG0", "PG1", "PG2",
"PG3", "PG4", "PG5";
function = "mmc1";
@@ -307,7 +385,7 @@
bias-pull-up;
};
- mmc2_8bit_pins: mmc2_8bit {
+ mmc2_8bit_pins: mmc2-8bit-pins {
pins = "PC5", "PC6", "PC8",
"PC9", "PC10", "PC11",
"PC12", "PC13", "PC14",
@@ -324,61 +402,53 @@
function = "nand0";
};
- nand_pins_cs0: nand-pins-cs0 {
+ nand_cs0_pin: nand-cs0-pin {
pins = "PC4";
function = "nand0";
bias-pull-up;
};
- nand_pins_cs1: nand-pins-cs1 {
+ nand_cs1_pin: nand-cs1-pin {
pins = "PC3";
function = "nand0";
bias-pull-up;
};
- nand_pins_rb0: nand-pins-rb0 {
+ nand_rb0_pin: nand-rb0-pin {
pins = "PC6";
function = "nand0";
bias-pull-up;
};
- nand_pins_rb1: nand-pins-rb1 {
+ nand_rb1_pin: nand-rb1-pin {
pins = "PC7";
function = "nand0";
bias-pull-up;
};
- pwm0_pins: pwm0 {
+ pwm0_pin: pwm0-pin {
pins = "PH0";
function = "pwm0";
};
- i2c0_pins_a: i2c0@0 {
- pins = "PH2", "PH3";
- function = "i2c0";
- };
-
- i2c1_pins_a: i2c1@0 {
- pins = "PH4", "PH5";
- function = "i2c1";
+ uart0_pf_pins: uart0-pf-pins {
+ pins = "PF2", "PF4";
+ function = "uart0";
};
- i2c2_pins_a: i2c2@0 {
- pins = "PE12", "PE13";
- function = "i2c2";
+ uart1_pg_pins: uart1-pg-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
};
- lcd_rgb666_pins: lcd-rgb666@0 {
- pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
- "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
- "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
- "PD24", "PD25", "PD26", "PD27";
- function = "lcd0";
+ uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
+ pins = "PG8", "PG9";
+ function = "uart1";
};
};
timer@1c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
+ compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -389,6 +459,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
pwm: pwm@1c21400 {
@@ -477,6 +548,8 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -488,6 +561,8 @@
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -499,6 +574,8 @@
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -532,7 +609,7 @@
};
gic: interrupt-controller@1c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
@@ -542,17 +619,104 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ fe0: display-frontend@1e00000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01e00000 0x20000>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
+ <&ccu CLK_DRAM_DE_FE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_BUS_DE_FE>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fe0_out: port@1 {
+ reg = <1>;
+
+ fe0_out_be0: endpoint {
+ remote-endpoint = <&be0_in_fe0>;
+ };
+ };
+ };
+ };
+
+ be0: display-backend@1e60000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01e60000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>;
+ clock-names = "ahb", "mod",
+ "ram";
+ resets = <&ccu RST_BUS_DE_BE>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ be0_in: port@0 {
+ reg = <0>;
+
+ be0_in_fe0: endpoint {
+ remote-endpoint = <&fe0_out_be0>;
+ };
+ };
+
+ be0_out: port@1 {
+ reg = <1>;
+
+ be0_out_drc0: endpoint {
+ remote-endpoint = <&drc0_in_be0>;
+ };
+ };
+ };
+ };
+
+ drc0: drc@1e70000 {
+ /* compatible gets set in SoC specific dtsi file */
+ reg = <0x01e70000 0x10000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
+ <&ccu CLK_DRAM_DRC>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_DRC>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ drc0_in: port@0 {
+ reg = <0>;
+
+ drc0_in_be0: endpoint {
+ remote-endpoint = <&be0_out_drc0>;
+ };
+ };
+
+ drc0_out: port@1 {
+ reg = <1>;
+
+ drc0_out_tcon0: endpoint {
+ remote-endpoint = <&tcon0_in_drc0>;
+ };
+ };
+ };
+ };
+
rtc: rtc@1f00000 {
- compatible = "allwinner,sun6i-a31-rtc";
- reg = <0x01f00000 0x54>;
+ compatible = "allwinner,sun8i-a23-rtc";
+ reg = <0x01f00000 0x400>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clock-output-names = "osc32k";
+ clock-output-names = "osc32k", "osc32k-out";
clocks = <&ext_osc32k>;
#clock-cells = <1>;
};
- nmi_intc: interrupt-controller@1f00c00 {
+ r_intc: interrupt-controller@1f00c00 {
compatible = "allwinner,sun6i-a31-r-intc";
interrupt-controller;
#interrupt-cells = <2>;
@@ -624,6 +788,20 @@
status = "disabled";
};
+ r_i2c: i2c@1f02400 {
+ compatible = "allwinner,sun8i-a23-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01f02400 0x400>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins>;
+ clocks = <&apb0_gates 6>;
+ resets = <&apb0_rst 6>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a23-r-pinctrl";
reg = <0x01f02c00 0x400>;
@@ -634,18 +812,22 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
#gpio-cells = <3>;
- r_rsb_pins: r_rsb {
+ r_i2c_pins: r-i2c-pins {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ bias-pull-up;
+ };
+
+ r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
drive-strength = <20>;
bias-pull-up;
};
- r_uart_pins_a: r_uart@0 {
+ r_uart_pins_a: r-uart-pins {
pins = "PL2", "PL3";
function = "s_uart";
};
diff --git a/arch/arm/dts/sun8i-a23-evb.dts b/arch/arm/dts/sun8i-a23-evb.dts
index 8a93697df3..53fb1be040 100644
--- a/arch/arm/dts/sun8i-a23-evb.dts
+++ b/arch/arm/dts/sun8i-a23-evb.dts
@@ -65,14 +65,10 @@
};
&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
};
@@ -80,21 +76,21 @@
vref-supply = <®_vcc3v0>;
status = "okay";
- button@190 {
+ button-190 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <190000>;
};
- button@390 {
+ button-390 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <390000>;
};
- button@600 {
+ button-600 {
label = "Home";
linux,code = <KEY_HOME>;
channel = <0>;
@@ -103,22 +99,12 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_evb>;
vmmc-supply = <®_vcc3v0>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
-&pio {
- mmc0_cd_pin_evb: mmc0_cd_pin@0 {
- pins = "PB4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
/*
* The RX line has a non-populated resistance. In order to use it, you
* need to solder R207 on the back of the board in order to close the
diff --git a/arch/arm/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/dts/sun8i-a23-gt90h-v4.dts
index e3c7a25ca3..bcbc9b0758 100644
--- a/arch/arm/dts/sun8i-a23-gt90h-v4.dts
+++ b/arch/arm/dts/sun8i-a23-gt90h-v4.dts
@@ -63,7 +63,7 @@
};
&lradc {
- button@600 {
+ button-600 {
label = "Back";
linux,code = <KEY_BACK>;
channel = <0>;
diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts b/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts
new file mode 100644
index 0000000000..51097c77a1
--- /dev/null
+++ b/arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sun8i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A23 Tablet";
+ compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
+};
+
+&codec {
+ allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ allwinner,audio-routing =
+ "Headphone", "HP",
+ "Headphone", "HPCOM",
+ "Speaker", "HP",
+ "MIC1", "Mic",
+ "MIC2", "Headset Mic",
+ "Mic", "MBIAS",
+ "Headset Mic", "HBIAS";
+ status = "okay";
+};
+
+&panel {
+ compatible = "bananapi,s070wv20-ct16";
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+};
diff --git a/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
new file mode 100644
index 0000000000..51097c77a1
--- /dev/null
+++ b/arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sun8i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A23 Tablet";
+ compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
+};
+
+&codec {
+ allwinner,pa-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ allwinner,audio-routing =
+ "Headphone", "HP",
+ "Headphone", "HPCOM",
+ "Speaker", "HP",
+ "MIC1", "Mic",
+ "MIC2", "Headset Mic",
+ "Mic", "MBIAS",
+ "Headset Mic", "HBIAS";
+ status = "okay";
+};
+
+&panel {
+ compatible = "bananapi,s070wv20-ct16";
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+};
diff --git a/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts
index 649e313396..d5f6aebd72 100644
--- a/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts
+++ b/arch/arm/dts/sun8i-a23-polaroid-mid2407pxe03.dts
@@ -54,8 +54,6 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_pwrseq_pin_mid2407>;
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
/* The esp8089 needs 200 ms after driving wifi-en high */
post-power-on-delay-ms = <200>;
@@ -71,7 +69,7 @@
&mmc1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <®_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@@ -85,17 +83,6 @@
};
};
-&mmc1_pins_a {
- bias-pull-up;
-};
-
-&r_pio {
- wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 {
- pins = "PL6";
- function = "gpio_out";
- };
-};
-
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl1680";
diff --git a/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts
index 6b3bcae089..9f9232a2fe 100644
--- a/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts
+++ b/arch/arm/dts/sun8i-a23-polaroid-mid2809pxe04.dts
@@ -54,8 +54,6 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
- pinctrl-names = "default";
- pinctrl-0 = <&wifi_pwrseq_pin_mid2809>;
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */
/* The esp8089 needs 200 ms after driving wifi-en high */
post-power-on-delay-ms = <200>;
@@ -64,7 +62,7 @@
&mmc1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <®_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@@ -78,17 +76,6 @@
};
};
-&mmc1_pins_a {
- bias-pull-up;
-};
-
-&r_pio {
- wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 {
- pins = "PL6";
- function = "gpio_out";
- };
-};
-
&touchscreen {
reg = <0x40>;
compatible = "silead,gsl3670";
diff --git a/arch/arm/dts/sun8i-a23-q8-tablet.dts b/arch/arm/dts/sun8i-a23-q8-tablet.dts
index b6958e8f2f..51097c77a1 100644
--- a/arch/arm/dts/sun8i-a23-q8-tablet.dts
+++ b/arch/arm/dts/sun8i-a23-q8-tablet.dts
@@ -61,3 +61,13 @@
"Headset Mic", "HBIAS";
status = "okay";
};
+
+&panel {
+ compatible = "bananapi,s070wv20-ct16";
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+};
diff --git a/arch/arm/dts/sun8i-a23.dtsi b/arch/arm/dts/sun8i-a23.dtsi
index 58e6585b50..a5e884a8b2 100644
--- a/arch/arm/dts/sun8i-a23.dtsi
+++ b/arch/arm/dts/sun8i-a23.dtsi
@@ -45,11 +45,7 @@
#include "sun8i-a23-a33.dtsi"
/ {
- memory {
- reg = <0x40000000 0x40000000>;
- };
-
- soc@1c00000 {
+ soc {
codec: codec@1c22c00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-a23-codec";
@@ -66,10 +62,26 @@
};
};
+&be0 {
+ compatible = "allwinner,sun8i-a23-display-backend";
+};
+
&ccu {
compatible = "allwinner,sun8i-a23-ccu";
};
+&de {
+ compatible = "allwinner,sun8i-a23-display-engine";
+};
+
+&drc0 {
+ compatible = "allwinner,sun8i-a23-drc";
+};
+
+&fe0 {
+ compatible = "allwinner,sun8i-a23-display-frontend";
+};
+
&pio {
compatible = "allwinner,sun8i-a23-pinctrl";
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -77,6 +89,10 @@
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
};
+&tcon0 {
+ compatible = "allwinner,sun8i-a23-tcon";
+};
+
&usb_otg {
compatible = "allwinner,sun6i-a31-musb";
};
diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts b/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts
similarity index 81%
rename from arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
rename to arch/arm/dts/sun8i-a33-et-q8-v1.6.dts
index e5590208ed..9c5750c256 100644
--- a/arch/arm/dts/sun8i-r16-nintendo-nes-classic-edition.dts
+++ b/arch/arm/dts/sun8i-a33-et-q8-v1.6.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016 FUKAUMI Naoki <naobsd@gmail.com>
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -42,34 +42,16 @@
/dts-v1/;
#include "sun8i-a33.dtsi"
+#include "sun8i-q8-common.dtsi"
/ {
- model = "Nintendo NES Classic Edition";
- compatible = "nintendo,nes-classic-edition", "allwinner,sun8i-a33";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
+ model = "Q8 A33 Tablet";
+ compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
};
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
-};
-
-&nfc {
- status = "okay";
-
- nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
+&tcon0_out {
+ tcon0_out_lcd: endpoint@0 {
reg = <0>;
- allwinner,rb = <0>;
- nand-ecc-mode = "hw";
+ remote-endpoint = <&panel_input>;
};
};
diff --git a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts
index f71159987c..2dfdd0a315 100644
--- a/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts
+++ b/arch/arm/dts/sun8i-a33-ga10h-v1.1.dts
@@ -69,7 +69,7 @@
};
&lradc {
- button@600 {
+ button-600 {
label = "Back";
linux,code = <KEY_BACK>;
channel = <0>;
@@ -79,7 +79,7 @@
&mmc1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <®_dldo1>;
bus-width = <4>;
non-removable;
diff --git a/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts
index 3e05959104..065cb620aa 100644
--- a/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts
+++ b/arch/arm/dts/sun8i-a33-inet-d978-rev2.dts
@@ -63,20 +63,16 @@
pinctrl-names = "default";
pinctrl-0 = <&led_pin_d978>;
- home {
+ led {
label = "d978:blue:home";
gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
};
};
};
-&mmc1_pins_a {
- bias-pull-up;
-};
-
&mmc1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <®_dldo1>;
bus-width = <4>;
non-removable;
@@ -88,7 +84,7 @@
};
&r_pio {
- led_pin_d978: led_pin_d978@0 {
+ led_pin_d978: led-pin {
pins = "PL5";
function = "gpio_out";
drive-strength = <20>;
@@ -101,7 +97,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>,
- <&uart1_pins_cts_rts_a>;
+ pinctrl-0 = <&uart1_pg_pins>,
+ <&uart1_cts_rts_pg_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
new file mode 100644
index 0000000000..9c5750c256
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sun8i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A33 Tablet";
+ compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
+};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
diff --git a/arch/arm/dts/sun8i-a33-olinuxino.dts b/arch/arm/dts/sun8i-a33-olinuxino.dts
index a1a1eb64ca..8538514c85 100644
--- a/arch/arm/dts/sun8i-a33-olinuxino.dts
+++ b/arch/arm/dts/sun8i-a33-olinuxino.dts
@@ -62,7 +62,7 @@
leds {
compatible = "gpio-leds";
- green {
+ led {
label = "a33-olinuxino:green:usr";
gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
};
@@ -82,8 +82,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
@@ -100,7 +98,7 @@
axp22x: pmic@3a3 {
compatible = "x-powers,axp223";
reg = <0x3a3>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <®_dcdc1>;
x-powers,drive-vbus-en;
@@ -196,8 +194,8 @@
"Headphone", "Headphone Jack";
/* Board level routing. First 2 routes copied from SoC level */
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right",
+ "Left DAC", "DACL",
+ "Right DAC", "DACR",
"HP", "HPCOM",
"Headphone Jack", "HP",
"MIC1", "Microphone Jack",
@@ -207,7 +205,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-a33-q8-tablet.dts b/arch/arm/dts/sun8i-a33-q8-tablet.dts
index b0bc2360f8..9c5750c256 100644
--- a/arch/arm/dts/sun8i-a33-q8-tablet.dts
+++ b/arch/arm/dts/sun8i-a33-q8-tablet.dts
@@ -48,3 +48,10 @@
model = "Q8 A33 Tablet";
compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
};
+
+&tcon0_out {
+ tcon0_out_lcd: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+};
diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
index 541acb4d2b..d54a067fc7 100644
--- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
+++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts
@@ -63,16 +63,10 @@
panel {
compatible = "netron-dy,e231732";
- #address-cells = <1>;
- #size-cells = <0>;
+ power-supply = <®_vcc3v3>;
- port@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- panel_input: endpoint@0 {
- reg = <0>;
+ port {
+ panel_input: endpoint {
remote-endpoint = <&tcon0_out_panel>;
};
};
@@ -117,21 +111,21 @@
vref-supply = <®_dcdc1>;
status = "okay";
- button@200 {
+ button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <191011>;
};
- button@400 {
+ button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
voltage = <391304>;
};
- button@600 {
+ button-600 {
label = "Home";
linux,code = <KEY_HOME>;
channel = <0>;
@@ -140,8 +134,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
@@ -161,29 +153,19 @@
&mmc2_8bit_pins {
/* Increase drive strength for DDR modes */
drive-strength = <40>;
- /* eMMC is missing pull-ups */
- bias-pull-up;
};
&ohci0 {
status = "okay";
};
-&pio {
- mmc0_cd_pin_sina33: mmc0_cd_pin@0 {
- pins = "PB4";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
&r_rsb {
status = "okay";
axp22x: pmic@3a3 {
compatible = "x-powers,axp223";
reg = <0x3a3>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <®_dcdc1>;
};
@@ -278,7 +260,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi
index 8d278ee001..b3d1bdfb51 100644
--- a/arch/arm/dts/sun8i-a33.dtsi
+++ b/arch/arm/dts/sun8i-a33.dtsi
@@ -46,7 +46,7 @@
#include <dt-bindings/thermal/thermal.h>
/ {
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -131,37 +131,40 @@
#cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <2>;
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <3>;
+ clocks = <&ccu CLK_CPUX>;
+ clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
};
- de: display-engine {
- compatible = "allwinner,sun8i-a33-display-engine";
- allwinner,pipelines = <&fe0>;
- status = "disabled";
- };
-
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&ths>;
};
- mali_opp_table: gpu-opp-table {
+ mali_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-144000000 {
@@ -177,21 +180,17 @@
};
};
- memory {
- reg = <0x40000000 0x80000000>;
- };
-
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,name = "sun8i-a33-audio";
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&link_codec>;
simple-audio-card,bitclock-master = <&link_codec>;
- simple-audio-card,mclk-fs = <512>;
+ simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
- "Left DAC", "AIF1 Slot 0 Left",
- "Right DAC", "AIF1 Slot 0 Right";
+ "Left DAC", "DACL",
+ "Right DAC", "DACR";
status = "disabled";
simple-audio-card,cpu {
@@ -199,54 +198,24 @@
};
link_codec: simple-audio-card,codec {
- sound-dai = <&codec>;
+ sound-dai = <&codec 0>;
};
};
- soc@1c00000 {
- tcon0: lcd-controller@1c0c000 {
- compatible = "allwinner,sun8i-a33-tcon";
- reg = <0x01c0c000 0x1000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_LCD>,
- <&ccu CLK_LCD_CH0>;
- clock-names = "ahb",
- "tcon-ch0";
- clock-output-names = "tcon-pixel-clock";
- resets = <&ccu RST_BUS_LCD>;
- reset-names = "lcd";
- status = "disabled";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- tcon0_in_drc0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&drc0_out_tcon0>;
- };
- };
-
- tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- tcon0_out_dsi: endpoint@1 {
- reg = <1>;
- remote-endpoint = <&dsi_in_tcon0>;
- };
- };
- };
+ soc {
+ video-codec@1c0e000 {
+ compatible = "allwinner,sun8i-a33-video-engine";
+ reg = <0x01c0e000 0x1000>;
+ clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+ <&ccu CLK_DRAM_VE>;
+ clock-names = "ahb", "mod", "ram";
+ resets = <&ccu RST_BUS_VE>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ allwinner,sram = <&ve_sram 1>;
};
crypto: crypto-engine@1c15000 {
- compatible = "allwinner,sun4i-a10-crypto";
+ compatible = "allwinner,sun8i-a33-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
@@ -269,7 +238,7 @@
};
codec: codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x400>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
@@ -296,19 +265,12 @@
phys = <&dphy>;
phy-names = "dphy";
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- dsi_in_tcon0: endpoint {
- remote-endpoint = <&tcon0_out_dsi>;
- };
+ port {
+ dsi_in_tcon0: endpoint {
+ remote-endpoint = <&tcon0_out_dsi>;
};
};
};
@@ -323,119 +285,10 @@
status = "disabled";
#phy-cells = <0>;
};
-
- fe0: display-frontend@1e00000 {
- compatible = "allwinner,sun8i-a33-display-frontend";
- reg = <0x01e00000 0x20000>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
- <&ccu CLK_DRAM_DE_FE>;
- clock-names = "ahb", "mod",
- "ram";
- resets = <&ccu RST_BUS_DE_FE>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- fe0_out_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_in_fe0>;
- };
- };
- };
- };
-
- be0: display-backend@1e60000 {
- compatible = "allwinner,sun8i-a33-display-backend";
- reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
- reg-names = "be", "sat";
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
- <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
- clock-names = "ahb", "mod",
- "ram", "sat";
- resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
- reset-names = "be", "sat";
- assigned-clocks = <&ccu CLK_DE_BE>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- be0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- be0_in_fe0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&fe0_out_be0>;
- };
- };
-
- be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- be0_out_drc0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&drc0_in_be0>;
- };
- };
- };
- };
-
- drc0: drc@1e70000 {
- compatible = "allwinner,sun8i-a33-drc";
- reg = <0x01e70000 0x10000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
- <&ccu CLK_DRAM_DRC>;
- clock-names = "ahb", "mod", "ram";
- resets = <&ccu RST_BUS_DRC>;
-
- assigned-clocks = <&ccu CLK_DRC>;
- assigned-clock-rates = <300000000>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- drc0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- drc0_in_be0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&be0_out_drc0>;
- };
- };
-
- drc0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
-
- drc0_out_tcon0: endpoint@0 {
- reg = <0>;
- remote-endpoint = <&tcon0_in_drc0>;
- };
- };
- };
- };
};
thermal-zones {
- cpu_thermal {
+ cpu-thermal {
/* milliseconds */
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -444,11 +297,17 @@
cooling-maps {
map0 {
trip = <&cpu_alert0>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu_alert1>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map2 {
@@ -502,10 +361,35 @@
};
};
+&be0 {
+ compatible = "allwinner,sun8i-a33-display-backend";
+ /* A33 has an extra "SAT" module packed inside the display backend */
+ reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>;
+ reg-names = "be", "sat";
+ clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
+ <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>;
+ clock-names = "ahb", "mod",
+ "ram", "sat";
+ resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>;
+ reset-names = "be", "sat";
+};
+
&ccu {
compatible = "allwinner,sun8i-a33-ccu";
};
+&de {
+ compatible = "allwinner,sun8i-a33-display-engine";
+};
+
+&drc0 {
+ compatible = "allwinner,sun8i-a33-drc";
+};
+
+&fe0 {
+ compatible = "allwinner,sun8i-a33-display-frontend";
+};
+
&mali {
operating-points-v2 = <&mali_opp_table>;
};
@@ -515,13 +399,27 @@
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- uart0_pins_b: uart0@1 {
+ uart0_pb_pins: uart0-pb-pins {
pins = "PB0", "PB1";
function = "uart0";
};
};
+&tcon0 {
+ compatible = "allwinner,sun8i-a33-tcon";
+};
+
+&tcon0_out {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_tcon0>;
+ };
+};
+
&usb_otg {
compatible = "allwinner,sun8i-a33-musb";
};
diff --git a/arch/arm/dts/sun8i-q8-common.dtsi b/arch/arm/dts/sun8i-q8-common.dtsi
index c676940a96..3d9a1524e1 100644
--- a/arch/arm/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/dts/sun8i-q8-common.dtsi
@@ -49,6 +49,19 @@
ethernet0 = &sdio_wifi;
};
+ panel: panel {
+ /* Tablet dts should provide panel compatible */
+ backlight = <&backlight>;
+ enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ power-supply = <®_dc1sw>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&tcon0_out_lcd>;
+ };
+ };
+ };
+
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
/*
@@ -64,13 +77,17 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <®_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@@ -82,18 +99,20 @@
};
};
-&mmc1_pins_a {
- bias-pull-up;
-};
-
&r_pio {
- wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 {
+ wifi_pwrseq_pin_q8: wifi-pwrseq-pins {
pins = "PL6", "PL7", "PL11";
function = "gpio_in";
bias-pull-up;
};
};
+&tcon0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_rgb666_pins>;
+ status = "okay";
+};
+
&usbphy {
usb1_vbus-supply = <®_dldo1>;
};
diff --git a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts
index 0dbdb29a8f..293016d081 100644
--- a/arch/arm/dts/sun8i-r16-bananapi-m2m.dts
+++ b/arch/arm/dts/sun8i-r16-bananapi-m2m.dts
@@ -64,17 +64,17 @@
leds {
compatible = "gpio-leds";
- blue {
+ led-0 {
label = "bpi-m2m:blue:usr";
gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;
};
- green {
+ led-1 {
label = "bpi-m2m:green:usr";
gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>;
};
- red {
+ led-2 {
label = "bpi-m2m:red:power";
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
default-state = "on";
@@ -91,6 +91,8 @@
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
};
};
@@ -103,13 +105,13 @@
};
&cpu0_opp_table {
- opp@1104000000 {
+ opp-1104000000 {
opp-hz = /bits/ 64 <1104000000>;
opp-microvolt = <1320000>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
- opp@1200000000 {
+ opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1320000>;
clock-latency-ns = <244144>; /* 8 32k periods */
@@ -124,30 +126,7 @@
status = "okay";
};
-/* This is the i2c bus exposed on the DSI connector for the touch panel */
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
- status = "disabled";
-};
-
-/* This is the i2c bus exposed on the GPIO header */
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
- status = "disabled";
-};
-
-/* This is the i2c bus exposed on the CSI connector to control the sensor */
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins_a>;
- status = "disabled";
-};
-
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
@@ -156,7 +135,7 @@
&mmc1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <®_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@@ -184,7 +163,7 @@
axp22x: pmic@3a3 {
compatible = "x-powers,axp223";
reg = <0x3a3>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <®_dcdc1>;
x-powers,drive-vbus-en;
@@ -292,14 +271,26 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>, <&uart1_pins_cts_rts_a>;
+ pinctrl-0 = <&uart1_pg_pins>, <&uart1_cts_rts_pg_pins>;
+ uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_dldo1>;
+ vddio-supply = <®_aldo3>;
+ device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ host-wakeup-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ shutdown-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ };
};
&usb_otg {
diff --git a/arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts b/arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts
new file mode 100644
index 0000000000..246dec5846
--- /dev/null
+++ b/arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/* Copyright (c) 2016 FUKAUMI Naoki <naobsd@gmail.com> */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ model = "Nintendo NES Classic Edition";
+ compatible = "nintendo,nes-classic", "allwinner,sun8i-r16",
+ "allwinner,sun8i-a33";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ /*
+ * UART0 is available on two ports: PB and PF, both are accessible.
+ * PF can also be used for the SD card so PB is preferred.
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pf_pins>;
+ status = "okay";
+};
+
+&nfc {
+ status = "okay";
+
+ /* 2Gb Macronix MX30LF2G18AC (3V) */
+ nand@0 {
+ reg = <0>;
+ allwinner,rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <16>;
+ nand-ecc-step-size = <1024>;
+ };
+};
+
+&usb_otg {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbphy {
+ /* VBUS is always on because it is wired to the power supply */
+ usb1_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts b/arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
new file mode 100644
index 0000000000..80761d7904
--- /dev/null
+++ b/arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0 OR X11
+/* Copyright (c) 2018 Miquèl RAYNAL <miquel.raynal@bootlin.com> */
+
+/dts-v1/;
+#include "sun8i-r16-nintendo-nes-classic.dts"
+
+/ {
+ model = "Nintendo SuperNES Classic Edition";
+ compatible = "nintendo,super-nes-classic", "nintendo,nes-classic",
+ "allwinner,sun8i-r16", "allwinner,sun8i-a33";
+};
diff --git a/arch/arm/dts/sun8i-r16-parrot.dts b/arch/arm/dts/sun8i-r16-parrot.dts
index 472c03b7ae..2be1b76fe2 100644
--- a/arch/arm/dts/sun8i-r16-parrot.dts
+++ b/arch/arm/dts/sun8i-r16-parrot.dts
@@ -63,17 +63,15 @@
leds {
compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins_parrot>;
- led1 {
+ led-1 {
label = "parrot:led1:usr";
- gpio = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+ gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
};
- led2 {
+ led-2 {
label = "parrot:led2:usr";
- gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+ gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
};
};
@@ -97,8 +95,6 @@
};
&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
status = "okay";
/*
@@ -111,14 +107,14 @@
vref-supply = <®_aldo3>;
status = "okay";
- button@0 {
+ button-190 {
label = "V+";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <190000>;
};
- button@1 {
+ button-390 {
label = "V-";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@@ -128,8 +124,6 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_parrot>;
vmmc-supply = <®_dcdc1>;
cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
bus-width = <4>;
@@ -138,7 +132,7 @@
&mmc1 {
pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_parrot>;
+ pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <®_aldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
@@ -158,51 +152,19 @@
&mmc2_8bit_pins {
drive-strength = <40>;
- bias-pull-up;
};
&ohci0 {
status = "okay";
};
-&pio {
- mmc0_cd_pin_parrot: mmc0_cd_pin@0 {
- pins = "PD14";
- function = "gpio_in";
- bias-pull-up;
- };
-
- led_pins_parrot: led_pins@0 {
- pins = "PE16", "PE17";
- function = "gpio_out";
- };
-
- usb0_id_det: usb0_id_detect_pin@0 {
- pins = "PD10";
- function = "gpio_in";
- bias-pull-up;
- };
-
- usb1_vbus_pin_parrot: usb1_vbus_pin@0 {
- pins = "PD12";
- function = "gpio_out";
- };
-};
-
-&r_pio {
- wifi_reset_pin_parrot: wifi_reset_pin@0 {
- pins = "PL6";
- function = "gpio_out";
- };
-};
-
&r_rsb {
status = "okay";
axp22x: pmic@3a3 {
compatible = "x-powers,axp223";
reg = <0x3a3>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
drivevbus-supply = <®_vcc5v0>;
x-powers,drive-vbus-en;
@@ -319,8 +281,6 @@
};
®_usb1_vbus {
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_vbus_pin_parrot>;
gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */
status = "okay";
};
@@ -331,7 +291,7 @@
&uart0 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_b>;
+ pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
@@ -346,10 +306,8 @@
&usbphy {
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_det>;
usb0_vbus-supply = <®_drivevbus>;
- usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */
+ usb0_id_det-gpios = <&pio 3 10 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PD10 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb1_vbus-supply = <®_usb1_vbus>;
};
diff --git a/arch/arm/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/dts/sun8i-reference-design-tablet.dtsi
index 880096c7e2..797d61cff1 100644
--- a/arch/arm/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/dts/sun8i-reference-design-tablet.dtsi
@@ -54,6 +54,7 @@
brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
default-brightness-level = <8>;
enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ power-supply = <®_dc1sw>;
};
chosen {
@@ -69,11 +70,10 @@
*/
clock-frequency = <400000>;
- touchscreen: touchscreen@0 {
+ touchscreen: touchscreen@40 {
+ reg = <0x40>;
interrupt-parent = <&pio>;
interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
- pinctrl-names = "default";
- pinctrl-0 = <&ts_power_pin>;
power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
/* Tablet dts must provide reg and compatible */
status = "disabled";
@@ -81,40 +81,19 @@
};
&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
vmmc-supply = <®_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 1 4 GPIO_ACTIVE_LOW>; /* PB4 */
status = "okay";
};
-&pio {
- mmc0_cd_pin: mmc0_cd_pin@0 {
- pins = "PB4";
- function = "gpio_in";
- bias-pull-up;
- };
-
- ts_power_pin: ts_power_pin@0 {
- pins = "PH1";
- function = "gpio_out";
- };
-
- usb0_id_detect_pin: usb0_id_detect_pin@0 {
- pins = "PH8";
- function = "gpio_in";
- bias-pull-up;
- };
-};
-
&r_rsb {
status = "okay";
axp22x: pmic@3a3 {
compatible = "x-powers,axp223";
reg = <0x3a3>;
- interrupt-parent = <&nmi_intc>;
+ interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <®_dcdc1>;
drivevbus-supply = <®_vcc5v0>;
@@ -238,9 +217,7 @@
};
&usbphy {
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_id_detect_pin>;
- usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+ usb0_id_det-gpios = <&pio 7 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH8 */
usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_drivevbus>;
status = "okay";
diff --git a/arch/arm/dts/sunxi-common-regulators.dtsi b/arch/arm/dts/sunxi-common-regulators.dtsi
index f1953b0c50..d8e5826fb3 100644
--- a/arch/arm/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/dts/sunxi-common-regulators.dtsi
@@ -43,43 +43,10 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-
-&pio {
- ahci_pwr_pin_a: ahci_pwr_pin@0 {
- allwinner,pins = "PB8";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb0_vbus_pin_a: usb0_vbus_pin@0 {
- allwinner,pins = "PB9";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb1_vbus_pin_a: usb1_vbus_pin@0 {
- allwinner,pins = "PH6";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-
- usb2_vbus_pin_a: usb2_vbus_pin@0 {
- allwinner,pins = "PH3";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
/ {
reg_ahci_5v: ahci-5v {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&ahci_pwr_pin_a>;
regulator-name = "ahci-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -91,8 +58,6 @@
reg_usb0_vbus: usb0-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_vbus_pin_a>;
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -103,8 +68,6 @@
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&usb1_vbus_pin_a>;
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -116,8 +79,6 @@
reg_usb2_vbus: usb2-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&usb2_vbus_pin_a>;
regulator-name = "usb2-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/dts/sunxi-reference-design-tablet.dtsi b/arch/arm/dts/sunxi-reference-design-tablet.dtsi
index b8241462fc..117198c52e 100644
--- a/arch/arm/dts/sunxi-reference-design-tablet.dtsi
+++ b/arch/arm/dts/sunxi-reference-design-tablet.dtsi
@@ -42,18 +42,17 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
#include "sunxi-common-regulators.dtsi"
&i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins_a>;
+ pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
@@ -61,14 +60,14 @@
vref-supply = <®_vcc3v0>;
status = "okay";
- button@200 {
+ button-200 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
channel = <0>;
voltage = <200000>;
};
- button@400 {
+ button-400 {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
channel = <0>;
@@ -78,6 +77,6 @@
&pwm {
pinctrl-names = "default";
- pinctrl-0 = <&pwm0_pins>;
+ pinctrl-0 = <&pwm0_pin>;
status = "okay";
};
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1f43b25324..5fc9b29a3e 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -911,7 +911,7 @@ config VIDEO_LCD_PANEL_I2C
config VIDEO_LCD_PANEL_I2C_NAME
string "LCD panel i2c interface node name"
depends on VIDEO_LCD_PANEL_I2C
- default "i2c@0"
+ default "i2c"
---help---
Set the device tree node name for the LCD i2c interface.
diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig
index 72e9725c9a..b66023418a 100644
--- a/configs/Nintendo_NES_Classic_Edition_defconfig
+++ b/configs/Nintendo_NES_Classic_Edition_defconfig
@@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic-edition"
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-r16-nintendo-nes-classic"
CONFIG_SPL=y
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 06/12] ARM: dts: sun9i: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (4 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 05/12] ARM: dts: sunxi: A13/A31/A23/A33: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-20 13:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 07/12] ARM: dts: sun8i: A83T: " Samuel Holland
` (7 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the A80 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/sun9i-a80-cubieboard4.dts | 67 ++++++---
arch/arm/dts/sun9i-a80-optimus.dts | 50 ++++++-
arch/arm/dts/sun9i-a80.dtsi | 195 +++++++++++++++----------
3 files changed, 212 insertions(+), 100 deletions(-)
diff --git a/arch/arm/dts/sun9i-a80-cubieboard4.dts b/arch/arm/dts/sun9i-a80-cubieboard4.dts
index 85da85faf8..c8ca8cb7f5 100644
--- a/arch/arm/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/dts/sun9i-a80-cubieboard4.dts
@@ -63,12 +63,12 @@
leds {
compatible = "gpio-leds";
- green {
+ led-0 {
label = "cubieboard4:green:usr";
gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */
};
- red {
+ led-1 {
label = "cubieboard4:red:usr";
gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
};
@@ -87,33 +87,25 @@
};
vga-dac {
- compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
+ compatible = "corpro,gm7123", "adi,adv7123";
vdd-supply = <®_dcdc1>;
- #address-cells = <1>;
- #size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- vga_dac_in: endpoint@0 {
- reg = <0>;
+ vga_dac_in: endpoint {
remote-endpoint = <&tcon0_out_vga>;
};
};
port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- vga_dac_out: endpoint@0 {
- reg = <0>;
+ vga_dac_out: endpoint {
remote-endpoint = <&vga_con_in>;
};
};
@@ -133,12 +125,27 @@
status = "okay";
};
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <®_cldo1>;
+ status = "okay";
+};
+
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
status = "okay";
};
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -183,10 +190,26 @@
clocks = <&ac100_rtc 0>;
};
+&pio {
+ vcc-pa-supply = <®_ldo_io1>;
+ vcc-pb-supply = <®_aldo2>;
+ vcc-pc-supply = <®_dcdc1>;
+ vcc-pd-supply = <®_dc1sw>;
+ vcc-pe-supply = <®_eldo2>;
+ vcc-pf-supply = <®_dcdc1>;
+ vcc-pg-supply = <®_ldo_io0>;
+ vcc-ph-supply = <®_dcdc1>;
+};
+
&r_ir {
status = "okay";
};
+&r_pio {
+ vcc-pl-supply = <®_dldo2>;
+ vcc-pm-supply = <®_eldo3>;
+};
+
&r_rsb {
status = "okay";
@@ -217,6 +240,10 @@
/* unused */
};
+ reg_dc1sw: dc1sw {
+ regulator-name = "vcc-pd";
+ };
+
reg_dc5ldo: dc5ldo {
regulator-always-on;
regulator-min-microvolt = <800000>;
@@ -271,7 +298,6 @@
};
reg_dldo2: dldo2 {
- regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pl";
@@ -290,14 +316,12 @@
};
reg_eldo3: eldo3 {
- regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pm-codec-io1";
};
reg_ldo_io0: ldo_io0 {
- regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pg";
@@ -385,6 +409,14 @@
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ /*
+ * The PHY requires 20ms after all voltages
+ * are applied until core logic is ready and
+ * 30ms after the reset pin is de-asserted.
+ * Set a 100ms delay to account for PMIC
+ * ramp time and board traces.
+ */
+ regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-gmac-phy";
};
@@ -464,8 +496,7 @@
};
&tcon0_out {
- tcon0_out_vga: endpoint@0 {
- reg = <0>;
+ tcon0_out_vga: endpoint {
remote-endpoint = <&vga_dac_in>;
};
};
diff --git a/arch/arm/dts/sun9i-a80-optimus.dts b/arch/arm/dts/sun9i-a80-optimus.dts
index 58a199b0e4..5c3580d712 100644
--- a/arch/arm/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/dts/sun9i-a80-optimus.dts
@@ -82,7 +82,7 @@
reg_usb1_vbus: usb1-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
+ regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
@@ -91,7 +91,7 @@
reg_usb3_vbus: usb3-vbus {
compatible = "regulator-fixed";
- pinctrl-names = "default";
+ regulator-name = "usb3-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
@@ -120,6 +120,21 @@
status = "okay";
};
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <®_cldo1>;
+ status = "okay";
+};
+
+&mdio {
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -172,10 +187,26 @@
clocks = <&ac100_rtc 0>;
};
+&pio {
+ vcc-pa-supply = <®_ldo_io1>;
+ vcc-pb-supply = <®_aldo2>;
+ vcc-pc-supply = <®_dcdc1>;
+ vcc-pd-supply = <®_dcdc1>;
+ vcc-pe-supply = <®_eldo2>;
+ vcc-pf-supply = <®_dcdc1>;
+ vcc-pg-supply = <®_ldo_io0>;
+ vcc-ph-supply = <®_dcdc1>;
+};
+
&r_ir {
status = "okay";
};
+&r_pio {
+ vcc-pl-supply = <®_dldo2>;
+ vcc-pm-supply = <®_eldo3>;
+};
+
&r_rsb {
status = "okay";
@@ -213,6 +244,10 @@
regulator-name = "vdd-cpus-09-usbh";
};
+ dc1sw {
+ /* unused */
+ };
+
reg_dcdc1: dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
@@ -260,7 +295,6 @@
};
reg_dldo2: dldo2 {
- regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pl";
@@ -279,14 +313,12 @@
};
reg_eldo3: eldo3 {
- regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pm-codec-io1";
};
reg_ldo_io0: ldo_io0 {
- regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-pg";
@@ -374,6 +406,14 @@
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ /*
+ * The PHY requires 20ms after all voltages
+ * are applied until core logic is ready and
+ * 30ms after the reset pin is de-asserted.
+ * Set a 100ms delay to account for PMIC
+ * ramp time and board traces.
+ */
+ regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-gmac-phy";
};
diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi
index 25591d6883..ce4fa6706d 100644
--- a/arch/arm/dts/sun9i-a80.dtsi
+++ b/arch/arm/dts/sun9i-a80.dtsi
@@ -56,6 +56,10 @@
#size-cells = <2>;
interrupt-parent = <&gic>;
+ aliases {
+ ethernet0 = &gmac;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -183,6 +187,37 @@
clock-output-names = "osc32k";
};
+ /*
+ * The following two are dummy clocks, placeholders
+ * used in the gmac_tx clock. The gmac driver will
+ * choose one parent depending on the PHY interface
+ * mode, using clk_set_rate auto-reparenting.
+ *
+ * The actual TX clock rate is not controlled by the
+ * gmac_tx clock.
+ */
+ mii_phy_tx_clk: mii_phy_tx_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: gmac_int_tx_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk@800030 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x00800030 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
+
cpus_clk: clk@8001410 {
compatible = "allwinner,sun9i-a80-cpus-clk";
reg = <0x08001410 0x4>;
@@ -254,7 +289,7 @@
status = "disabled";
};
- soc {
+ soc@20000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -283,6 +318,27 @@
};
};
+ gmac: ethernet@830000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x00830000 0x1054>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ resets = <&ccu RST_BUS_GMAC>;
+ reset-names = "stmmaceth";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
ehci0: usb@a00000 {
compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
reg = <0x00a00000 0x100>;
@@ -331,16 +387,16 @@
usbphy2: phy@a01800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a01800 0x4>;
- clocks = <&usb_clocks CLK_USB1_HSIC>,
+ clocks = <&usb_clocks CLK_USB1_PHY>,
<&usb_clocks CLK_USB_HSIC>,
- <&usb_clocks CLK_USB1_PHY>;
- clock-names = "hsic_480M",
+ <&usb_clocks CLK_USB1_HSIC>;
+ clock-names = "phy",
"hsic_12M",
- "phy";
- resets = <&usb_clocks RST_USB1_HSIC>,
- <&usb_clocks RST_USB1_PHY>;
- reset-names = "hsic",
- "phy";
+ "hsic_480M";
+ resets = <&usb_clocks RST_USB1_PHY>,
+ <&usb_clocks RST_USB1_HSIC>;
+ reset-names = "phy",
+ "hsic";
status = "disabled";
#phy-cells = <0>;
/* usb1 is always used with HSIC */
@@ -373,16 +429,16 @@
usbphy3: phy@a02800 {
compatible = "allwinner,sun9i-a80-usb-phy";
reg = <0x00a02800 0x4>;
- clocks = <&usb_clocks CLK_USB2_HSIC>,
+ clocks = <&usb_clocks CLK_USB2_PHY>,
<&usb_clocks CLK_USB_HSIC>,
- <&usb_clocks CLK_USB2_PHY>;
- clock-names = "hsic_480M",
+ <&usb_clocks CLK_USB2_HSIC>;
+ clock-names = "phy",
"hsic_12M",
- "phy";
- resets = <&usb_clocks RST_USB2_HSIC>,
- <&usb_clocks RST_USB2_PHY>;
- reset-names = "hsic",
- "phy";
+ "hsic_480M";
+ resets = <&usb_clocks RST_USB2_PHY>,
+ <&usb_clocks RST_USB2_HSIC>;
+ reset-names = "phy",
+ "hsic";
status = "disabled";
#phy-cells = <0>;
};
@@ -401,6 +457,15 @@
reg = <0x01700000 0x100>;
};
+ crypto: crypto@1c02000 {
+ compatible = "allwinner,sun9i-a80-crypto";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_SS>;
+ clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
+ clock-names = "bus", "mod";
+ };
+
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun9i-a80-mmc";
reg = <0x01c0f000 0x1000>;
@@ -465,9 +530,7 @@
compatible = "allwinner,sun9i-a80-mmc-config-clk";
reg = <0x01c13000 0x10>;
clocks = <&ccu CLK_BUS_MMC>;
- clock-names = "ahb";
resets = <&ccu RST_BUS_MMC>;
- reset-names = "ahb";
#clock-cells = <1>;
#reset-cells = <1>;
clock-output-names = "mmc0_config", "mmc1_config",
@@ -475,7 +538,7 @@
};
gic: interrupt-controller@1c41000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
reg = <0x01c41000 0x1000>,
<0x01c42000 0x2000>,
<0x01c44000 0x2000>,
@@ -544,12 +607,9 @@
#size-cells = <0>;
fe0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- fe0_out_deu0: endpoint@0 {
- reg = <0>;
+ fe0_out_deu0: endpoint {
remote-endpoint = <&deu0_in_fe0>;
};
};
@@ -571,12 +631,9 @@
#size-cells = <0>;
fe1_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- fe1_out_deu1: endpoint@0 {
- reg = <0>;
+ fe1_out_deu1: endpoint {
remote-endpoint = <&deu1_in_fe1>;
};
};
@@ -614,12 +671,9 @@
};
be0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- be0_out_drc0: endpoint@0 {
- reg = <0>;
+ be0_out_drc0: endpoint {
remote-endpoint = <&drc0_in_be0>;
};
};
@@ -657,12 +711,9 @@
};
be1_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- be1_out_drc1: endpoint@0 {
- reg = <0>;
+ be1_out_drc1: endpoint {
remote-endpoint = <&drc1_in_be1>;
};
};
@@ -686,12 +737,9 @@
#size-cells = <0>;
deu0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- deu0_in_fe0: endpoint@0 {
- reg = <0>;
+ deu0_in_fe0: endpoint {
remote-endpoint = <&fe0_out_deu0>;
};
};
@@ -731,12 +779,9 @@
#size-cells = <0>;
deu1_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- deu1_in_fe1: endpoint@0 {
- reg = <0>;
+ deu1_in_fe1: endpoint {
remote-endpoint = <&fe1_out_deu1>;
};
};
@@ -776,23 +821,17 @@
#size-cells = <0>;
drc0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- drc0_in_be0: endpoint@0 {
- reg = <0>;
+ drc0_in_be0: endpoint {
remote-endpoint = <&be0_out_drc0>;
};
};
drc0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- drc0_out_tcon0: endpoint@0 {
- reg = <0>;
+ drc0_out_tcon0: endpoint {
remote-endpoint = <&tcon0_in_drc0>;
};
};
@@ -816,23 +855,17 @@
#size-cells = <0>;
drc1_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- drc1_in_be1: endpoint@0 {
- reg = <0>;
+ drc1_in_be1: endpoint {
remote-endpoint = <&be1_out_drc1>;
};
};
drc1_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
- drc1_out_tcon1: endpoint@0 {
- reg = <0>;
+ drc1_out_tcon1: endpoint {
remote-endpoint = <&tcon1_in_drc1>;
};
};
@@ -845,28 +878,28 @@
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
clock-names = "ahb", "tcon-ch0";
- resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
- reset-names = "lcd", "edp";
+ resets = <&ccu RST_BUS_LCD0>,
+ <&ccu RST_BUS_EDP>,
+ <&ccu RST_BUS_LVDS>;
+ reset-names = "lcd",
+ "edp",
+ "lvds";
clock-output-names = "tcon0-pixel-clock";
+ #clock-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
tcon0_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- tcon0_in_drc0: endpoint@0 {
- reg = <0>;
+ tcon0_in_drc0: endpoint {
remote-endpoint = <&drc0_out_tcon0>;
};
};
tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
};
};
@@ -886,19 +919,14 @@
#size-cells = <0>;
tcon1_in: port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <0>;
- tcon1_in_drc1: endpoint@0 {
- reg = <0>;
+ tcon1_in_drc1: endpoint {
remote-endpoint = <&drc1_out_tcon1>;
};
};
tcon1_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
};
};
@@ -930,6 +958,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x06000ca0 0x20>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
pio: pinctrl@6000800 {
@@ -945,9 +974,20 @@
gpio-controller;
interrupt-controller;
#interrupt-cells = <3>;
- #size-cells = <0>;
#gpio-cells = <3>;
+ gmac_rgmii_pins: gmac-rgmii-pins {
+ pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
+ "PA7", "PA8", "PA9", "PA10", "PA12",
+ "PA13", "PA15", "PA16", "PA17";
+ function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ drive-strength = <40>;
+ };
+
i2c3_pins: i2c3-pins {
pins = "PG10", "PG11";
function = "i2c3";
@@ -1126,6 +1166,7 @@
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x08001000 0x20>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
prcm@8001400 {
@@ -1148,7 +1189,7 @@
};
r_ir: ir@8002000 {
- compatible = "allwinner,sun5i-a13-ir";
+ compatible = "allwinner,sun6i-a31-ir";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&r_ir_pins>;
@@ -1196,7 +1237,7 @@
};
};
- r_rsb: i2c@8003400 {
+ r_rsb: rsb@8003400 {
compatible = "allwinner,sun8i-a23-rsb";
reg = <0x08003400 0x400>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 07/12] ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (5 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 06/12] ARM: dts: sun9i: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-20 13:48 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 08/12] ARM: dts: sunxi: H2+/H3/H5: " Samuel Holland
` (6 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the A83T SoC and all existing boards
from the Linux v5.18-rc1 tag.
To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
As with the other SoCs, updates of note include adding detection GPIO
properties in the USB PHY nodes.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/axp81x.dtsi | 15 +-
.../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 +
arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 55 +++-
arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 77 ++++-
arch/arm/dts/sun8i-a83t-tbs-a711.dts | 101 +++++-
arch/arm/dts/sun8i-a83t.dtsi | 311 ++++++++++++++++--
6 files changed, 515 insertions(+), 56 deletions(-)
diff --git a/arch/arm/dts/axp81x.dtsi b/arch/arm/dts/axp81x.dtsi
index 043c717dce..b93387b0c1 100644
--- a/arch/arm/dts/axp81x.dtsi
+++ b/arch/arm/dts/axp81x.dtsi
@@ -48,6 +48,11 @@
interrupt-controller;
#interrupt-cells = <1>;
+ ac_power_supply: ac-power {
+ compatible = "x-powers,axp813-ac-power-supply";
+ status = "disabled";
+ };
+
axp_adc: adc {
compatible = "x-powers,axp813-adc";
#io-channel-cells = <1>;
@@ -58,18 +63,18 @@
gpio-controller;
#gpio-cells = <2>;
- gpio0_ldo: gpio0-ldo {
+ gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
- gpio1_ldo: gpio1-ldo {
+ gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
};
- battery_power_supply: battery-power-supply {
+ battery_power_supply: battery-power {
compatible = "x-powers,axp813-battery-power-supply";
status = "disabled";
};
@@ -166,4 +171,8 @@
status = "disabled";
};
};
+
+ usb_power_supply: usb-power {
+ compatible = "x-powers,axp813-usb-power-supply";
+ };
};
diff --git a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
index 36ecebaff3..9c006fc188 100644
--- a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
+++ b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
@@ -79,6 +79,14 @@
};
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu100 {
+ cpu-supply = <®_dcdc3>;
+};
+
&ehci0 {
status = "okay";
};
@@ -146,6 +154,10 @@
#include "axp81x.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
®_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
index 2beafe3a31..b60016a442 100644
--- a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
@@ -74,12 +74,12 @@
leds {
compatible = "gpio-leds";
- blue {
+ led-0 {
label = "bananapi-m3:blue:usr";
gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
};
- green {
+ led-1 {
label = "bananapi-m3:green:usr";
gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
};
@@ -107,6 +107,14 @@
};
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu100 {
+ cpu-supply = <®_dcdc3>;
+};
+
&de {
status = "okay";
};
@@ -183,6 +191,11 @@
status = "okay";
};
+&r_cir {
+ clock-frequency = <3000000>;
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -224,6 +237,14 @@
#include "axp81x.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
®_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
@@ -301,8 +322,8 @@
®_dldo3 {
regulator-always-on;
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pd";
};
@@ -350,11 +371,37 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&ac100_rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_dldo1>;
+ vddio-supply = <®_dldo1>;
+ device-wakeup-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+};
+
&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
status = "okay";
};
&usbphy {
+ usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_drivevbus>;
usb1_vbus-supply = <®_usb1_vbus>;
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
index ecd9ff38a8..e26af7cf10 100644
--- a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
@@ -60,25 +60,36 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
- blue {
+ led-0 {
label = "cubietruck-plus:blue:usr";
gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
};
- orange {
+ led-1 {
label = "cubietruck-plus:orange:usr";
gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */
};
- white {
+ led-2 {
label = "cubietruck-plus:white:usr";
gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */
};
- green {
+ led-3 {
label = "cubietruck-plus:green:usr";
gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */
};
@@ -90,7 +101,7 @@
initial-mode = <1>; /* initialize in HUB mode */
disabled-ports = <1>;
intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
- reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
refclk-frequency = <19200000>;
};
@@ -145,6 +156,18 @@
};
};
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&cpu100 {
+ cpu-supply = <®_dcdc3>;
+};
+
+&de {
+ status = "okay";
+};
+
&ehci0 {
/* GL830 USB-to-SATA bridge here */
status = "okay";
@@ -164,6 +187,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -239,6 +272,14 @@
#include "axp81x.dtsi"
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
®_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
@@ -386,11 +427,37 @@
status = "okay";
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4330-bt";
+ clocks = <&ac100_rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_dcdc1>;
+ vddio-supply = <®_sw>;
+ device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ host-wakeup-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ };
+};
+
&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
status = "okay";
};
&usbphy {
+ usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_drivevbus>;
usb1_vbus-supply = <®_usb1_vbus>;
usb2_vbus-supply = <®_usb2_vbus>;
status = "okay";
diff --git a/arch/arm/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/dts/sun8i-a83t-tbs-a711.dts
index 1537ce148c..13ae10f60d 100644
--- a/arch/arm/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/dts/sun8i-a83t-tbs-a711.dts
@@ -46,6 +46,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/input/input.h>
/ {
model = "TBS A711 Tablet";
@@ -64,7 +65,7 @@
compatible = "pwm-backlight";
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;
-
+ power-supply = <®_sw>;
brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
default-brightness-level = <9>;
};
@@ -98,6 +99,13 @@
};
};
+ reg_gps: reg-gps {
+ compatible = "regulator-fixed";
+ regulator-name = "gps";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
reg_vbat: reg-vbat {
compatible = "regulator-fixed";
regulator-name = "vbat";
@@ -156,10 +164,39 @@
status = "okay";
};
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5206";
+ reg = <0x38>;
+ interrupt-parent = <&r_pio>;
+ interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */
+ reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */
+ vcc-supply = <®_ldo_io0>;
+ touchscreen-size-x = <1024>;
+ touchscreen-size-y = <600>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+
+ accelerometer@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+ };
+};
+
&mmc0 {
vmmc-supply = <®_dcdc1>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
+ bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
@@ -171,6 +208,7 @@
vqmmc-supply = <®_dldo1>;
non-removable;
wakeup-source;
+ keep-power-in-suspend;
status = "okay";
brcmf: wifi@1 {
@@ -199,6 +237,25 @@
status = "okay";
};
+&r_lradc {
+ vref-supply = <®_aldo2>;
+ status = "okay";
+
+ button-210 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <210000>;
+ };
+
+ button-410 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <410000>;
+ };
+};
+
&r_rsb {
status = "okay";
@@ -317,8 +374,8 @@
};
®_dldo3 {
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-name = "vdd-csi";
};
@@ -390,8 +447,7 @@
};
&tcon0_out {
- tcon0_out_lcd: endpoint@0 {
- reg = <0>;
+ tcon0_out_lcd: endpoint {
remote-endpoint = <&panel_input>;
};
};
@@ -406,18 +462,45 @@
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm20702a1";
+ clocks = <&ac100_rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_vbat>;
+ vddio-supply = <®_dldo1>;
+ device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
+ shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
+ max-speed = <1500000>;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pb_pins>;
+ status = "okay";
+
+ gnss {
+ compatible = "u-blox,neo-6m";
+
+ v-bckp-supply = <®_rtc_ldo>;
+ vcc-supply = <®_gps>;
+ current-speed = <9600>;
+ };
};
&usb_otg {
- dr_mode = "otg";
status = "okay";
};
&usbphy {
- usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
+ usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
usb0_vbus-supply = <®_drivevbus>;
- usb1_vbus_supply = <®_vmain>;
- usb2_vbus_supply = <®_vmain>;
+ usb1_vbus-supply = <®_vmain>;
+ usb2_vbus-supply = <®_vmain>;
status = "okay";
};
diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi
index 2be23d6009..9c07660080 100644
--- a/arch/arm/dts/sun8i-a83t.dtsi
+++ b/arch/arm/dts/sun8i-a83t.dtsi
@@ -50,6 +50,7 @@
#include <dt-bindings/reset/sun8i-a83t-ccu.h>
#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -61,79 +62,91 @@
#size-cells = <0>;
cpu0: cpu@0 {
- clocks = <&ccu CLK_C0CPUX>;
- clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <1>;
+ #cooling-cells = <2>;
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <2>;
+ #cooling-cells = <2>;
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C0CPUX>;
operating-points-v2 = <&cpu0_opp_table>;
cci-control-port = <&cci_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <3>;
+ #cooling-cells = <2>;
};
cpu100: cpu@100 {
- clocks = <&ccu CLK_C1CPUX>;
- clock-names = "cpu";
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
+ #cooling-cells = <2>;
};
- cpu@101 {
+ cpu101: cpu@101 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x101>;
+ #cooling-cells = <2>;
};
- cpu@102 {
+ cpu102: cpu@102 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x102>;
+ #cooling-cells = <2>;
};
- cpu@103 {
+ cpu103: cpu@103 {
compatible = "arm,cortex-a7";
device_type = "cpu";
+ clocks = <&ccu CLK_C1CPUX>;
operating-points-v2 = <&cpu1_opp_table>;
cci-control-port = <&cci_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x103>;
+ #cooling-cells = <2>;
};
};
@@ -187,12 +200,7 @@
status = "disabled";
};
- memory {
- reg = <0x40000000 0x80000000>;
- device_type = "memory";
- };
-
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-cluster0 {
compatible = "operating-points-v2";
opp-shared;
@@ -245,7 +253,7 @@
};
};
- cpu1_opp_table: opp_table1 {
+ cpu1_opp_table: opp-table-cluster1 {
compatible = "operating-points-v2";
opp-shared;
@@ -306,16 +314,27 @@
display_clocks: clock@1000000 {
compatible = "allwinner,sun8i-a83t-de2-clk";
- reg = <0x01000000 0x100000>;
- clocks = <&ccu CLK_PLL_DE>,
- <&ccu CLK_BUS_DE>;
- clock-names = "mod",
- "bus";
+ reg = <0x01000000 0x10000>;
+ clocks = <&ccu CLK_BUS_DE>,
+ <&ccu CLK_PLL_DE>;
+ clock-names = "bus",
+ "mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
};
+ rotate: rotate@1020000 {
+ compatible = "allwinner,sun8i-a83t-de2-rotate";
+ reg = <0x1020000 0x10000>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&display_clocks CLK_BUS_ROT>,
+ <&display_clocks CLK_ROT>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_ROT>;
+ };
+
mixer0: mixer@1100000 {
compatible = "allwinner,sun8i-a83t-de2-mixer-0";
reg = <0x01100000 0x100000>;
@@ -338,6 +357,11 @@
reg = <0>;
remote-endpoint = <&tcon0_in_mixer0>;
};
+
+ mixer0_out_tcon1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tcon1_in_mixer0>;
+ };
};
};
};
@@ -356,9 +380,17 @@
#size-cells = <0>;
mixer1_out: port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
- mixer1_out_tcon1: endpoint {
+ mixer1_out_tcon0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tcon0_in_mixer1>;
+ };
+
+ mixer1_out_tcon1: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&tcon1_in_mixer1>;
};
};
@@ -425,6 +457,7 @@
clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
clock-names = "ahb", "tcon-ch0";
clock-output-names = "tcon-pixel-clock";
+ #clock-cells = <0>;
resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
reset-names = "lcd", "lvds";
@@ -441,11 +474,14 @@
reg = <0>;
remote-endpoint = <&mixer0_out_tcon0>;
};
+
+ tcon0_in_mixer1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mixer1_out_tcon0>;
+ };
};
tcon0_out: port@1 {
- #address-cells = <1>;
- #size-cells = <0>;
reg = <1>;
};
};
@@ -465,9 +501,17 @@
#size-cells = <0>;
tcon1_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
- tcon1_in_mixer1: endpoint {
+ tcon1_in_mixer0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mixer0_out_tcon1>;
+ };
+
+ tcon1_in_mixer1: endpoint@1 {
+ reg = <1>;
remote-endpoint = <&mixer1_out_tcon1>;
};
};
@@ -549,6 +593,31 @@
sid: eeprom@1c14000 {
compatible = "allwinner,sun8i-a83t-sid";
reg = <0x1c14000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ths_calibration: thermal-sensor-calibration@34 {
+ reg = <0x34 8>;
+ };
+ };
+
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun8i-a83t-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&ccu RST_BUS_SS>;
+ clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
+ clock-names = "bus", "mod";
+ };
+
+ msgbox: mailbox@1c17000 {
+ compatible = "allwinner,sun8i-a83t-msgbox",
+ "allwinner,sun6i-a31-msgbox";
+ reg = <0x01c17000 0x1000>;
+ clocks = <&ccu CLK_BUS_MSGBOX>;
+ resets = <&ccu RST_BUS_MSGBOX>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
};
usb_otg: usb@1c19000 {
@@ -562,6 +631,7 @@
phys = <&usbphy 0>;
phy-names = "usb";
extcon = <&usbphy 0>;
+ dr_mode = "otg";
status = "disabled";
};
@@ -649,6 +719,20 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ /omit-if-no-ref/
+ csi_8bit_parallel_pins: csi-8bit-parallel-pins {
+ pins = "PE0", "PE2", "PE3", "PE6", "PE7",
+ "PE8", "PE9", "PE10", "PE11",
+ "PE12", "PE13";
+ function = "csi";
+ };
+
+ /omit-if-no-ref/
+ csi_mclk_pin: csi-mclk-pin {
+ pins = "PE1";
+ function = "csi";
+ };
+
emac_rgmii_pins: emac-rgmii-pins {
pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
"PD11", "PD12", "PD13", "PD14", "PD18",
@@ -676,6 +760,12 @@
function = "i2c1";
};
+ /omit-if-no-ref/
+ i2c2_pe_pins: i2c2-pe-pins {
+ pins = "PE14", "PE15";
+ function = "i2c2";
+ };
+
i2c2_ph_pins: i2c2-ph-pins {
pins = "PH4", "PH5";
function = "i2c2";
@@ -747,10 +837,16 @@
pins = "PG8", "PG9";
function = "uart1";
};
+
+ /omit-if-no-ref/
+ uart2_pb_pins: uart2-pb-pins {
+ pins = "PB0", "PB1";
+ function = "uart2";
+ };
};
timer@1c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
+ compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -852,6 +948,39 @@
status = "disabled";
};
+ uart2: serial@1c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART2>;
+ resets = <&ccu RST_BUS_UART2>;
+ status = "disabled";
+ };
+
+ uart3: serial@1c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART3>;
+ resets = <&ccu RST_BUS_UART3>;
+ status = "disabled";
+ };
+
+ uart4: serial@1c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&ccu CLK_BUS_UART4>;
+ resets = <&ccu RST_BUS_UART4>;
+ status = "disabled";
+ };
+
i2c0: i2c@1c2ac00 {
compatible = "allwinner,sun8i-a83t-i2c",
"allwinner,sun6i-a31-i2c";
@@ -898,12 +1027,10 @@
reg = <0x01c30000 0x104>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
- resets = <&ccu 13>;
- reset-names = "stmmaceth";
- clocks = <&ccu 27>;
+ clocks = <&ccu CLK_BUS_EMAC>;
clock-names = "stmmaceth";
- #address-cells = <1>;
- #size-cells = <0>;
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
status = "disabled";
mdio: mdio {
@@ -914,7 +1041,7 @@
};
gic: interrupt-controller@1c81000 {
- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x2000>,
<0x01c84000 0x2000>,
@@ -924,6 +1051,18 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ csi: camera@1cb0000 {
+ compatible = "allwinner,sun8i-a83t-csi";
+ reg = <0x01cb0000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+ };
+
hdmi: hdmi@1ee0000 {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
@@ -935,7 +1074,7 @@
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
- phy-names = "hdmi-phy";
+ phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
@@ -981,7 +1120,7 @@
compatible = "allwinner,sun8i-a83t-r-ccu";
reg = <0x01f01400 0x400>;
clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
- <&ccu 6>;
+ <&ccu CLK_PLL_PERIPH>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
@@ -992,6 +1131,26 @@
reg = <0x1f01c00 0x400>;
};
+ r_cir: ir@1f02000 {
+ compatible = "allwinner,sun8i-a83t-ir",
+ "allwinner,sun6i-a31-ir";
+ clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
+ clock-names = "apb", "ir";
+ resets = <&r_ccu RST_APB0_IR>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x400>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_cir_pin>;
+ status = "disabled";
+ };
+
+ r_lradc: lradc@1f03c00 {
+ compatible = "allwinner,sun8i-a83t-r-lradc";
+ reg = <0x01f03c00 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
@@ -1004,6 +1163,11 @@
interrupt-controller;
#interrupt-cells = <3>;
+ r_cir_pin: r-cir-pin {
+ pins = "PL12";
+ function = "s_cir_rx";
+ };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
@@ -1026,5 +1190,82 @@
#address-cells = <1>;
#size-cells = <0>;
};
+
+ ths: thermal-sensor@1f04000 {
+ compatible = "allwinner,sun8i-a83t-ths";
+ reg = <0x01f04000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ nvmem-cells = <&ths_calibration>;
+ nvmem-cell-names = "calibration";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu0_thermal: cpu0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 0>;
+
+ trips {
+ cpu0_hot: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_very_hot: cpu-very-hot {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu0_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1_thermal: cpu1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 1>;
+
+ trips {
+ cpu1_hot: cpu-hot {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_very_hot: cpu-very-hot {
+ temperature = <100000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ cpu-hot-limit {
+ trip = <&cpu1_hot>;
+ cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&ths 2>;
+ };
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 08/12] ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (6 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 07/12] ARM: dts: sun8i: A83T: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-22 23:33 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 09/12] ARM: dts: sun8i: V3/V3s/S3: " Samuel Holland
` (5 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the H2+/H3/H5 SoCs and all existing
boards from the Linux v5.18-rc1 tag.
To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
This commit also adds the following new board devicetree:
- sun8i-h3-nanopi-r1.dts
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 2 +-
arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +-
arch/arm/dts/sun50i-h5.dtsi | 6 +-
.../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 28 ++-
arch/arm/dts/sun8i-h3-beelink-x2.dts | 27 ++-
arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 28 +++
arch/arm/dts/sun8i-h3-nanopi-r1.dts | 169 ++++++++++++++++++
arch/arm/dts/sun8i-h3-nanopi.dtsi | 1 +
arch/arm/dts/sun8i-h3-orangepi-2.dts | 3 +-
arch/arm/dts/sun8i-h3-orangepi-pc.dts | 3 +-
arch/arm/dts/sun8i-h3.dtsi | 10 +-
arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 18 +-
arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 4 +-
arch/arm/dts/sunxi-h3-h5.dtsi | 42 ++++-
arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 13 ++
arch/arm/dts/sunxi-libretech-all-h3-it.dtsi | 2 +-
17 files changed, 342 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6433f63455..bbd69d3a67 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -655,6 +655,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
+ sun8i-h3-nanopi-r1.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
diff --git a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
index b265720195..1afad8b437 100644
--- a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
+++ b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
@@ -2,7 +2,7 @@
// Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
/ {
- cpu_opp_table: cpu-opp-table {
+ cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
index 55bcdf8d1a..55b369534a 100644
--- a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
+++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
@@ -142,9 +142,16 @@
status = "okay";
eeprom@51 {
- compatible = "microchip,24c02";
+ compatible = "microchip,24c02", "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
+ read-only;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eth_mac1: mac-address@fa {
+ reg = <0xfa 0x06>;
+ };
};
};
diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi
index ab860e20d0..9b3462b13c 100644
--- a/arch/arm/dts/sun50i-h5.dtsi
+++ b/arch/arm/dts/sun50i-h5.dtsi
@@ -217,7 +217,7 @@
};
};
- gpu_thermal {
+ gpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 1>;
@@ -233,6 +233,10 @@
compatible = "allwinner,sun50i-h5-de2-clk";
};
+&mbus {
+ compatible = "allwinner,sun50i-h5-mbus";
+};
+
&mmc0 {
compatible = "allwinner,sun50i-h5-mmc",
"allwinner,sun50i-a64-mmc";
diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
index f3f7a2c912..d5c7b7984d 100644
--- a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
+++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
@@ -26,6 +26,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -41,8 +52,9 @@
sw4 {
label = "power";
- linux,code = <BTN_0>;
+ linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
};
@@ -103,10 +115,24 @@
cpu-supply = <®_vdd_cpux>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mmc0 {
vmmc-supply = <®_vcc3v3>;
bus-width = <4>;
diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts
index 62b5280ec0..cd9f655e4f 100644
--- a/arch/arm/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts
@@ -57,6 +57,12 @@
ethernet1 = &sdiowifi;
};
+ cec-gpio {
+ compatible = "cec-gpio";
+ cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
+ hdmi-phandle = <&hdmi>;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -87,11 +93,15 @@
};
};
- wifi_pwrseq: wifi_pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
- clocks = <&rtc 1>;
- clock-names = "ext_clock";
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ power {
+ label = "power";
+ linux,code = <KEY_POWER>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
};
sound_spdif {
@@ -111,6 +121,13 @@
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ };
};
&de {
diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
index be49eabbff..cd3df12b65 100644
--- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
+++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
@@ -103,12 +103,40 @@
};
};
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pa_pins>;
status = "okay";
};
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_vcc3v3>;
+ vddio-supply = <®_vcc3v3>;
+ device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
+ shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
+ };
+};
+
&usbphy {
/* USB VBUS is always on */
status = "okay";
diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
new file mode 100644
index 0000000000..26e2e6172e
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
+ * Copyright (C) 2020 Yu-Tung Chang <mtwget@gmail.com>
+*/
+
+#include "sun8i-h3-nanopi.dtsi"
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1";
+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3";
+
+ aliases {
+ serial1 = &uart1;
+ ethernet0 = &emac;
+ ethernet1 = &wifi;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+
+ reg_vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>;
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+ gpios-states = <0x1>;
+ states = <1100000 0x0>,
+ <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ };
+
+ leds {
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
+ };
+
+ led-3 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ wifi: wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+®_usb0_vbus {
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rtc 1>;
+ clock-names = "lpo";
+ vbat-supply = <®_vcc3v3>;
+ vddio-supply = <®_vcc3v3>;
+ device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
+ host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
+ shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
+ };
+};
+
+&usb_otg {
+ status = "okay";
+ dr_mode = "otg";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-h3-nanopi.dtsi b/arch/arm/dts/sun8i-h3-nanopi.dtsi
index c7c3e7d8b3..fc45d5aaa6 100644
--- a/arch/arm/dts/sun8i-h3-nanopi.dtsi
+++ b/arch/arm/dts/sun8i-h3-nanopi.dtsi
@@ -81,6 +81,7 @@
label = "k1";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
};
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
index 597c425d08..9daffd90c1 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts
@@ -99,8 +99,9 @@
sw4 {
label = "sw4";
- linux,code = <BTN_0>;
+ linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
};
diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
index 5aff8ecc66..90f75fa85e 100644
--- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
@@ -91,8 +91,9 @@
sw4 {
label = "sw4";
- linux,code = <BTN_0>;
+ linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
};
};
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index 4e89701df9..eac2349a23 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -44,7 +44,7 @@
#include <dt-bindings/thermal/thermal.h>
/ {
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
@@ -112,7 +112,7 @@
};
};
- gpu_opp_table: gpu-opp-table {
+ gpu_opp_table: opp-table-gpu {
compatible = "operating-points-v2";
opp-120000000 {
@@ -245,7 +245,7 @@
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
- thermal-sensors = <&ths 0>;
+ thermal-sensors = <&ths>;
trips {
cpu_hot_trip: cpu-hot {
@@ -282,6 +282,10 @@
compatible = "allwinner,sun8i-h3-de2-clk";
};
+&mbus {
+ compatible = "allwinner,sun8i-h3-mbus";
+};
+
&mmc0 {
compatible = "allwinner,sun7i-a20-mmc";
clocks = <&ccu CLK_BUS_MMC0>,
diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
index 22466afd38..235994a4a2 100644
--- a/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
+++ b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
@@ -16,15 +16,27 @@
regulator-type = "voltage";
regulator-boot-on;
regulator-always-on;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1300000>;
+ regulator-min-microvolt = <1108475>;
+ regulator-max-microvolt = <1308475>;
regulator-ramp-delay = <50>; /* 4ms */
gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
gpios-states = <0x1>;
- states = <1100000 0>, <1300000 1>;
+ states = <1108475 0>, <1308475 1>;
};
};
&cpu0 {
cpu-supply = <®_vdd_cpux>;
};
+
+&cpu1 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu2 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu3 {
+ cpu-supply = <®_vdd_cpux>;
+};
diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
index 8e5cb3b3fd..d03f5853ef 100644
--- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
+++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
@@ -82,8 +82,9 @@
sw4 {
label = "power";
- linux,code = <BTN_0>;
+ linux,code = <KEY_POWER>;
gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
};
};
@@ -219,6 +220,7 @@
bluetooth {
compatible = "brcm,bcm43438-bt";
+ max-speed = <1500000>;
clocks = <&rtc 1>;
clock-names = "lpo";
vbat-supply = <®_vcc3v3>;
diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi
index 9be13378d4..6cea57e07f 100644
--- a/arch/arm/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/dts/sunxi-h3-h5.dtsi
@@ -567,9 +567,14 @@
};
mbus: dram-controller@1c62000 {
- compatible = "allwinner,sun8i-h3-mbus";
- reg = <0x01c62000 0x1000>;
- clocks = <&ccu CLK_MBUS>;
+ /* compatible is in per SoC .dtsi file */
+ reg = <0x01c62000 0x1000>,
+ <0x01c63000 0x1000>;
+ reg-names = "mbus", "dram";
+ clocks = <&ccu CLK_MBUS>,
+ <&ccu CLK_DRAM>,
+ <&ccu CLK_BUS_DRAM>;
+ clock-names = "mbus", "dram", "bus";
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
@@ -812,8 +817,8 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
- <&ccu CLK_HDMI>;
- clock-names = "iahb", "isfr", "tmds";
+ <&ccu CLK_HDMI>, <&rtc 0>;
+ clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
@@ -859,6 +864,15 @@
#clock-cells = <1>;
};
+ r_intc: interrupt-controller@1f00c00 {
+ compatible = "allwinner,sun8i-h3-r-intc",
+ "allwinner,sun6i-a31-r-intc";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x01f00c00 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-h3-r-ccu";
reg = <0x01f01400 0x100>;
@@ -897,6 +911,19 @@
#size-cells = <0>;
};
+ r_uart: serial@1f02800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01f02800 0x400>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&r_ccu CLK_APB0_UART>;
+ resets = <&r_ccu RST_APB0_UART>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins>;
+ status = "disabled";
+ };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-h3-r-pinctrl";
reg = <0x01f02c00 0x400>;
@@ -922,6 +949,11 @@
pins = "PL10";
function = "s_pwm";
};
+
+ r_uart_pins: r-uart-pins {
+ pins = "PL2", "PL3";
+ function = "s_uart";
+ };
};
r_pwm: pwm@1f03800 {
diff --git a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
index 19b3b23cfa..9e14fe5fdc 100644
--- a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
+++ b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
@@ -49,6 +49,7 @@
label = "power";
linux,code = <KEY_POWER>;
gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ wakeup-source;
};
};
@@ -128,6 +129,18 @@
cpu-supply = <®_vdd_cpux>;
};
+&cpu1 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu2 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
+&cpu3 {
+ cpu-supply = <®_vdd_cpux>;
+};
+
&de {
status = "okay";
};
diff --git a/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
index 204fba3614..50d328c2a8 100644
--- a/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
+++ b/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
@@ -156,7 +156,7 @@
&spi0 {
status = "okay";
- spiflash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 09/12] ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (7 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 08/12] ARM: dts: sunxi: H2+/H3/H5: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-22 22:22 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 10/12] ARM: dts: sun8i: R40/T3: " Samuel Holland
` (4 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the V3(s)/S3 SoCs and all existing boards
verbatim from the Linux v5.18-rc1 tag.
This commit also adds the following new board devicetrees:
- sun8i-s3-elimo-initium.dts
- sun8i-v3-sl631-imx179.dts
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun8i-s3-elimo-impetus.dtsi | 44 ++++++
arch/arm/dts/sun8i-s3-elimo-initium.dts | 29 ++++
arch/arm/dts/sun8i-s3-pinecube.dts | 13 +-
arch/arm/dts/sun8i-v3-sl631-imx179.dts | 12 ++
arch/arm/dts/sun8i-v3-sl631.dtsi | 138 ++++++++++++++++++
arch/arm/dts/sun8i-v3.dtsi | 36 +++++
arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 17 ++-
arch/arm/dts/sun8i-v3s.dtsi | 93 ++++++++++--
9 files changed, 358 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
create mode 100644 arch/arm/dts/sun8i-s3-elimo-initium.dts
create mode 100644 arch/arm/dts/sun8i-v3-sl631-imx179.dts
create mode 100644 arch/arm/dts/sun8i-v3-sl631.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index bbd69d3a67..059ac7fad8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -670,7 +670,9 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+ sun8i-s3-elimo-initium.dtb \
sun8i-s3-pinecube.dtb \
+ sun8i-v3-sl631-imx179.dtb \
sun8i-v3s-licheepi-zero.dtb
dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-bananapi-m2-plus.dtb \
diff --git a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
new file mode 100644
index 0000000000..052b010a56
--- /dev/null
+++ b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
+ */
+
+/dts-v1/;
+#include "sun8i-v3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+ model = "Elimo Impetus SoM";
+ compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-s3-elimo-initium.dts b/arch/arm/dts/sun8i-s3-elimo-initium.dts
new file mode 100644
index 0000000000..039677c2cc
--- /dev/null
+++ b/arch/arm/dts/sun8i-s3-elimo-initium.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
+ */
+
+/dts-v1/;
+#include "sun8i-s3-elimo-impetus.dtsi"
+
+/ {
+ model = "Elimo Initium";
+ compatible = "elimo,initium", "elimo,impetus", "sochip,s3",
+ "allwinner,sun8i-v3";
+
+ aliases {
+ serial1 = &uart1;
+ };
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pg_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts
index 9bab6b7f40..20966e954e 100644
--- a/arch/arm/dts/sun8i-s3-pinecube.dts
+++ b/arch/arm/dts/sun8i-s3-pinecube.dts
@@ -10,7 +10,7 @@
/ {
model = "PineCube IP Camera";
- compatible = "pine64,pinecube", "allwinner,sun8i-s3";
+ compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
aliases {
serial0 = &uart2;
@@ -64,9 +64,6 @@
status = "okay";
port {
- #address-cells = <1>;
- #size-cells = <0>;
-
csi1_ep: endpoint {
remote-endpoint = <&ov5640_ep>;
bus-width = <8>;
@@ -88,13 +85,9 @@
status = "okay";
axp209: pmic@34 {
- compatible = "x-powers,axp203",
- "x-powers,axp209";
reg = <0x34>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/dts/sun8i-v3-sl631-imx179.dts
new file mode 100644
index 0000000000..117aeece4e
--- /dev/null
+++ b/arch/arm/dts/sun8i-v3-sl631-imx179.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+#include "sun8i-v3-sl631.dtsi"
+
+/ {
+ model = "SL631 Action Camera with IMX179";
+ compatible = "allwinner,sl631-imx179", "allwinner,sl631",
+ "allwinner,sun8i-v3";
+};
diff --git a/arch/arm/dts/sun8i-v3-sl631.dtsi b/arch/arm/dts/sun8i-v3-sl631.dtsi
new file mode 100644
index 0000000000..6f93f8c49f
--- /dev/null
+++ b/arch/arm/dts/sun8i-v3-sl631.dtsi
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
+ */
+
+/dts-v1/;
+
+#include "sun8i-v3.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "SL631 Action Camera";
+ compatible = "allwinner,sl631", "allwinner,sun8i-v3";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pb_pins>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <®_ldo2>;
+ status = "okay";
+
+ button-174 {
+ label = "Down";
+ linux,code = <KEY_DOWN>;
+ channel = <0>;
+ voltage = <174603>;
+ };
+
+ button-384 {
+ label = "Up";
+ linux,code = <KEY_UP>;
+ channel = <0>;
+ voltage = <384126>;
+ };
+
+ button-593 {
+ label = "OK";
+ linux,code = <KEY_OK>;
+ channel = <0>;
+ voltage = <593650>;
+ };
+};
+
+&mmc0 {
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ vmmc-supply = <®_dcdc3>;
+ status = "okay";
+};
+
+&pio {
+ vcc-pd-supply = <®_dcdc3>;
+ vcc-pe-supply = <®_dcdc3>;
+};
+
+#include "axp209.dtsi"
+
+&ac_power_supply {
+ status = "okay";
+};
+
+&battery_power_supply {
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-sys-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vdd-3v3";
+};
+
+®_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pg_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi
index ca4672ed2e..186c30cbe6 100644
--- a/arch/arm/dts/sun8i-v3.dtsi
+++ b/arch/arm/dts/sun8i-v3.dtsi
@@ -1,14 +1,40 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*/
#include "sun8i-v3s.dtsi"
+/ {
+ soc {
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-v3-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 3>, <&dma 3>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_pins>;
+ resets = <&ccu RST_BUS_I2S0>;
+ status = "disabled";
+ };
+ };
+};
+
&ccu {
compatible = "allwinner,sun8i-v3-ccu";
};
+&codec_analog {
+ compatible = "allwinner,sun8i-v3-codec-analog",
+ "allwinner,sun8i-h3-codec-analog";
+};
+
&emac {
/delete-property/ phy-handle;
/delete-property/ phy-mode;
@@ -24,4 +50,14 @@
&pio {
compatible = "allwinner,sun8i-v3-pinctrl";
+
+ i2s0_pins: i2s0-pins {
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "i2s";
+ };
+
+ uart1_pg_pins: uart1-pg-pins {
+ pins = "PG6", "PG7";
+ function = "uart1";
+ };
};
diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
index db5cd0b857..752ad05c8f 100644
--- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
+++ b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
@@ -49,16 +49,18 @@
compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
"allwinner,sun8i-v3s";
+ aliases {
+ ethernet0 = &emac;
+ };
+
leds {
/* The LEDs use PG0~2 pins, which conflict with MMC1 */
status = "disabled";
};
};
-&mmc1 {
- broken-cd;
- bus-width = <4>;
- vmmc-supply = <®_vcc3v3>;
+&emac {
+ allwinner,leds-active-low;
status = "okay";
};
@@ -94,3 +96,10 @@
voltage = <800000>;
};
};
+
+&mmc1 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
index 0c73416769..084323d5c6 100644
--- a/arch/arm/dts/sun8i-v3s.dtsi
+++ b/arch/arm/dts/sun8i-v3s.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -157,12 +158,30 @@
syscon: system-control@1c00000 {
compatible = "allwinner,sun8i-v3s-system-control",
"allwinner,sun8i-h3-system-control";
- reg = <0x01c00000 0x1000>;
+ reg = <0x01c00000 0xd0>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
+ nmi_intc: interrupt-controller@1c000d0 {
+ compatible = "allwinner,sun8i-v3s-nmi",
+ "allwinner,sun9i-a80-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c000d0 0x0c>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun8i-v3s-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-v3s-tcon";
reg = <0x01c0c000 0x1000>;
@@ -266,6 +285,8 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
clock-names = "ahb", "mod";
+ dmas = <&dma 16>, <&dma 16>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_CE>;
reset-names = "ahb";
};
@@ -328,6 +349,12 @@
interrupt-controller;
#interrupt-cells = <3>;
+ /omit-if-no-ref/
+ csi0_mclk_pin: csi0-mclk-pin {
+ pins = "PE20";
+ function = "csi_mipi";
+ };
+
/omit-if-no-ref/
csi1_8bit_pins: csi1-8bit-pins {
pins = "PE0", "PE2", "PE3", "PE8", "PE9",
@@ -347,6 +374,12 @@
function = "i2c0";
};
+ /omit-if-no-ref/
+ i2c1_pb_pins: i2c1-pb-pins {
+ pins = "PB8", "PB9";
+ function = "i2c1";
+ };
+
/omit-if-no-ref/
i2c1_pe_pins: i2c1-pe-pins {
pins = "PE21", "PE22";
@@ -401,6 +434,15 @@
clocks = <&osc24M>;
};
+ pwm: pwm@1c21400 {
+ compatible = "allwinner,sun8i-v3s-pwm",
+ "allwinner,sun7i-a20-pwm";
+ reg = <0x01c21400 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x400>;
@@ -408,6 +450,25 @@
status = "disabled";
};
+ codec: codec@1c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-v3s-codec";
+ reg = <0x01c22c00 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+ clock-names = "apb", "codec";
+ resets = <&ccu RST_BUS_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ allwinner,codec-analog-controls = <&codec_analog>;
+ status = "disabled";
+ };
+
+ codec_analog: codec-analog@1c23000 {
+ compatible = "allwinner,sun8i-v3s-codec-analog";
+ reg = <0x01c23000 0x4>;
+ };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@@ -415,6 +476,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -426,6 +489,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -437,6 +502,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART2>;
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
@@ -516,6 +583,8 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
@@ -524,6 +593,17 @@
#size-cells = <0>;
};
+ gic: interrupt-controller@1c81000 {
+ compatible = "arm,gic-400";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x2000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
@@ -535,16 +615,5 @@
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
};
-
- gic: interrupt-controller@1c81000 {
- compatible = "arm,gic-400";
- reg = <0x01c81000 0x1000>,
- <0x01c82000 0x1000>,
- <0x01c84000 0x2000>,
- <0x01c86000 0x2000>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- };
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 10/12] ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (8 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 09/12] ARM: dts: sun8i: V3/V3s/S3: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-22 22:38 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 11/12] ARM: dts: sun50i: A64: " Samuel Holland
` (3 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree for the R40/T3 SoC verbatim from the Linux v5.18-rc1
tag. None of the existing boards had any devicetree updates.
This commit adds the following new board devicetrees:
- sun8i-r40-oka40i-c.dts
- sun8i-t3-cqa3t-bv3.dts
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun8i-r40-feta40i.dtsi | 106 +++++++++++++
arch/arm/dts/sun8i-r40-oka40i-c.dts | 203 +++++++++++++++++++++++++
arch/arm/dts/sun8i-r40.dtsi | 118 ++++++++++++++-
arch/arm/dts/sun8i-t3-cqa3t-bv3.dts | 226 ++++++++++++++++++++++++++++
5 files changed, 653 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/sun8i-r40-feta40i.dtsi
create mode 100644 arch/arm/dts/sun8i-r40-oka40i-c.dts
create mode 100644 arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 059ac7fad8..95909ef037 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -668,6 +668,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-zeropi.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
+ sun8i-r40-oka40i-c.dtb \
+ sun8i-t3-cqa3t-bv3.dtb \
sun8i-v40-bananapi-m2-berry.dtb
dtb-$(CONFIG_MACH_SUN8I_V3S) += \
sun8i-s3-elimo-initium.dtb \
diff --git a/arch/arm/dts/sun8i-r40-feta40i.dtsi b/arch/arm/dts/sun8i-r40-feta40i.dtsi
new file mode 100644
index 0000000000..265e0fa57a
--- /dev/null
+++ b/arch/arm/dts/sun8i-r40-feta40i.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+#include "sun8i-r40.dtsi"
+
+&i2c0 {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+&mmc2 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_aldo2>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_out_a_pin>;
+ vcc-pa-supply = <®_dcdc1>;
+ vcc-pc-supply = <®_aldo2>;
+ vcc-pd-supply = <®_dcdc1>;
+ vcc-pf-supply = <®_dldo4>;
+ vcc-pg-supply = <®_dldo1>;
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pa";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd2v5-sata";
+};
+
+®_eldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd1v2-sata";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
diff --git a/arch/arm/dts/sun8i-r40-oka40i-c.dts b/arch/arm/dts/sun8i-r40-oka40i-c.dts
new file mode 100644
index 0000000000..0bd1336206
--- /dev/null
+++ b/arch/arm/dts/sun8i-r40-oka40i-c.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+/dts-v1/;
+#include "sun8i-r40-feta40i.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Forlinx OKA40i-C";
+ compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40";
+
+ aliases {
+ ethernet0 = &gmac;
+ serial0 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5; /* RS485 */
+ serial7 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-5 { /* this is how the leds are labeled on the board */
+ gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led-6 {
+ gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "ext_clock";
+ };
+};
+
+&ahci {
+ ahci-supply = <®_dldo4>;
+ phy-supply = <®_eldo2>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <®_dcdc1>;
+ status = "okay";
+};
+
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
+ status = "okay";
+};
+
+&mmc3 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+®_dc1sw {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-lcd";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&tcon_tv0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pg_pins>;
+ status = "okay";
+};
+
+&uart5 { /* RS485 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_ph_pins>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pi_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v0>;
+ usb2_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
index d5ad3b9efd..03d3e5f45a 100644
--- a/arch/arm/dts/sun8i-r40.dtsi
+++ b/arch/arm/dts/sun8i-r40.dtsi
@@ -357,6 +357,8 @@
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC3>;
reset-names = "ahb";
+ pinctrl-0 = <&mmc3_pins>;
+ pinctrl-names = "default";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
@@ -509,6 +511,16 @@
#interrupt-cells = <3>;
#gpio-cells = <3>;
+ can_ph_pins: can-ph-pins {
+ pins = "PH20", "PH21";
+ function = "can";
+ };
+
+ can_pa_pins: can-pa-pins {
+ pins = "PA16", "PA17";
+ function = "can";
+ };
+
clk_out_a_pin: clk-out-a-pin {
pins = "PI12";
function = "clk_out_a";
@@ -601,6 +613,15 @@
bias-pull-up;
};
+ /omit-if-no-ref/
+ mmc3_pins: mmc3-pins {
+ pins = "PI4", "PI5", "PI6",
+ "PI7", "PI8", "PI9";
+ function = "mmc3";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
/omit-if-no-ref/
spi0_pc_pins: spi0-pc-pins {
pins = "PC0", "PC1", "PC2";
@@ -631,20 +652,65 @@
function = "spi1";
};
+ /omit-if-no-ref/
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
};
+ /omit-if-no-ref/
+ uart2_pi_pins: uart2-pi-pins {
+ pins = "PI18", "PI19";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
+ uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
+ pins = "PI16", "PI17";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
uart3_pg_pins: uart3-pg-pins {
pins = "PG6", "PG7";
function = "uart3";
};
+ /omit-if-no-ref/
uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
pins = "PG8", "PG9";
function = "uart3";
};
+
+ /omit-if-no-ref/
+ uart4_pg_pins: uart4-pg-pins {
+ pins = "PG10", "PG11";
+ function = "uart4";
+ };
+
+ /omit-if-no-ref/
+ uart5_ph_pins: uart5-ph-pins {
+ pins = "PH6", "PH7";
+ function = "uart5";
+ };
+
+ /omit-if-no-ref/
+ uart7_pi_pins: uart7-pi-pins {
+ pins = "PI20", "PI21";
+ function = "uart7";
+ };
+ };
+
+ timer@1c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
wdt: watchdog@1c20c90 {
@@ -680,6 +746,45 @@
status = "disabled";
};
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-r40-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S0>;
+ dmas = <&dma 3>, <&dma 3>;
+ dma-names = "rx", "tx";
+ };
+
+ i2s1: i2s@1c22400 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-r40-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22400 0x400>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S1>;
+ dmas = <&dma 4>, <&dma 4>;
+ dma-names = "rx", "tx";
+ };
+
+ i2s2: i2s@1c22800 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-r40-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22800 0x400>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
+ clock-names = "apb", "mod";
+ resets = <&ccu RST_BUS_I2S2>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
+ };
+
ths: thermal-sensor@1c24c00 {
compatible = "allwinner,sun8i-r40-ths";
reg = <0x01c24c00 0x100>;
@@ -831,6 +936,15 @@
#size-cells = <0>;
};
+ can0: can@1c2bc00 {
+ compatible = "allwinner,sun8i-r40-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CAN>;
+ resets = <&ccu RST_BUS_CAN>;
+ status = "disabled";
+ };
+
i2c4: i2c@1c2c000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2c000 0x400>;
@@ -1117,8 +1231,8 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
- <&ccu CLK_HDMI>;
- clock-names = "iahb", "isfr", "tmds";
+ <&ccu CLK_HDMI>, <&rtc 0>;
+ clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
diff --git a/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
new file mode 100644
index 0000000000..6931aaab23
--- /dev/null
+++ b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
@@ -0,0 +1,226 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright (C) 2018 Hao Zhang <hao5781286@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-r40.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "t3-cqa3t-bv3";
+ compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3",
+ "allwinner,sun8i-r40";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
+ enable-active-high;
+ };
+};
+
+&ahci {
+ ahci-supply = <®_dldo4>;
+ phy-supply = <®_eldo3>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+&mmc0 {
+ vmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-pa";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pg";
+};
+
+®_dldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-dldo3";
+};
+
+®_eldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
+
+&tcon_tv0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v0>;
+ usb2_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 11/12] ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (9 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 10/12] ARM: dts: sun8i: R40/T3: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-20 14:01 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 12/12] ARM: dts: sun50i: H6: " Samuel Holland
` (2 subsequent siblings)
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the A64 SoC and all existing boards
from the Linux v5.18-rc1 tag.
To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/axp803.dtsi | 10 +--
arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 2 +-
arch/arm/dts/sun50i-a64-orangepi-win.dts | 2 +-
arch/arm/dts/sun50i-a64-pinebook.dts | 1 +
arch/arm/dts/sun50i-a64-pinephone.dtsi | 27 +++++++
arch/arm/dts/sun50i-a64-pinetab.dts | 29 +++++++-
arch/arm/dts/sun50i-a64-teres-i.dts | 4 +-
arch/arm/dts/sun50i-a64.dtsi | 93 ++++++++++++++++++------
8 files changed, 137 insertions(+), 31 deletions(-)
diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi
index 10e9186a76..578ef368e2 100644
--- a/arch/arm/dts/axp803.dtsi
+++ b/arch/arm/dts/axp803.dtsi
@@ -10,7 +10,7 @@
interrupt-controller;
#interrupt-cells = <1>;
- ac_power_supply: ac-power-supply {
+ ac_power_supply: ac-power {
compatible = "x-powers,axp803-ac-power-supply",
"x-powers,axp813-ac-power-supply";
status = "disabled";
@@ -26,18 +26,18 @@
gpio-controller;
#gpio-cells = <2>;
- gpio0_ldo: gpio0-ldo {
+ gpio0_ldo: gpio0-ldo-pin {
pins = "GPIO0";
function = "ldo";
};
- gpio1_ldo: gpio1-ldo {
+ gpio1_ldo: gpio1-ldo-pin {
pins = "GPIO1";
function = "ldo";
};
};
- battery_power_supply: battery-power-supply {
+ battery_power_supply: battery-power {
compatible = "x-powers,axp803-battery-power-supply",
"x-powers,axp813-battery-power-supply";
status = "disabled";
@@ -147,7 +147,7 @@
};
};
- usb_power_supply: usb-power-supply {
+ usb_power_supply: usb-power {
compatible = "x-powers,axp803-usb-power-supply",
"x-powers,axp813-usb-power-supply";
status = "disabled";
diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
index 578c37490d..e39db51eb4 100644
--- a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
+++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
@@ -4,7 +4,7 @@
*/
/ {
- cpu0_opp_table: opp_table0 {
+ cpu0_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts
index 70e31743f0..8eee8051ac 100644
--- a/arch/arm/dts/sun50i-a64-orangepi-win.dts
+++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts
@@ -343,7 +343,7 @@
&spi0 {
status = "okay";
- spi-flash@0 {
+ flash@0 {
compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts
index 7ae16541d1..68b6ab4707 100644
--- a/arch/arm/dts/sun50i-a64-pinebook.dts
+++ b/arch/arm/dts/sun50i-a64-pinebook.dts
@@ -15,6 +15,7 @@
/ {
model = "Pinebook";
compatible = "pine64,pinebook", "allwinner,sun50i-a64";
+ chassis-type = "laptop";
aliases {
serial0 = &uart0;
diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi
index 9f69d489a8..b25e7913f5 100644
--- a/arch/arm/dts/sun50i-a64-pinephone.dtsi
+++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi
@@ -12,6 +12,8 @@
#include <dt-bindings/pwm/pwm.h>
/ {
+ chassis-type = "handset";
+
aliases {
ethernet0 = &rtl8723cs;
serial0 = &uart0;
@@ -25,6 +27,11 @@
/* Backlight configuration differs per PinePhone revision. */
};
+ bt_sco_codec: bt-sco-codec {
+ #sound-dai-cells = <1>;
+ compatible = "linux,bt-sco";
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -91,6 +98,8 @@
};
&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&aif3_pins>;
status = "okay";
};
@@ -426,6 +435,7 @@
&sound {
status = "okay";
+ simple-audio-card,name = "PinePhone";
simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
simple-audio-card,widgets = "Microphone", "Headset Microphone",
"Microphone", "Internal Microphone",
@@ -447,6 +457,23 @@
"MIC1", "Internal Microphone",
"Headset Microphone", "HBIAS",
"MIC2", "Headset Microphone";
+
+ simple-audio-card,dai-link@2 {
+ format = "dsp_a";
+ frame-master = <&link2_codec>;
+ bitclock-master = <&link2_codec>;
+ bitclock-inversion;
+
+ link2_cpu: cpu {
+ sound-dai = <&bt_sco_codec 0>;
+ };
+
+ link2_codec: codec {
+ sound-dai = <&codec 2>;
+ dai-tdm-slot-num = <1>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
};
&uart0 {
diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts
index 422a8507f6..0b2258ef88 100644
--- a/arch/arm/dts/sun50i-a64-pinetab.dts
+++ b/arch/arm/dts/sun50i-a64-pinetab.dts
@@ -16,6 +16,7 @@
/ {
model = "PineTab, Development Sample";
compatible = "pine64,pinetab", "allwinner,sun50i-a64";
+ chassis-type = "tablet";
aliases {
serial0 = &uart0;
@@ -35,6 +36,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "c";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
i2c-csi {
compatible = "i2c-gpio";
sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */
@@ -77,7 +89,7 @@
sound-name-prefix = "Speaker Amp";
};
- vdd_bl: regulator@0 {
+ vdd_bl: regulator {
compatible = "regulator-fixed";
regulator-name = "bl-3v3";
regulator-min-microvolt = <3300000>;
@@ -410,6 +422,21 @@
regulator-name = "vcc-rtc";
};
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
+&hdmi {
+ hvcc-supply = <®_dldo1>;
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&sound {
status = "okay";
simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts
index f0a16f355e..6668431dcb 100644
--- a/arch/arm/dts/sun50i-a64-teres-i.dts
+++ b/arch/arm/dts/sun50i-a64-teres-i.dts
@@ -14,6 +14,7 @@
/ {
model = "Olimex A64 Teres-I";
compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
+ chassis-type = "laptop";
aliases {
serial0 = &uart0;
@@ -139,6 +140,8 @@
#size-cells = <0>;
port@0 {
+ reg = <0>;
+
anx6345_in: endpoint {
remote-endpoint = <&tcon0_out_anx6345>;
};
@@ -206,7 +209,6 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
- wakeup-source;
};
};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 57786fc120..555bc92a6f 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -102,6 +102,22 @@
status = "disabled";
};
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-120000000 {
+ opp-hz = /bits/ 64 <120000000>;
+ };
+
+ opp-312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp-432000000 {
+ opp-hz = /bits/ 64 <432000000>;
+ };
+ };
+
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -131,12 +147,10 @@
};
sound: sound {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "simple-audio-card";
simple-audio-card,name = "sun50i-a64-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&cpudai>;
- simple-audio-card,bitclock-master = <&cpudai>;
- simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "DACL",
@@ -145,12 +159,19 @@
"ADCR", "Right ADC";
status = "disabled";
- cpudai: simple-audio-card,cpu {
- sound-dai = <&dai>;
- };
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ frame-master = <&link0_cpu>;
+ bitclock-master = <&link0_cpu>;
+ mclk-fs = <128>;
+
+ link0_cpu: cpu {
+ sound-dai = <&dai>;
+ };
- link_codec: simple-audio-card,codec {
- sound-dai = <&codec>;
+ link0_codec: codec {
+ sound-dai = <&codec 0>;
+ };
};
};
@@ -658,6 +679,18 @@
interrupt-controller;
#interrupt-cells = <3>;
+ /omit-if-no-ref/
+ aif2_pins: aif2-pins {
+ pins = "PB4", "PB5", "PB6", "PB7";
+ function = "aif2";
+ };
+
+ /omit-if-no-ref/
+ aif3_pins: aif3-pins {
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "aif3";
+ };
+
csi_pins: csi-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
"PE7", "PE8", "PE9", "PE10", "PE11";
@@ -798,6 +831,23 @@
};
};
+ timer@1c20c00 {
+ compatible = "allwinner,sun50i-a64-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@1c20ca0 {
+ compatible = "allwinner,sun50i-a64-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-spdif",
@@ -878,7 +928,7 @@
};
codec: codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun50i-a64-codec",
"allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x600>;
@@ -1067,6 +1117,7 @@
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_BUS_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
};
gic: interrupt-controller@1c81000 {
@@ -1093,8 +1144,14 @@
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun50i-a64-mbus";
- reg = <0x01c62000 0x1000>;
- clocks = <&ccu 112>;
+ reg = <0x01c62000 0x1000>,
+ <0x01c63000 0x1000>;
+ reg-names = "mbus", "dram";
+ clocks = <&ccu CLK_MBUS>,
+ <&ccu CLK_DRAM>,
+ <&ccu CLK_BUS_DRAM>;
+ clock-names = "mbus", "dram", "bus";
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x00000000 0x40000000 0xc0000000>;
@@ -1167,8 +1224,8 @@
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
- <&ccu CLK_HDMI>;
- clock-names = "iahb", "isfr", "tmds";
+ <&ccu CLK_HDMI>, <&rtc 0>;
+ clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
@@ -1321,13 +1378,5 @@
#address-cells = <1>;
#size-cells = <0>;
};
-
- wdt0: watchdog@1c20ca0 {
- compatible = "allwinner,sun50i-a64-wdt",
- "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 12/12] ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (10 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 11/12] ARM: dts: sun50i: A64: " Samuel Holland
@ 2022-04-27 20:31 ` Samuel Holland
2022-05-20 14:14 ` Andre Przywara
2022-04-29 14:51 ` [PATCH 00/12] sunxi: Devicetree sync " Andre Przywara
2022-05-24 15:58 ` Andre Przywara
13 siblings, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-27 20:31 UTC (permalink / raw)
To: u-boot, Jagan Teki, Andre Przywara; +Cc: Samuel Holland, Tom Rini
Copy the devicetree source for the H6 SoC and all existing boards
from the Linux v5.18-rc1 tag.
To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.
This commit also adds the following new board devicetrees:
- sun50i-h6-pine-h64-model-b.dts
- sun50i-h6-tanix-tx6-mini.dts
This update should not impact any existing U-Boot functionality.
Signed-off-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/sun50i-h6-beelink-gs1.dts | 38 ++--
arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 2 +-
arch/arm/dts/sun50i-h6-orangepi-3.dts | 14 +-
arch/arm/dts/sun50i-h6-orangepi.dtsi | 22 +--
arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 51 ++++++
arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts | 15 ++
arch/arm/dts/sun50i-h6-tanix-tx6.dts | 115 ++----------
arch/arm/dts/sun50i-h6-tanix.dtsi | 189 ++++++++++++++++++++
arch/arm/dts/sun50i-h6.dtsi | 26 ++-
10 files changed, 328 insertions(+), 148 deletions(-)
create mode 100644 arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
create mode 100644 arch/arm/dts/sun50i-h6-tanix.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 95909ef037..85e731aec9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -695,7 +695,9 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-orangepi-lite2.dtb \
sun50i-h6-orangepi-one-plus.dtb \
sun50i-h6-pine-h64.dtb \
- sun50i-h6-tanix-tx6.dtb
+ sun50i-h6-pine-h64-model-b.dtb \
+ sun50i-h6-tanix-tx6.dtb \
+ sun50i-h6-tanix-tx6-mini.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
index b5808047d6..649b146dff 100644
--- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
@@ -150,12 +150,28 @@
vcc-pg-supply = <®_aldo1>;
};
-&r_i2c {
+&r_ir {
+ linux,rc-map-name = "rc-beelink-gs1";
+ status = "okay";
+};
+
+&r_pio {
+ /*
+ * FIXME: We can't add that supply for now since it would
+ * create a circular dependency between pinctrl, the regulator
+ * and the RSB Bus.
+ *
+ * vcc-pl-supply = <®_aldo1>;
+ */
+ vcc-pm-supply = <®_aldo1>;
+};
+
+&r_rsb {
status = "okay";
- axp805: pmic@36 {
+ axp805: pmic@745 {
compatible = "x-powers,axp805", "x-powers,axp806";
- reg = <0x36>;
+ reg = <0x745>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -273,22 +289,6 @@
};
};
-&r_ir {
- linux,rc-map-name = "rc-beelink-gs1";
- status = "okay";
-};
-
-&r_pio {
- /*
- * PL0 and PL1 are used for PMIC I2C
- * don't enable the pl-supply else
- * it will fail at boot
- *
- * vcc-pl-supply = <®_aldo1>;
- */
- vcc-pm-supply = <®_aldo1>;
-};
-
&spdif {
status = "okay";
};
diff --git a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
index 8c6e8536b6..0baf0f8e4d 100644
--- a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
+++ b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
@@ -3,7 +3,7 @@
// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
/ {
- cpu_opp_table: cpu-opp-table {
+ cpu_opp_table: opp-table-cpu {
compatible = "allwinner,sun50i-h6-operating-points";
nvmem-cells = <&cpu_speed_grade>;
opp-shared;
diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts
index 7e83f6146f..9f12c05e21 100644
--- a/arch/arm/dts/sun50i-h6-orangepi-3.dts
+++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts
@@ -175,12 +175,16 @@
vcc-pg-supply = <®_vcc_wifi_io>;
};
-&r_i2c {
+&r_ir {
+ status = "okay";
+};
+
+&r_rsb {
status = "okay";
- axp805: pmic@36 {
+ axp805: pmic@745 {
compatible = "x-powers,axp805", "x-powers,axp806";
- reg = <0x36>;
+ reg = <0x745>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -291,10 +295,6 @@
};
};
-&r_ir {
- status = "okay";
-};
-
&rtc {
clocks = <&ext_osc32k>;
};
diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi
index da0875bd38..a5811d55bb 100644
--- a/arch/arm/dts/sun50i-h6-orangepi.dtsi
+++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi
@@ -112,12 +112,20 @@
vcc-pg-supply = <®_aldo1>;
};
-&r_i2c {
+&r_ir {
+ status = "okay";
+};
+
+&r_pio {
+ vcc-pm-supply = <®_bldo3>;
+};
+
+&r_rsb {
status = "okay";
- axp805: pmic@36 {
+ axp805: pmic@745 {
compatible = "x-powers,axp805", "x-powers,axp806";
- reg = <0x36>;
+ reg = <0x745>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
@@ -232,14 +240,6 @@
};
};
-&r_ir {
- status = "okay";
-};
-
-&r_pio {
- vcc-pm-supply = <®_bldo3>;
-};
-
&rtc {
clocks = <&ext_osc32k>;
};
diff --git a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
new file mode 100644
index 0000000000..686f58e770
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2019 Corentin LABBE <clabbe@baylibre.com>
+ */
+
+#include "sun50i-h6-pine-h64.dts"
+
+/ {
+ model = "Pine H64 model B";
+ compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6";
+
+ /delete-node/ reg_gmac_3v3;
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&hdmi_connector {
+ /delete-property/ ddc-en-gpios;
+};
+
+&emac {
+ phy-supply = <®_aldo2>;
+};
+
+&mmc1 {
+ vmmc-supply = <®_cldo3>;
+ vqmmc-supply = <®_aldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "realtek,rtl8723bs-bt";
+ device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
+ host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
+ enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
+ max-speed = <1500000>;
+ };
+};
diff --git a/arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts b/arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
new file mode 100644
index 0000000000..08d84160d8
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
+
+/dts-v1/;
+
+#include "sun50i-h6-tanix.dtsi"
+
+/ {
+ model = "Tanix TX6 mini";
+ compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6";
+};
+
+&r_ir {
+ linux,rc-map-name = "rc-tanix-tx3mini";
+};
diff --git a/arch/arm/dts/sun50i-h6-tanix-tx6.dts b/arch/arm/dts/sun50i-h6-tanix-tx6.dts
index be81330db1..9a38ff9b3f 100644
--- a/arch/arm/dts/sun50i-h6-tanix-tx6.dts
+++ b/arch/arm/dts/sun50i-h6-tanix-tx6.dts
@@ -3,122 +3,27 @@
/dts-v1/;
-#include "sun50i-h6.dtsi"
-#include "sun50i-h6-cpu-opp.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
+#include "sun50i-h6-tanix.dtsi"
/ {
model = "Tanix TX6";
compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- connector {
- compatible = "hdmi-connector";
- ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
- type = "a";
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi_out_con>;
- };
- };
- };
-
- reg_vcc3v3: vcc3v3 {
- compatible = "regulator-fixed";
- regulator-name = "vcc3v3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- reg_vdd_cpu_gpu: vdd-cpu-gpu {
- compatible = "regulator-fixed";
- regulator-name = "vdd-cpu-gpu";
- regulator-min-microvolt = <1135000>;
- regulator-max-microvolt = <1135000>;
- };
-};
-
-&cpu0 {
- cpu-supply = <®_vdd_cpu_gpu>;
-};
-
-&de {
- status = "okay";
-};
-
-&dwc3 {
- status = "okay";
-};
-
-&ehci0 {
- status = "okay";
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&gpu {
- mali-supply = <®_vdd_cpu_gpu>;
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-};
-
-&hdmi_out {
- hdmi_out_con: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
-};
-
-&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins>;
- vmmc-supply = <®_vcc3v3>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
- bus-width = <4>;
- status = "okay";
-};
-
-&ohci0 {
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
};
&r_ir {
linux,rc-map-name = "rc-tanix-tx5max";
- status = "okay";
};
-&uart0 {
+&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&uart0_ph_pins>;
+ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+ uart-has-rtscts;
status = "okay";
-};
-&usb2otg {
- dr_mode = "host";
- status = "okay";
-};
-
-&usb2phy {
- status = "okay";
-};
-
-&usb3phy {
- status = "okay";
+ bluetooth {
+ compatible = "realtek,rtl8822cs-bt";
+ device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
+ host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
+ enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
+ };
};
diff --git a/arch/arm/dts/sun50i-h6-tanix.dtsi b/arch/arm/dts/sun50i-h6-tanix.dtsi
new file mode 100644
index 0000000000..edb71e4a03
--- /dev/null
+++ b/arch/arm/dts/sun50i-h6-tanix.dtsi
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ /* used for FD650 LED display driver */
+ i2c {
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */
+ scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */
+ i2c-gpio,delay-us = <5>;
+ };
+
+ reg_vcc1v8: regulator-vcc1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_vcc3v3: regulator-vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd-cpu-gpu";
+ regulator-min-microvolt = <1135000>;
+ regulator-max-microvolt = <1135000>;
+ };
+
+ sound-spdif {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "sun50i-h6-spdif";
+
+ simple-audio-card,cpu {
+ sound-dai = <&spdif>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&spdif_out>;
+ };
+ };
+
+ spdif_out: spdif-out {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ };
+
+ wifi_pwrseq: wifi-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rtc 1>;
+ clock-names = "ext_clock";
+ reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vdd_cpu_gpu>;
+};
+
+&de {
+ status = "okay";
+};
+
+&dwc3 {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <®_vdd_cpu_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_vcc3v3>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc1v8>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
+
+&mmc2 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc1v8>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pc-supply = <®_vcc1v8>;
+ vcc-pd-supply = <®_vcc3v3>;
+ vcc-pg-supply = <®_vcc1v8>;
+};
+
+&r_ir {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ status = "okay";
+};
+
+&usb3phy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
index af8b7d0ef7..71a45a624d 100644
--- a/arch/arm/dts/sun50i-h6.dtsi
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -119,10 +119,10 @@
display_clocks: clock@0 {
compatible = "allwinner,sun50i-h6-de3-clk";
reg = <0x0 0x10000>;
- clocks = <&ccu CLK_DE>,
- <&ccu CLK_BUS_DE>;
- clock-names = "mod",
- "bus";
+ clocks = <&ccu CLK_BUS_DE>,
+ <&ccu CLK_DE>;
+ clock-names = "bus",
+ "mod";
resets = <&ccu RST_BUS_DE>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -153,6 +153,15 @@
};
};
+ video-codec-g2@1c00000 {
+ compatible = "allwinner,sun50i-h6-vpu-g2";
+ reg = <0x01c00000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_VP9>;
+ };
+
video-codec@1c0e000 {
compatible = "allwinner,sun50i-h6-video-engine";
reg = <0x01c0e000 0x2000>;
@@ -271,6 +280,15 @@
};
};
+ timer@3009000 {
+ compatible = "allwinner,sun50i-h6-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x03009000 0xa0>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
watchdog: watchdog@30090a0 {
compatible = "allwinner,sun50i-h6-wdt",
"allwinner,sun6i-a31-wdt";
--
2.35.1
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (11 preceding siblings ...)
2022-04-27 20:31 ` [PATCH 12/12] ARM: dts: sun50i: H6: " Samuel Holland
@ 2022-04-29 14:51 ` Andre Przywara
2022-04-29 14:57 ` Tom Rini
2022-05-24 15:58 ` Andre Przywara
13 siblings, 1 reply; 41+ messages in thread
From: Andre Przywara @ 2022-04-29 14:51 UTC (permalink / raw)
To: Samuel Holland, Tom Rini; +Cc: u-boot, Jagan Teki, Simon Glass
On Wed, 27 Apr 2022 15:31:19 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel, Tom,
> This series brings all of our devicetrees up to date with Linux.
>
> Older SoCs (before A83T) have not been synchronized in over 3 years.
> And I don't have any of this hardware to test. But there are not major
> changes to those devicetrees either.
>
> The big motivation for including older SoCs in this update is converting
> the USB PHY driver to get its VBUS detection GPIO/regulator from the
> devicetree instead of from a pin name in Kconfig. Many older boards had
> those properties added or fixed since the last devicetree sync. This PHY
> driver change is necessary to complete the DM_GPIO migration.
>
> A couple of breaking changes were made to several SoCs' devicetrees in
> Linux relating to the "r_intc" interrupt controller. New kernels support
> old devicetrees, but not the other way around. So to be most compatible
> and avoid regressions, those changes are skipped here.
Many thanks for considering this! I just skimmed over the A64 and H6
patches, and this is indeed the only difference.
But while I love this pragmatic approach, and would be happy to take this,
this goes against our own rules, and more importantly against Tom's one's:
to take only direct DT file copies from the kernel tree.
Tom, can you give your opinion here? As Samuel mentioned above, the
current mainline DTs wouldn't boot on older kernels (the changes affect
critical devices), so this spoils stable distro and installer kernels,
when using $fdtcontroladdr, for instance when booting via UEFI.
As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
For context, those changed properties were in the mainline kernel tree at
some point, but have been amended since. So it's not some random change.
Cheers,
Andre
> Samuel Holland (12):
> dt-bindings: sunxi: Update clock/reset binding headers
> ARM: dts: sunxi: Remove unused devicetree headers
> ARM: dts: sun4i: Sync from Linux v5.18-rc1
> ARM: dts: sun7i: Sync from Linux v5.18-rc1
> ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1
> ARM: dts: sun9i: Sync from Linux v5.18-rc1
> ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1
> ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1
> ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1
> ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1
> ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1
> ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1
>
> arch/arm/dts/Makefile | 25 +-
> arch/arm/dts/axp209.dtsi | 6 +-
> arch/arm/dts/axp22x.dtsi | 11 +-
> arch/arm/dts/axp803.dtsi | 10 +-
> arch/arm/dts/axp81x.dtsi | 15 +-
> arch/arm/dts/sun4i-a10-a1000.dts | 31 +-
> arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
> arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 20 +-
> arch/arm/dts/sun4i-a10-cubieboard.dts | 16 +-
> arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 21 +-
> arch/arm/dts/sun4i-a10-hackberry.dts | 2 +-
> arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 20 +-
> arch/arm/dts/sun4i-a10-inet1.dts | 21 +-
> arch/arm/dts/sun4i-a10-inet97fv2.dts | 22 +-
> arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 74 ++--
> .../dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +-
> arch/arm/dts/sun4i-a10-jesurun-q5.dts | 4 +-
> arch/arm/dts/sun4i-a10-marsboard.dts | 22 +-
> arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 33 +-
> arch/arm/dts/sun4i-a10-pcduino.dts | 20 +-
> arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 21 +-
> arch/arm/dts/sun4i-a10-topwise-a721.dts | 242 +++++++++++++
> arch/arm/dts/sun4i-a10.dtsi | 135 ++++++-
> arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-a64-orangepi-win.dts | 2 +-
> arch/arm/dts/sun50i-a64-pinebook.dts | 1 +
> arch/arm/dts/sun50i-a64-pinephone.dtsi | 27 ++
> arch/arm/dts/sun50i-a64-pinetab.dts | 29 +-
> arch/arm/dts/sun50i-a64-teres-i.dts | 4 +-
> arch/arm/dts/sun50i-a64.dtsi | 93 +++--
> arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +-
> arch/arm/dts/sun50i-h5.dtsi | 6 +-
> arch/arm/dts/sun50i-h6-beelink-gs1.dts | 38 +-
> arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-h6-orangepi-3.dts | 14 +-
> arch/arm/dts/sun50i-h6-orangepi.dtsi | 22 +-
> arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 51 +++
> arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts | 15 +
> arch/arm/dts/sun50i-h6-tanix-tx6.dts | 115 +-----
> arch/arm/dts/sun50i-h6-tanix.dtsi | 189 ++++++++++
> arch/arm/dts/sun50i-h6.dtsi | 26 +-
> arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 16 +-
> arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 35 +-
> arch/arm/dts/sun5i-a10s-mk802.dts | 31 +-
> arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 68 +---
> arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +-
> arch/arm/dts/sun5i-a10s-wobo-i5.dts | 34 +-
> arch/arm/dts/sun5i-a10s.dtsi | 30 +-
> arch/arm/dts/sun5i-a13-ampe-a76.dts | 2 +-
> .../dts/sun5i-a13-empire-electronix-d709.dts | 41 +--
> arch/arm/dts/sun5i-a13-hsg-h702.dts | 37 +-
> arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +-
> ...common.dtsi => sun5i-a13-licheepi-one.dts} | 146 +++++---
> arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 50 +--
> arch/arm/dts/sun5i-a13-olinuxino.dts | 56 +--
> .../dts/sun5i-a13-pocketbook-touch-lux-3.dts | 258 ++++++++++++++
> arch/arm/dts/sun5i-a13-q8-tablet.dts | 18 +-
> arch/arm/dts/sun5i-a13-utoo-p66.dts | 26 +-
> arch/arm/dts/sun5i-a13.dtsi | 23 +-
> arch/arm/dts/sun5i-gr8-chip-pro.dts | 38 +-
> arch/arm/dts/sun5i-gr8-evb.dts | 333 ++++++++++++++++++
> arch/arm/dts/sun5i-gr8.dtsi | 12 +-
> arch/arm/dts/sun5i-r8-chip.dts | 52 +--
> .../dts/sun5i-reference-design-tablet.dtsi | 57 +--
> arch/arm/dts/sun5i.dtsi | 209 +++++++----
> arch/arm/dts/sun6i-a31-app4-evb1.dts | 10 +-
> arch/arm/dts/sun6i-a31-colombus.dts | 57 +--
> arch/arm/dts/sun6i-a31-hummingbird.dts | 75 +---
> arch/arm/dts/sun6i-a31-i7.dts | 47 +--
> arch/arm/dts/sun6i-a31-m9.dts | 46 +--
> arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts | 46 +--
> arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 6 +-
> arch/arm/dts/sun6i-a31.dtsi | 218 +++++++-----
> arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts | 2 +-
> arch/arm/dts/sun6i-a31s-cs908.dts | 17 +-
> arch/arm/dts/sun6i-a31s-inet-q972.dts | 8 +-
> arch/arm/dts/sun6i-a31s-primo81.dts | 32 +-
> arch/arm/dts/sun6i-a31s-sina31s-core.dtsi | 4 +-
> arch/arm/dts/sun6i-a31s-sina31s.dts | 39 +-
> arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 144 +++++---
> .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 22 +-
> .../dts/sun6i-reference-design-tablet.dtsi | 22 +-
> arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 16 +-
> arch/arm/dts/sun7i-a20-bananapi.dts | 41 +--
> arch/arm/dts/sun7i-a20-bananapro.dts | 16 +-
> arch/arm/dts/sun7i-a20-cubieboard2.dts | 28 +-
> arch/arm/dts/sun7i-a20-cubietruck.dts | 20 +-
> arch/arm/dts/sun7i-a20-haoyu-marsboard.dts | 182 ++++++++++
> arch/arm/dts/sun7i-a20-hummingbird.dts | 21 +-
> arch/arm/dts/sun7i-a20-i12-tvbox.dts | 16 +-
> arch/arm/dts/sun7i-a20-icnova-swac.dts | 15 +-
> arch/arm/dts/sun7i-a20-itead-ibox.dts | 8 +-
> arch/arm/dts/sun7i-a20-lamobo-r1.dts | 16 +-
> .../dts/sun7i-a20-linutronix-testbox-v2.dts | 47 +++
> arch/arm/dts/sun7i-a20-m3.dts | 14 +-
> arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 14 +-
> arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 30 +-
> .../arm/dts/sun7i-a20-olinuxino-lime-emmc.dts | 32 ++
> arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 32 +-
> arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 46 +--
> arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 32 +-
> arch/arm/dts/sun7i-a20-orangepi-mini.dts | 28 +-
> arch/arm/dts/sun7i-a20-orangepi.dts | 26 +-
> arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 32 +-
> arch/arm/dts/sun7i-a20-pcduino3.dts | 28 +-
> arch/arm/dts/sun7i-a20-wexler-tab7200.dts | 13 +-
> arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts | 24 +-
> arch/arm/dts/sun7i-a20.dtsi | 254 +++++++++++--
> arch/arm/dts/sun8i-a23-a33.dtsi | 308 ++++++++++++----
> arch/arm/dts/sun8i-a23-evb.dts | 20 +-
> arch/arm/dts/sun8i-a23-gt90h-v4.dts | 2 +-
> ...ommon.dtsi => sun8i-a23-ippo-q8h-v1.2.dts} | 54 ++-
> arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts | 73 ++++
> .../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 15 +-
> .../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 15 +-
> arch/arm/dts/sun8i-a23-q8-tablet.dts | 10 +
> arch/arm/dts/sun8i-a23.dtsi | 26 +-
> ...c-edition.dts => sun8i-a33-et-q8-v1.6.dts} | 32 +-
> arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 4 +-
> arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 14 +-
> arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts | 57 +++
> arch/arm/dts/sun8i-a33-olinuxino.dts | 12 +-
> arch/arm/dts/sun8i-a33-q8-tablet.dts | 7 +
> arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 34 +-
> arch/arm/dts/sun8i-a33.dtsi | 270 +++++---------
> .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 +
> arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 55 ++-
> arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 77 +++-
> arch/arm/dts/sun8i-a83t-tbs-a711.dts | 101 +++++-
> arch/arm/dts/sun8i-a83t.dtsi | 311 ++++++++++++++--
> .../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 28 +-
> arch/arm/dts/sun8i-h3-beelink-x2.dts | 27 +-
> arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 28 ++
> arch/arm/dts/sun8i-h3-nanopi-r1.dts | 169 +++++++++
> arch/arm/dts/sun8i-h3-nanopi.dtsi | 1 +
> arch/arm/dts/sun8i-h3-orangepi-2.dts | 3 +-
> arch/arm/dts/sun8i-h3-orangepi-pc.dts | 3 +-
> arch/arm/dts/sun8i-h3.dtsi | 10 +-
> arch/arm/dts/sun8i-q8-common.dtsi | 31 +-
> arch/arm/dts/sun8i-r16-bananapi-m2m.dts | 55 ++-
> .../dts/sun8i-r16-nintendo-nes-classic.dts | 54 +++
> .../sun8i-r16-nintendo-super-nes-classic.dts | 11 +
> arch/arm/dts/sun8i-r16-parrot.dts | 62 +---
> arch/arm/dts/sun8i-r40-feta40i.dtsi | 106 ++++++
> arch/arm/dts/sun8i-r40-oka40i-c.dts | 203 +++++++++++
> arch/arm/dts/sun8i-r40.dtsi | 118 ++++++-
> .../dts/sun8i-reference-design-tablet.dtsi | 33 +-
> arch/arm/dts/sun8i-s3-elimo-impetus.dtsi | 44 +++
> arch/arm/dts/sun8i-s3-elimo-initium.dts | 29 ++
> arch/arm/dts/sun8i-s3-pinecube.dts | 13 +-
> arch/arm/dts/sun8i-t3-cqa3t-bv3.dts | 226 ++++++++++++
> arch/arm/dts/sun8i-v3-sl631-imx179.dts | 12 +
> arch/arm/dts/sun8i-v3-sl631.dtsi | 138 ++++++++
> arch/arm/dts/sun8i-v3.dtsi | 36 ++
> arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 17 +-
> arch/arm/dts/sun8i-v3s.dtsi | 93 ++++-
> arch/arm/dts/sun9i-a80-cubieboard4.dts | 67 +++-
> arch/arm/dts/sun9i-a80-optimus.dts | 50 ++-
> arch/arm/dts/sun9i-a80.dtsi | 195 ++++++----
> arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 18 +-
> arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 4 +-
> arch/arm/dts/sunxi-common-regulators.dtsi | 39 --
> arch/arm/dts/sunxi-h3-h5.dtsi | 42 ++-
> arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 13 +
> arch/arm/dts/sunxi-libretech-all-h3-it.dtsi | 2 +-
> .../dts/sunxi-reference-design-tablet.dtsi | 11 +-
> arch/arm/mach-sunxi/Kconfig | 2 +-
> .../Nintendo_NES_Classic_Edition_defconfig | 2 +-
> include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +-
> include/dt-bindings/clock/sun5i-ccu.h | 13 +-
> include/dt-bindings/clock/sun6i-a31-ccu.h | 2 +
> include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 2 +
> include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +-
> include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
> include/dt-bindings/reset/sun5i-ccu.h | 11 +-
> include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
> 177 files changed, 5704 insertions(+), 2683 deletions(-)
> create mode 100644 arch/arm/dts/sun4i-a10-topwise-a721.dts
> create mode 100644 arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
> create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
> create mode 100644 arch/arm/dts/sun50i-h6-tanix.dtsi
> rename arch/arm/dts/{sun5i-q8-common.dtsi => sun5i-a13-licheepi-one.dts} (62%)
> create mode 100644 arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts
> create mode 100644 arch/arm/dts/sun5i-gr8-evb.dts
> create mode 100644 arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
> create mode 100644 arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
> create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
> rename arch/arm/dts/{sunxi-q8-common.dtsi => sun8i-a23-ippo-q8h-v1.2.dts} (75%)
> create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
> rename arch/arm/dts/{sun8i-r16-nintendo-nes-classic-edition.dts => sun8i-a33-et-q8-v1.6.dts} (81%)
> create mode 100644 arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
> create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
> create mode 100644 arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts
> create mode 100644 arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
> create mode 100644 arch/arm/dts/sun8i-r40-feta40i.dtsi
> create mode 100644 arch/arm/dts/sun8i-r40-oka40i-c.dts
> create mode 100644 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
> create mode 100644 arch/arm/dts/sun8i-s3-elimo-initium.dts
> create mode 100644 arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
> create mode 100644 arch/arm/dts/sun8i-v3-sl631-imx179.dts
> create mode 100644 arch/arm/dts/sun8i-v3-sl631.dtsi
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 14:51 ` [PATCH 00/12] sunxi: Devicetree sync " Andre Przywara
@ 2022-04-29 14:57 ` Tom Rini
2022-04-29 15:25 ` Andre Przywara
0 siblings, 1 reply; 41+ messages in thread
From: Tom Rini @ 2022-04-29 14:57 UTC (permalink / raw)
To: Andre Przywara; +Cc: Samuel Holland, u-boot, Jagan Teki, Simon Glass
[-- Attachment #1: Type: text/plain, Size: 2560 bytes --]
On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> On Wed, 27 Apr 2022 15:31:19 -0500
> Samuel Holland <samuel@sholland.org> wrote:
>
> Hi Samuel, Tom,
>
> > This series brings all of our devicetrees up to date with Linux.
> >
> > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > And I don't have any of this hardware to test. But there are not major
> > changes to those devicetrees either.
> >
> > The big motivation for including older SoCs in this update is converting
> > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > devicetree instead of from a pin name in Kconfig. Many older boards had
> > those properties added or fixed since the last devicetree sync. This PHY
> > driver change is necessary to complete the DM_GPIO migration.
> >
> > A couple of breaking changes were made to several SoCs' devicetrees in
> > Linux relating to the "r_intc" interrupt controller. New kernels support
> > old devicetrees, but not the other way around. So to be most compatible
> > and avoid regressions, those changes are skipped here.
>
> Many thanks for considering this! I just skimmed over the A64 and H6
> patches, and this is indeed the only difference.
>
> But while I love this pragmatic approach, and would be happy to take this,
> this goes against our own rules, and more importantly against Tom's one's:
> to take only direct DT file copies from the kernel tree.
>
> Tom, can you give your opinion here? As Samuel mentioned above, the
> current mainline DTs wouldn't boot on older kernels (the changes affect
> critical devices), so this spoils stable distro and installer kernels,
> when using $fdtcontroladdr, for instance when booting via UEFI.
>
> As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
>
> For context, those changed properties were in the mainline kernel tree at
> some point, but have been amended since. So it's not some random change.
So, this is I guess a bit annoying. But, we aren't at the point where
the common use case is the downstream OS using the DTB we've loaded and
are using, are we? I mean, we can't be, as ours are so far out of date,
so this will only be an option when we use a recent DT ourself. So we
should be able to sync in the changes and update our code, as they can't
be using $fdtcontroladdr in this case, right? Or am I missing the use
case that's in the wild atm? Thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 14:57 ` Tom Rini
@ 2022-04-29 15:25 ` Andre Przywara
2022-04-29 15:31 ` Tom Rini
0 siblings, 1 reply; 41+ messages in thread
From: Andre Przywara @ 2022-04-29 15:25 UTC (permalink / raw)
To: Tom Rini; +Cc: Samuel Holland, u-boot, Jagan Teki, Simon Glass
On Fri, 29 Apr 2022 10:57:10 -0400
Tom Rini <trini@konsulko.com> wrote:
Hi,
> On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > On Wed, 27 Apr 2022 15:31:19 -0500
> > Samuel Holland <samuel@sholland.org> wrote:
> >
> > Hi Samuel, Tom,
> >
> > > This series brings all of our devicetrees up to date with Linux.
> > >
> > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > And I don't have any of this hardware to test. But there are not major
> > > changes to those devicetrees either.
> > >
> > > The big motivation for including older SoCs in this update is converting
> > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > those properties added or fixed since the last devicetree sync. This PHY
> > > driver change is necessary to complete the DM_GPIO migration.
> > >
> > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > old devicetrees, but not the other way around. So to be most compatible
> > > and avoid regressions, those changes are skipped here.
> >
> > Many thanks for considering this! I just skimmed over the A64 and H6
> > patches, and this is indeed the only difference.
> >
> > But while I love this pragmatic approach, and would be happy to take this,
> > this goes against our own rules, and more importantly against Tom's one's:
> > to take only direct DT file copies from the kernel tree.
> >
> > Tom, can you give your opinion here? As Samuel mentioned above, the
> > current mainline DTs wouldn't boot on older kernels (the changes affect
> > critical devices), so this spoils stable distro and installer kernels,
> > when using $fdtcontroladdr, for instance when booting via UEFI.
> >
> > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> >
> > For context, those changed properties were in the mainline kernel tree at
> > some point, but have been amended since. So it's not some random change.
>
> So, this is I guess a bit annoying. But, we aren't at the point where
> the common use case is the downstream OS using the DTB we've loaded and
> are using, are we? I mean, we can't be, as ours are so far out of date,
> so this will only be an option when we use a recent DT ourself. So we
> should be able to sync in the changes and update our code, as they can't
> be using $fdtcontroladdr in this case, right? Or am I missing the use
> case that's in the wild atm? Thanks!
While it sounds like the DTs are wildly out of date, this mostly affects
secondary functionality. The mainline updates for the 64-bit SoCs are:
- H6: adding the VP9 video h/w codec and an additional wakeup timer
- A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
digital audio interfaces, plus the wakeup timer
Also there are cosmetic changes, like changing node names to make them
binding compliant.
So those DT updates are really only important for mobile devices like the
Pinephone, which probably don't use UEFI booting.
At the moment I boot distro grubs and installers just fine, and without
losing any real functionality (minus suspend/resume, maybe). The
out-of-the-box default boot works now, and would break when pulling in the
pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
Cheers,
Andre
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 15:25 ` Andre Przywara
@ 2022-04-29 15:31 ` Tom Rini
2022-04-29 15:57 ` Andre Przywara
2022-04-29 16:05 ` Mark Kettenis
0 siblings, 2 replies; 41+ messages in thread
From: Tom Rini @ 2022-04-29 15:31 UTC (permalink / raw)
To: Andre Przywara, Rob Herring
Cc: Samuel Holland, u-boot, Jagan Teki, Simon Glass
[-- Attachment #1: Type: text/plain, Size: 4376 bytes --]
On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> On Fri, 29 Apr 2022 10:57:10 -0400
> Tom Rini <trini@konsulko.com> wrote:
>
> Hi,
>
> > On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > > On Wed, 27 Apr 2022 15:31:19 -0500
> > > Samuel Holland <samuel@sholland.org> wrote:
> > >
> > > Hi Samuel, Tom,
> > >
> > > > This series brings all of our devicetrees up to date with Linux.
> > > >
> > > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > > And I don't have any of this hardware to test. But there are not major
> > > > changes to those devicetrees either.
> > > >
> > > > The big motivation for including older SoCs in this update is converting
> > > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > > those properties added or fixed since the last devicetree sync. This PHY
> > > > driver change is necessary to complete the DM_GPIO migration.
> > > >
> > > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > > old devicetrees, but not the other way around. So to be most compatible
> > > > and avoid regressions, those changes are skipped here.
> > >
> > > Many thanks for considering this! I just skimmed over the A64 and H6
> > > patches, and this is indeed the only difference.
> > >
> > > But while I love this pragmatic approach, and would be happy to take this,
> > > this goes against our own rules, and more importantly against Tom's one's:
> > > to take only direct DT file copies from the kernel tree.
> > >
> > > Tom, can you give your opinion here? As Samuel mentioned above, the
> > > current mainline DTs wouldn't boot on older kernels (the changes affect
> > > critical devices), so this spoils stable distro and installer kernels,
> > > when using $fdtcontroladdr, for instance when booting via UEFI.
> > >
> > > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > >
> > > For context, those changed properties were in the mainline kernel tree at
> > > some point, but have been amended since. So it's not some random change.
> >
> > So, this is I guess a bit annoying. But, we aren't at the point where
> > the common use case is the downstream OS using the DTB we've loaded and
> > are using, are we? I mean, we can't be, as ours are so far out of date,
> > so this will only be an option when we use a recent DT ourself. So we
> > should be able to sync in the changes and update our code, as they can't
> > be using $fdtcontroladdr in this case, right? Or am I missing the use
> > case that's in the wild atm? Thanks!
>
> While it sounds like the DTs are wildly out of date, this mostly affects
> secondary functionality. The mainline updates for the 64-bit SoCs are:
> - H6: adding the VP9 video h/w codec and an additional wakeup timer
> - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> digital audio interfaces, plus the wakeup timer
> Also there are cosmetic changes, like changing node names to make them
> binding compliant.
> So those DT updates are really only important for mobile devices like the
> Pinephone, which probably don't use UEFI booting.
>
> At the moment I boot distro grubs and installers just fine, and without
> losing any real functionality (minus suspend/resume, maybe). The
> out-of-the-box default boot works now, and would break when pulling in the
> pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
I guess the first point is, yes, we should sync in what we can sync in,
to bring things closer to proper alignment. I further guess that given
that we have to support both "new Linux" and "not Linux", we have to
keep the old style DT information instead as that's how compatibility is
supposed to be handled? I'm adding in Rob here since this still reads a
bit confusing as to what's supposed to happen, but maybe we also just
need to check in with some other-OS folks to see what their plan is?
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 15:31 ` Tom Rini
@ 2022-04-29 15:57 ` Andre Przywara
2022-04-29 16:05 ` Mark Kettenis
1 sibling, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-04-29 15:57 UTC (permalink / raw)
To: Tom Rini; +Cc: Rob Herring, Samuel Holland, u-boot, Jagan Teki, Simon Glass
On Fri, 29 Apr 2022 11:31:00 -0400
Tom Rini <trini@konsulko.com> wrote:
Hi,
> On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> > On Fri, 29 Apr 2022 10:57:10 -0400
> > Tom Rini <trini@konsulko.com> wrote:
> >
> > Hi,
> >
> > > On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > > > On Wed, 27 Apr 2022 15:31:19 -0500
> > > > Samuel Holland <samuel@sholland.org> wrote:
> > > >
> > > > Hi Samuel, Tom,
> > > >
> > > > > This series brings all of our devicetrees up to date with Linux.
> > > > >
> > > > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > > > And I don't have any of this hardware to test. But there are not major
> > > > > changes to those devicetrees either.
> > > > >
> > > > > The big motivation for including older SoCs in this update is converting
> > > > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > > > those properties added or fixed since the last devicetree sync. This PHY
> > > > > driver change is necessary to complete the DM_GPIO migration.
> > > > >
> > > > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > > > old devicetrees, but not the other way around. So to be most compatible
> > > > > and avoid regressions, those changes are skipped here.
> > > >
> > > > Many thanks for considering this! I just skimmed over the A64 and H6
> > > > patches, and this is indeed the only difference.
> > > >
> > > > But while I love this pragmatic approach, and would be happy to take this,
> > > > this goes against our own rules, and more importantly against Tom's one's:
> > > > to take only direct DT file copies from the kernel tree.
> > > >
> > > > Tom, can you give your opinion here? As Samuel mentioned above, the
> > > > current mainline DTs wouldn't boot on older kernels (the changes affect
> > > > critical devices), so this spoils stable distro and installer kernels,
> > > > when using $fdtcontroladdr, for instance when booting via UEFI.
> > > >
> > > > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > > > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > > >
> > > > For context, those changed properties were in the mainline kernel tree at
> > > > some point, but have been amended since. So it's not some random change.
> > >
> > > So, this is I guess a bit annoying. But, we aren't at the point where
> > > the common use case is the downstream OS using the DTB we've loaded and
> > > are using, are we? I mean, we can't be, as ours are so far out of date,
> > > so this will only be an option when we use a recent DT ourself. So we
> > > should be able to sync in the changes and update our code, as they can't
> > > be using $fdtcontroladdr in this case, right? Or am I missing the use
> > > case that's in the wild atm? Thanks!
> >
> > While it sounds like the DTs are wildly out of date, this mostly affects
> > secondary functionality. The mainline updates for the 64-bit SoCs are:
> > - H6: adding the VP9 video h/w codec and an additional wakeup timer
> > - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> > digital audio interfaces, plus the wakeup timer
> > Also there are cosmetic changes, like changing node names to make them
> > binding compliant.
> > So those DT updates are really only important for mobile devices like the
> > Pinephone, which probably don't use UEFI booting.
> >
> > At the moment I boot distro grubs and installers just fine, and without
> > losing any real functionality (minus suspend/resume, maybe). The
> > out-of-the-box default boot works now, and would break when pulling in the
> > pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> > can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
>
> I guess the first point is, yes, we should sync in what we can sync in,
> to bring things closer to proper alignment. I further guess that given
> that we have to support both "new Linux" and "not Linux", we have to
> keep the old style DT information instead as that's how compatibility is
> supposed to be handled? I'm adding in Rob here since this still reads a
> bit confusing as to what's supposed to happen, but maybe we also just
> need to check in with some other-OS folks to see what their plan is?
AFAIK, the official Linux DT compatibility requirements are to always keep
backwards compatibility (boot newer kernels with older DTs), but leave the
decision to support the other way around (older kernels with newer DTs) to
the respective platform maintainers.
At least in the past sunxi opted to allow non-forward compatible changes
(this r_intc one being an example of), with the rationale that without
proper documentation and with doing "retroactive" development, incompatible
changes are unavoidable, or would require more work than those volunteers
are willing to do.
Those incompatible changes (there were some more, though minor in the
past) are the reason I (grudgingly) held back with DT updates for U-Boot,
so I would very much appreciate if that situation could be cleared up.
As mentioned, I would be happy to take the changed DTs, and would
volunteer to keep those diffs somehow maintained in U-Boot.
Cheers,
Andre
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 15:31 ` Tom Rini
2022-04-29 15:57 ` Andre Przywara
@ 2022-04-29 16:05 ` Mark Kettenis
2022-04-29 18:14 ` Tom Rini
1 sibling, 1 reply; 41+ messages in thread
From: Mark Kettenis @ 2022-04-29 16:05 UTC (permalink / raw)
To: Tom Rini; +Cc: andre.przywara, robh, samuel, u-boot, jagan, sjg
> Date: Fri, 29 Apr 2022 11:31:00 -0400
> From: Tom Rini <trini@konsulko.com>
>
> On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> > On Fri, 29 Apr 2022 10:57:10 -0400
> > Tom Rini <trini@konsulko.com> wrote:
> >
> > Hi,
> >
> > > On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > > > On Wed, 27 Apr 2022 15:31:19 -0500
> > > > Samuel Holland <samuel@sholland.org> wrote:
> > > >
> > > > Hi Samuel, Tom,
> > > >
> > > > > This series brings all of our devicetrees up to date with Linux.
> > > > >
> > > > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > > > And I don't have any of this hardware to test. But there are not major
> > > > > changes to those devicetrees either.
> > > > >
> > > > > The big motivation for including older SoCs in this update is converting
> > > > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > > > those properties added or fixed since the last devicetree sync. This PHY
> > > > > driver change is necessary to complete the DM_GPIO migration.
> > > > >
> > > > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > > > old devicetrees, but not the other way around. So to be most compatible
> > > > > and avoid regressions, those changes are skipped here.
> > > >
> > > > Many thanks for considering this! I just skimmed over the A64 and H6
> > > > patches, and this is indeed the only difference.
> > > >
> > > > But while I love this pragmatic approach, and would be happy to take this,
> > > > this goes against our own rules, and more importantly against Tom's one's:
> > > > to take only direct DT file copies from the kernel tree.
> > > >
> > > > Tom, can you give your opinion here? As Samuel mentioned above, the
> > > > current mainline DTs wouldn't boot on older kernels (the changes affect
> > > > critical devices), so this spoils stable distro and installer kernels,
> > > > when using $fdtcontroladdr, for instance when booting via UEFI.
> > > >
> > > > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > > > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > > >
> > > > For context, those changed properties were in the mainline kernel tree at
> > > > some point, but have been amended since. So it's not some random change.
> > >
> > > So, this is I guess a bit annoying. But, we aren't at the point where
> > > the common use case is the downstream OS using the DTB we've loaded and
> > > are using, are we? I mean, we can't be, as ours are so far out of date,
> > > so this will only be an option when we use a recent DT ourself. So we
> > > should be able to sync in the changes and update our code, as they can't
> > > be using $fdtcontroladdr in this case, right? Or am I missing the use
> > > case that's in the wild atm? Thanks!
> >
> > While it sounds like the DTs are wildly out of date, this mostly affects
> > secondary functionality. The mainline updates for the 64-bit SoCs are:
> > - H6: adding the VP9 video h/w codec and an additional wakeup timer
> > - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> > digital audio interfaces, plus the wakeup timer
> > Also there are cosmetic changes, like changing node names to make them
> > binding compliant.
> > So those DT updates are really only important for mobile devices like the
> > Pinephone, which probably don't use UEFI booting.
> >
> > At the moment I boot distro grubs and installers just fine, and without
> > losing any real functionality (minus suspend/resume, maybe). The
> > out-of-the-box default boot works now, and would break when pulling in the
> > pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> > can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
>
> I guess the first point is, yes, we should sync in what we can sync in,
> to bring things closer to proper alignment. I further guess that given
> that we have to support both "new Linux" and "not Linux", we have to
> keep the old style DT information instead as that's how compatibility is
> supposed to be handled? I'm adding in Rob here since this still reads a
> bit confusing as to what's supposed to happen, but maybe we also just
> need to check in with some other-OS folks to see what their plan is?
My goal with OpenBSD has always been to make the OS boot with the DT
built into U-Boot, but to allow users to use a more up-to-date Linux
DT by putting the apropriate .dtb file on the ESP. However it is easy
to miss changes that break backwards compatibility of the bindings in
the noise of other changes. So in many cases we only notice this when
the changes make it into U-Boot and we update the OpenBSD U-Boot port.
I'll drag out one of my A64 boards and see what needs to be done to
support the routing of these interrupts through r_intc.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 16:05 ` Mark Kettenis
@ 2022-04-29 18:14 ` Tom Rini
2022-04-29 18:21 ` Mark Kettenis
2022-04-30 0:08 ` Andre Przywara
0 siblings, 2 replies; 41+ messages in thread
From: Tom Rini @ 2022-04-29 18:14 UTC (permalink / raw)
To: Mark Kettenis; +Cc: andre.przywara, robh, samuel, u-boot, jagan, sjg
[-- Attachment #1: Type: text/plain, Size: 5580 bytes --]
On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
> > Date: Fri, 29 Apr 2022 11:31:00 -0400
> > From: Tom Rini <trini@konsulko.com>
> >
> > On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> > > On Fri, 29 Apr 2022 10:57:10 -0400
> > > Tom Rini <trini@konsulko.com> wrote:
> > >
> > > Hi,
> > >
> > > > On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > > > > On Wed, 27 Apr 2022 15:31:19 -0500
> > > > > Samuel Holland <samuel@sholland.org> wrote:
> > > > >
> > > > > Hi Samuel, Tom,
> > > > >
> > > > > > This series brings all of our devicetrees up to date with Linux.
> > > > > >
> > > > > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > > > > And I don't have any of this hardware to test. But there are not major
> > > > > > changes to those devicetrees either.
> > > > > >
> > > > > > The big motivation for including older SoCs in this update is converting
> > > > > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > > > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > > > > those properties added or fixed since the last devicetree sync. This PHY
> > > > > > driver change is necessary to complete the DM_GPIO migration.
> > > > > >
> > > > > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > > > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > > > > old devicetrees, but not the other way around. So to be most compatible
> > > > > > and avoid regressions, those changes are skipped here.
> > > > >
> > > > > Many thanks for considering this! I just skimmed over the A64 and H6
> > > > > patches, and this is indeed the only difference.
> > > > >
> > > > > But while I love this pragmatic approach, and would be happy to take this,
> > > > > this goes against our own rules, and more importantly against Tom's one's:
> > > > > to take only direct DT file copies from the kernel tree.
> > > > >
> > > > > Tom, can you give your opinion here? As Samuel mentioned above, the
> > > > > current mainline DTs wouldn't boot on older kernels (the changes affect
> > > > > critical devices), so this spoils stable distro and installer kernels,
> > > > > when using $fdtcontroladdr, for instance when booting via UEFI.
> > > > >
> > > > > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > > > > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > > > >
> > > > > For context, those changed properties were in the mainline kernel tree at
> > > > > some point, but have been amended since. So it's not some random change.
> > > >
> > > > So, this is I guess a bit annoying. But, we aren't at the point where
> > > > the common use case is the downstream OS using the DTB we've loaded and
> > > > are using, are we? I mean, we can't be, as ours are so far out of date,
> > > > so this will only be an option when we use a recent DT ourself. So we
> > > > should be able to sync in the changes and update our code, as they can't
> > > > be using $fdtcontroladdr in this case, right? Or am I missing the use
> > > > case that's in the wild atm? Thanks!
> > >
> > > While it sounds like the DTs are wildly out of date, this mostly affects
> > > secondary functionality. The mainline updates for the 64-bit SoCs are:
> > > - H6: adding the VP9 video h/w codec and an additional wakeup timer
> > > - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> > > digital audio interfaces, plus the wakeup timer
> > > Also there are cosmetic changes, like changing node names to make them
> > > binding compliant.
> > > So those DT updates are really only important for mobile devices like the
> > > Pinephone, which probably don't use UEFI booting.
> > >
> > > At the moment I boot distro grubs and installers just fine, and without
> > > losing any real functionality (minus suspend/resume, maybe). The
> > > out-of-the-box default boot works now, and would break when pulling in the
> > > pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> > > can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
> >
> > I guess the first point is, yes, we should sync in what we can sync in,
> > to bring things closer to proper alignment. I further guess that given
> > that we have to support both "new Linux" and "not Linux", we have to
> > keep the old style DT information instead as that's how compatibility is
> > supposed to be handled? I'm adding in Rob here since this still reads a
> > bit confusing as to what's supposed to happen, but maybe we also just
> > need to check in with some other-OS folks to see what their plan is?
>
> My goal with OpenBSD has always been to make the OS boot with the DT
> built into U-Boot, but to allow users to use a more up-to-date Linux
> DT by putting the apropriate .dtb file on the ESP. However it is easy
> to miss changes that break backwards compatibility of the bindings in
> the noise of other changes. So in many cases we only notice this when
> the changes make it into U-Boot and we update the OpenBSD U-Boot port.
>
> I'll drag out one of my A64 boards and see what needs to be done to
> support the routing of these interrupts through r_intc.
So, does that mean the plan is to keep the r_intc changes out of U-Boot
for now, but we can sync the rest, and come up with a plan to fully
update in time?
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 18:14 ` Tom Rini
@ 2022-04-29 18:21 ` Mark Kettenis
2022-04-30 0:08 ` Andre Przywara
1 sibling, 0 replies; 41+ messages in thread
From: Mark Kettenis @ 2022-04-29 18:21 UTC (permalink / raw)
To: Tom Rini; +Cc: andre.przywara, robh, samuel, u-boot, jagan, sjg
> Date: Fri, 29 Apr 2022 14:14:19 -0400
> From: Tom Rini <trini@konsulko.com>
>
> On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
> > > Date: Fri, 29 Apr 2022 11:31:00 -0400
> > > From: Tom Rini <trini@konsulko.com>
> > >
> > > On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> > > > On Fri, 29 Apr 2022 10:57:10 -0400
> > > > Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > Hi,
> > > >
> > > > > On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > > > > > On Wed, 27 Apr 2022 15:31:19 -0500
> > > > > > Samuel Holland <samuel@sholland.org> wrote:
> > > > > >
> > > > > > Hi Samuel, Tom,
> > > > > >
> > > > > > > This series brings all of our devicetrees up to date with Linux.
> > > > > > >
> > > > > > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > > > > > And I don't have any of this hardware to test. But there are not major
> > > > > > > changes to those devicetrees either.
> > > > > > >
> > > > > > > The big motivation for including older SoCs in this update is converting
> > > > > > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > > > > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > > > > > those properties added or fixed since the last devicetree sync. This PHY
> > > > > > > driver change is necessary to complete the DM_GPIO migration.
> > > > > > >
> > > > > > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > > > > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > > > > > old devicetrees, but not the other way around. So to be most compatible
> > > > > > > and avoid regressions, those changes are skipped here.
> > > > > >
> > > > > > Many thanks for considering this! I just skimmed over the A64 and H6
> > > > > > patches, and this is indeed the only difference.
> > > > > >
> > > > > > But while I love this pragmatic approach, and would be happy to take this,
> > > > > > this goes against our own rules, and more importantly against Tom's one's:
> > > > > > to take only direct DT file copies from the kernel tree.
> > > > > >
> > > > > > Tom, can you give your opinion here? As Samuel mentioned above, the
> > > > > > current mainline DTs wouldn't boot on older kernels (the changes affect
> > > > > > critical devices), so this spoils stable distro and installer kernels,
> > > > > > when using $fdtcontroladdr, for instance when booting via UEFI.
> > > > > >
> > > > > > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > > > > > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > > > > >
> > > > > > For context, those changed properties were in the mainline kernel tree at
> > > > > > some point, but have been amended since. So it's not some random change.
> > > > >
> > > > > So, this is I guess a bit annoying. But, we aren't at the point where
> > > > > the common use case is the downstream OS using the DTB we've loaded and
> > > > > are using, are we? I mean, we can't be, as ours are so far out of date,
> > > > > so this will only be an option when we use a recent DT ourself. So we
> > > > > should be able to sync in the changes and update our code, as they can't
> > > > > be using $fdtcontroladdr in this case, right? Or am I missing the use
> > > > > case that's in the wild atm? Thanks!
> > > >
> > > > While it sounds like the DTs are wildly out of date, this mostly affects
> > > > secondary functionality. The mainline updates for the 64-bit SoCs are:
> > > > - H6: adding the VP9 video h/w codec and an additional wakeup timer
> > > > - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> > > > digital audio interfaces, plus the wakeup timer
> > > > Also there are cosmetic changes, like changing node names to make them
> > > > binding compliant.
> > > > So those DT updates are really only important for mobile devices like the
> > > > Pinephone, which probably don't use UEFI booting.
> > > >
> > > > At the moment I boot distro grubs and installers just fine, and without
> > > > losing any real functionality (minus suspend/resume, maybe). The
> > > > out-of-the-box default boot works now, and would break when pulling in the
> > > > pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> > > > can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
> > >
> > > I guess the first point is, yes, we should sync in what we can sync in,
> > > to bring things closer to proper alignment. I further guess that given
> > > that we have to support both "new Linux" and "not Linux", we have to
> > > keep the old style DT information instead as that's how compatibility is
> > > supposed to be handled? I'm adding in Rob here since this still reads a
> > > bit confusing as to what's supposed to happen, but maybe we also just
> > > need to check in with some other-OS folks to see what their plan is?
> >
> > My goal with OpenBSD has always been to make the OS boot with the DT
> > built into U-Boot, but to allow users to use a more up-to-date Linux
> > DT by putting the apropriate .dtb file on the ESP. However it is easy
> > to miss changes that break backwards compatibility of the bindings in
> > the noise of other changes. So in many cases we only notice this when
> > the changes make it into U-Boot and we update the OpenBSD U-Boot port.
> >
> > I'll drag out one of my A64 boards and see what needs to be done to
> > support the routing of these interrupts through r_intc.
>
> So, does that mean the plan is to keep the r_intc changes out of U-Boot
> for now, but we can sync the rest, and come up with a plan to fully
> update in time?
That would work for me.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-29 18:14 ` Tom Rini
2022-04-29 18:21 ` Mark Kettenis
@ 2022-04-30 0:08 ` Andre Przywara
2022-04-30 2:38 ` Samuel Holland
2022-05-01 16:25 ` Tom Rini
1 sibling, 2 replies; 41+ messages in thread
From: Andre Przywara @ 2022-04-30 0:08 UTC (permalink / raw)
To: Tom Rini; +Cc: Mark Kettenis, robh, samuel, u-boot, jagan, sjg
On Fri, 29 Apr 2022 14:14:19 -0400
Tom Rini <trini@konsulko.com> wrote:
Hi,
> On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
> > > Date: Fri, 29 Apr 2022 11:31:00 -0400
> > > From: Tom Rini <trini@konsulko.com>
> > >
> > > On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> > > > On Fri, 29 Apr 2022 10:57:10 -0400
> > > > Tom Rini <trini@konsulko.com> wrote:
> > > >
> > > > Hi,
> > > >
> > > > > On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > > > > > On Wed, 27 Apr 2022 15:31:19 -0500
> > > > > > Samuel Holland <samuel@sholland.org> wrote:
> > > > > >
> > > > > > Hi Samuel, Tom,
> > > > > >
> > > > > > > This series brings all of our devicetrees up to date with Linux.
> > > > > > >
> > > > > > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > > > > > And I don't have any of this hardware to test. But there are not major
> > > > > > > changes to those devicetrees either.
> > > > > > >
> > > > > > > The big motivation for including older SoCs in this update is converting
> > > > > > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > > > > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > > > > > those properties added or fixed since the last devicetree sync. This PHY
> > > > > > > driver change is necessary to complete the DM_GPIO migration.
> > > > > > >
> > > > > > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > > > > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > > > > > old devicetrees, but not the other way around. So to be most compatible
> > > > > > > and avoid regressions, those changes are skipped here.
> > > > > >
> > > > > > Many thanks for considering this! I just skimmed over the A64 and H6
> > > > > > patches, and this is indeed the only difference.
> > > > > >
> > > > > > But while I love this pragmatic approach, and would be happy to take this,
> > > > > > this goes against our own rules, and more importantly against Tom's one's:
> > > > > > to take only direct DT file copies from the kernel tree.
> > > > > >
> > > > > > Tom, can you give your opinion here? As Samuel mentioned above, the
> > > > > > current mainline DTs wouldn't boot on older kernels (the changes affect
> > > > > > critical devices), so this spoils stable distro and installer kernels,
> > > > > > when using $fdtcontroladdr, for instance when booting via UEFI.
> > > > > >
> > > > > > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > > > > > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > > > > >
> > > > > > For context, those changed properties were in the mainline kernel tree at
> > > > > > some point, but have been amended since. So it's not some random change.
> > > > >
> > > > > So, this is I guess a bit annoying. But, we aren't at the point where
> > > > > the common use case is the downstream OS using the DTB we've loaded and
> > > > > are using, are we? I mean, we can't be, as ours are so far out of date,
> > > > > so this will only be an option when we use a recent DT ourself. So we
> > > > > should be able to sync in the changes and update our code, as they can't
> > > > > be using $fdtcontroladdr in this case, right? Or am I missing the use
> > > > > case that's in the wild atm? Thanks!
> > > >
> > > > While it sounds like the DTs are wildly out of date, this mostly affects
> > > > secondary functionality. The mainline updates for the 64-bit SoCs are:
> > > > - H6: adding the VP9 video h/w codec and an additional wakeup timer
> > > > - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> > > > digital audio interfaces, plus the wakeup timer
> > > > Also there are cosmetic changes, like changing node names to make them
> > > > binding compliant.
> > > > So those DT updates are really only important for mobile devices like the
> > > > Pinephone, which probably don't use UEFI booting.
> > > >
> > > > At the moment I boot distro grubs and installers just fine, and without
> > > > losing any real functionality (minus suspend/resume, maybe). The
> > > > out-of-the-box default boot works now, and would break when pulling in the
> > > > pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> > > > can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
> > >
> > > I guess the first point is, yes, we should sync in what we can sync in,
> > > to bring things closer to proper alignment. I further guess that given
> > > that we have to support both "new Linux" and "not Linux", we have to
> > > keep the old style DT information instead as that's how compatibility is
> > > supposed to be handled? I'm adding in Rob here since this still reads a
> > > bit confusing as to what's supposed to happen, but maybe we also just
> > > need to check in with some other-OS folks to see what their plan is?
> >
> > My goal with OpenBSD has always been to make the OS boot with the DT
> > built into U-Boot, but to allow users to use a more up-to-date Linux
> > DT by putting the apropriate .dtb file on the ESP. However it is easy
> > to miss changes that break backwards compatibility of the bindings in
> > the noise of other changes. So in many cases we only notice this when
> > the changes make it into U-Boot and we update the OpenBSD U-Boot port.
> >
> > I'll drag out one of my A64 boards and see what needs to be done to
> > support the routing of these interrupts through r_intc.
In FreeBSD the change would be fairly small, I think: just ignoring the
first parameter of an r_intc interrupt specifier when it advertises
#interrupt-cells = <3>.
In OpenBSD I don't find the allwinner,sun6i-a31-r-intc (or any other
intc related) compatible string at all, and so far we just lose the NMI
from the PMIC. But this would radically change with the new DT: now the
two PIOs and the RTC are routed through that IRQ controller, so they
would probably fail probing.
> So, does that mean the plan is to keep the r_intc changes out of U-Boot
> for now, but we can sync the rest, and come up with a plan to fully
> update in time?
That's one possible solution, yes, and so far the easiest, it provides
a good balance between features and compatibility.
Theoretically we can never fully sync, unless we decide to no longer
support those older OSes (older Linux kernels and (current) *BSD).
One thing we could explore is patching the DT at runtime, but U-Boot
cannot know if the OS supports the new style or not, so it has to be
manually triggered.
Cheers,
Andre
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-30 0:08 ` Andre Przywara
@ 2022-04-30 2:38 ` Samuel Holland
2022-05-01 0:59 ` Andre Przywara
2022-05-01 16:25 ` Tom Rini
1 sibling, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-04-30 2:38 UTC (permalink / raw)
To: Andre Przywara, Tom Rini; +Cc: Mark Kettenis, robh, u-boot, jagan, sjg
On 4/29/22 7:08 PM, Andre Przywara wrote:
> On Fri, 29 Apr 2022 14:14:19 -0400
> Tom Rini <trini@konsulko.com> wrote:
>
> Hi,
>
>> On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
>>>> Date: Fri, 29 Apr 2022 11:31:00 -0400
>>>> From: Tom Rini <trini@konsulko.com>
>>>>
>>>> On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
>>>>> On Fri, 29 Apr 2022 10:57:10 -0400
>>>>> Tom Rini <trini@konsulko.com> wrote:
>>>>>
>>>>> Hi,
>>>>>
>>>>>> On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
>>>>>>> On Wed, 27 Apr 2022 15:31:19 -0500
>>>>>>> Samuel Holland <samuel@sholland.org> wrote:
>>>>>>>
>>>>>>> Hi Samuel, Tom,
>>>>>>>
>>>>>>>> This series brings all of our devicetrees up to date with Linux.
>>>>>>>>
>>>>>>>> Older SoCs (before A83T) have not been synchronized in over 3 years.
>>>>>>>> And I don't have any of this hardware to test. But there are not major
>>>>>>>> changes to those devicetrees either.
>>>>>>>>
>>>>>>>> The big motivation for including older SoCs in this update is converting
>>>>>>>> the USB PHY driver to get its VBUS detection GPIO/regulator from the
>>>>>>>> devicetree instead of from a pin name in Kconfig. Many older boards had
>>>>>>>> those properties added or fixed since the last devicetree sync. This PHY
>>>>>>>> driver change is necessary to complete the DM_GPIO migration.
>>>>>>>>
>>>>>>>> A couple of breaking changes were made to several SoCs' devicetrees in
>>>>>>>> Linux relating to the "r_intc" interrupt controller. New kernels support
>>>>>>>> old devicetrees, but not the other way around. So to be most compatible
>>>>>>>> and avoid regressions, those changes are skipped here.
>>>>>>>
>>>>>>> Many thanks for considering this! I just skimmed over the A64 and H6
>>>>>>> patches, and this is indeed the only difference.
>>>>>>>
>>>>>>> But while I love this pragmatic approach, and would be happy to take this,
>>>>>>> this goes against our own rules, and more importantly against Tom's one's:
>>>>>>> to take only direct DT file copies from the kernel tree.
>>>>>>>
>>>>>>> Tom, can you give your opinion here? As Samuel mentioned above, the
>>>>>>> current mainline DTs wouldn't boot on older kernels (the changes affect
>>>>>>> critical devices), so this spoils stable distro and installer kernels,
>>>>>>> when using $fdtcontroladdr, for instance when booting via UEFI.
>>>>>>>
>>>>>>> As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
>>>>>>> use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
>>>>>>>
>>>>>>> For context, those changed properties were in the mainline kernel tree at
>>>>>>> some point, but have been amended since. So it's not some random change.
>>>>>>
>>>>>> So, this is I guess a bit annoying. But, we aren't at the point where
>>>>>> the common use case is the downstream OS using the DTB we've loaded and
>>>>>> are using, are we? I mean, we can't be, as ours are so far out of date,
>>>>>> so this will only be an option when we use a recent DT ourself. So we
>>>>>> should be able to sync in the changes and update our code, as they can't
>>>>>> be using $fdtcontroladdr in this case, right? Or am I missing the use
>>>>>> case that's in the wild atm? Thanks!
>>>>>
>>>>> While it sounds like the DTs are wildly out of date, this mostly affects
>>>>> secondary functionality. The mainline updates for the 64-bit SoCs are:
>>>>> - H6: adding the VP9 video h/w codec and an additional wakeup timer
>>>>> - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
>>>>> digital audio interfaces, plus the wakeup timer
>>>>> Also there are cosmetic changes, like changing node names to make them
>>>>> binding compliant.
The SoCs where the DTs are wildly out of date (v4.18-rc3) are:
A10 A10s/A13 A31 A20 A80 A23/A33 A83T
The SoCs with the r_intc binding change are:
A31 A23/A33 A83T A64 H3/H5 H6
For the SoCs which are in both lists, yes, it is unlikely that anyone is using
$fdtcontroladdr for Linux. So we could probably fully update those DTs. That
leaves just A64, H3/H5, and H6 which would temporarily need to exclude the
r_intc-related changes.
>>>>> So those DT updates are really only important for mobile devices like the
>>>>> Pinephone, which probably don't use UEFI booting.
We would really like to use UEFI booting on the PinePhone, and the out-of-date
devicetree is one thing blocking that. We need to use $fdtcontroladdr to pick up
the CPU idle states that are added at runtime by TF-A.
>>>>> At the moment I boot distro grubs and installers just fine, and without
>>>>> losing any real functionality (minus suspend/resume, maybe). The
>>>>> out-of-the-box default boot works now, and would break when pulling in the
>>>>> pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
>>>>> can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
FreeBSD already supports the new binding for forwarding interrupts (everything
except NMI). Any version with this change should boot fine:
https://cgit.freebsd.org/src/commit/?id=993e8236c30a
>>>> I guess the first point is, yes, we should sync in what we can sync in,
>>>> to bring things closer to proper alignment. I further guess that given
>>>> that we have to support both "new Linux" and "not Linux", we have to
>>>> keep the old style DT information instead as that's how compatibility is
>>>> supposed to be handled? I'm adding in Rob here since this still reads a
>>>> bit confusing as to what's supposed to happen, but maybe we also just
>>>> need to check in with some other-OS folks to see what their plan is?
>>>
>>> My goal with OpenBSD has always been to make the OS boot with the DT
>>> built into U-Boot, but to allow users to use a more up-to-date Linux
>>> DT by putting the apropriate .dtb file on the ESP. However it is easy
>>> to miss changes that break backwards compatibility of the bindings in
>>> the noise of other changes. So in many cases we only notice this when
>>> the changes make it into U-Boot and we update the OpenBSD U-Boot port.
>>>
>>> I'll drag out one of my A64 boards and see what needs to be done to
>>> support the routing of these interrupts through r_intc.
>
> In FreeBSD the change would be fairly small, I think: just ignoring the
> first parameter of an r_intc interrupt specifier when it advertises
> #interrupt-cells = <3>.
See above, FreeBSD already supports this.
> In OpenBSD I don't find the allwinner,sun6i-a31-r-intc (or any other
> intc related) compatible string at all, and so far we just lose the NMI
> from the PMIC. But this would radically change with the new DT: now the
> two PIOs and the RTC are routed through that IRQ controller, so they
> would probably fail probing.
>
>> So, does that mean the plan is to keep the r_intc changes out of U-Boot
>> for now, but we can sync the rest, and come up with a plan to fully
>> update in time?
>
> That's one possible solution, yes, and so far the easiest, it provides
> a good balance between features and compatibility.
This was my understanding of the plan as well.
> Theoretically we can never fully sync, unless we decide to no longer
> support those older OSes (older Linux kernels and (current) *BSD).
Do we have any guidance for when this could be? After the n+1 LTS kernel/BSD
release? After the distro/BSD installers update their kernels?
> One thing we could explore is patching the DT at runtime, but U-Boot
> cannot know if the OS supports the new style or not, so it has to be
> manually triggered.
Right, automatically handling this is not really feasible. Users that need the
r_intc changes for suspend/resume will have to load a DTB or overlay from disk.
(We could possibly build in such an overlay, and load it based on some
environment variable, but this seems like little benefit when most users load a
DTB from disk anyway.)
Regards,
Samuel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-30 2:38 ` Samuel Holland
@ 2022-05-01 0:59 ` Andre Przywara
2022-05-01 11:01 ` Mark Kettenis
2022-05-03 1:57 ` Samuel Holland
0 siblings, 2 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-01 0:59 UTC (permalink / raw)
To: Samuel Holland; +Cc: Tom Rini, Mark Kettenis, robh, u-boot, jagan, sjg
On Fri, 29 Apr 2022 21:38:58 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
> On 4/29/22 7:08 PM, Andre Przywara wrote:
> > On Fri, 29 Apr 2022 14:14:19 -0400
> > Tom Rini <trini@konsulko.com> wrote:
> >
> > Hi,
> >
> >> On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
> >>>> Date: Fri, 29 Apr 2022 11:31:00 -0400
> >>>> From: Tom Rini <trini@konsulko.com>
> >>>>
> >>>> On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> >>>>> On Fri, 29 Apr 2022 10:57:10 -0400
> >>>>> Tom Rini <trini@konsulko.com> wrote:
> >>>>>
> >>>>> Hi,
> >>>>>
> >>>>>> On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> >>>>>>> On Wed, 27 Apr 2022 15:31:19 -0500
> >>>>>>> Samuel Holland <samuel@sholland.org> wrote:
> >>>>>>>
> >>>>>>> Hi Samuel, Tom,
> >>>>>>>
> >>>>>>>> This series brings all of our devicetrees up to date with Linux.
> >>>>>>>>
> >>>>>>>> Older SoCs (before A83T) have not been synchronized in over 3 years.
> >>>>>>>> And I don't have any of this hardware to test. But there are not major
> >>>>>>>> changes to those devicetrees either.
> >>>>>>>>
> >>>>>>>> The big motivation for including older SoCs in this update is converting
> >>>>>>>> the USB PHY driver to get its VBUS detection GPIO/regulator from the
> >>>>>>>> devicetree instead of from a pin name in Kconfig. Many older boards had
> >>>>>>>> those properties added or fixed since the last devicetree sync. This PHY
> >>>>>>>> driver change is necessary to complete the DM_GPIO migration.
> >>>>>>>>
> >>>>>>>> A couple of breaking changes were made to several SoCs' devicetrees in
> >>>>>>>> Linux relating to the "r_intc" interrupt controller. New kernels support
> >>>>>>>> old devicetrees, but not the other way around. So to be most compatible
> >>>>>>>> and avoid regressions, those changes are skipped here.
> >>>>>>>
> >>>>>>> Many thanks for considering this! I just skimmed over the A64 and H6
> >>>>>>> patches, and this is indeed the only difference.
> >>>>>>>
> >>>>>>> But while I love this pragmatic approach, and would be happy to take this,
> >>>>>>> this goes against our own rules, and more importantly against Tom's one's:
> >>>>>>> to take only direct DT file copies from the kernel tree.
> >>>>>>>
> >>>>>>> Tom, can you give your opinion here? As Samuel mentioned above, the
> >>>>>>> current mainline DTs wouldn't boot on older kernels (the changes affect
> >>>>>>> critical devices), so this spoils stable distro and installer kernels,
> >>>>>>> when using $fdtcontroladdr, for instance when booting via UEFI.
> >>>>>>>
> >>>>>>> As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> >>>>>>> use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> >>>>>>>
> >>>>>>> For context, those changed properties were in the mainline kernel tree at
> >>>>>>> some point, but have been amended since. So it's not some random change.
> >>>>>>
> >>>>>> So, this is I guess a bit annoying. But, we aren't at the point where
> >>>>>> the common use case is the downstream OS using the DTB we've loaded and
> >>>>>> are using, are we? I mean, we can't be, as ours are so far out of date,
> >>>>>> so this will only be an option when we use a recent DT ourself. So we
> >>>>>> should be able to sync in the changes and update our code, as they can't
> >>>>>> be using $fdtcontroladdr in this case, right? Or am I missing the use
> >>>>>> case that's in the wild atm? Thanks!
> >>>>>
> >>>>> While it sounds like the DTs are wildly out of date, this mostly affects
> >>>>> secondary functionality. The mainline updates for the 64-bit SoCs are:
> >>>>> - H6: adding the VP9 video h/w codec and an additional wakeup timer
> >>>>> - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> >>>>> digital audio interfaces, plus the wakeup timer
> >>>>> Also there are cosmetic changes, like changing node names to make them
> >>>>> binding compliant.
>
> The SoCs where the DTs are wildly out of date (v4.18-rc3) are:
> A10 A10s/A13 A31 A20 A80 A23/A33 A83T
>
> The SoCs with the r_intc binding change are:
> A31 A23/A33 A83T A64 H3/H5 H6
>
> For the SoCs which are in both lists, yes, it is unlikely that anyone is using
> $fdtcontroladdr for Linux. So we could probably fully update those DTs. That
> leaves just A64, H3/H5, and H6 which would temporarily need to exclude the
> r_intc-related changes.
Yes, I don't really care about those older SoCs, devices using them are
probably not really distro / UEFI material anyway.
> >>>>> So those DT updates are really only important for mobile devices like the
> >>>>> Pinephone, which probably don't use UEFI booting.
>
> We would really like to use UEFI booting on the PinePhone, and the out-of-date
> devicetree is one thing blocking that. We need to use $fdtcontroladdr to pick up
> the CPU idle states that are added at runtime by TF-A.
Yes, I was wondering about that. I could imagine that suspend/resume is
a killer feature for the PinePhone. It probably sounds useful to fully
update just the Pinephone .dts, giving up compatibility for older
kernels. IIUC the PinePhone doesn't run normal "desktop" distros, but
relies more on custom OSes, tailored to a Phone use case in general?
What kernels are those OSes using?
The only caveat would be that this adds to the mess and increases the
diff to mainline, but maybe this could be solved by a
sun50i-a64-pinephone-u-boot.dtsi?
> >>>>> At the moment I boot distro grubs and installers just fine, and without
> >>>>> losing any real functionality (minus suspend/resume, maybe). The
> >>>>> out-of-the-box default boot works now, and would break when pulling in the
> >>>>> pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> >>>>> can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
>
> FreeBSD already supports the new binding for forwarding interrupts (everything
> except NMI). Any version with this change should boot fine:
>
> https://cgit.freebsd.org/src/commit/?id=993e8236c30a
Ah, sorry, my bad, I was looking at a stale repo (they stopped updating
the original master branch and switched to main, for technical reasons).
> >>>> I guess the first point is, yes, we should sync in what we can sync in,
> >>>> to bring things closer to proper alignment. I further guess that given
> >>>> that we have to support both "new Linux" and "not Linux", we have to
> >>>> keep the old style DT information instead as that's how compatibility is
> >>>> supposed to be handled? I'm adding in Rob here since this still reads a
> >>>> bit confusing as to what's supposed to happen, but maybe we also just
> >>>> need to check in with some other-OS folks to see what their plan is?
> >>>
> >>> My goal with OpenBSD has always been to make the OS boot with the DT
> >>> built into U-Boot, but to allow users to use a more up-to-date Linux
> >>> DT by putting the apropriate .dtb file on the ESP. However it is easy
> >>> to miss changes that break backwards compatibility of the bindings in
> >>> the noise of other changes. So in many cases we only notice this when
> >>> the changes make it into U-Boot and we update the OpenBSD U-Boot port.
> >>>
> >>> I'll drag out one of my A64 boards and see what needs to be done to
> >>> support the routing of these interrupts through r_intc.
> >
> > In FreeBSD the change would be fairly small, I think: just ignoring the
> > first parameter of an r_intc interrupt specifier when it advertises
> > #interrupt-cells = <3>.
>
> See above, FreeBSD already supports this.
>
> > In OpenBSD I don't find the allwinner,sun6i-a31-r-intc (or any other
> > intc related) compatible string at all, and so far we just lose the NMI
> > from the PMIC. But this would radically change with the new DT: now the
> > two PIOs and the RTC are routed through that IRQ controller, so they
> > would probably fail probing.
> >
> >> So, does that mean the plan is to keep the r_intc changes out of U-Boot
> >> for now, but we can sync the rest, and come up with a plan to fully
> >> update in time?
> >
> > That's one possible solution, yes, and so far the easiest, it provides
> > a good balance between features and compatibility.
>
> This was my understanding of the plan as well.
>
> > Theoretically we can never fully sync, unless we decide to no longer
> > support those older OSes (older Linux kernels and (current) *BSD).
>
> Do we have any guidance for when this could be? After the n+1 LTS kernel/BSD
> release? After the distro/BSD installers update their kernels?
More the latter, I'd say when major distros stop shipping those
old kernels in relevant releases. Especially Debian is one to keep an
eye on I guess, since they are on 5.10 *currently*, and their installer
properly stays there for a while. Ubuntu 20.04 shipped with 5.4, and I'd
like to support that say at least one more year still. Don't really
keep track of the kernels in other distros, but I think these two are
among the more conservative ones.
Samuel, since I have you here: With your new hat Linux hat on, can you
say whether incompatible DT changes won't happen in the future anymore?
From experience I'd say there are ways to avoid them, though possibly at
some cost (less clean DT, or deviating from some DT rules).
> > One thing we could explore is patching the DT at runtime, but U-Boot
> > cannot know if the OS supports the new style or not, so it has to be
> > manually triggered.
>
> Right, automatically handling this is not really feasible. Users that need the
> r_intc changes for suspend/resume will have to load a DTB or overlay from disk.
> (We could possibly build in such an overlay, and load it based on some
> environment variable, but this seems like little benefit when most users load a
> DTB from disk anyway.)
But loading from disk would lose any manipulation that previous
firmware did, for instance TF-A. Plus I think reserved memory is not
properly propagated, at least last time I checked. Also the DT would
really need to be loaded by U-Boot, loading it via grub would lose even
more manipulations like the DRAM size and MAC address.
So I believe an overlay is the way to go. I have a patch sitting here
that applies all .dtbo files found in a directory on some block device
(e.g. "fdt apply_all mmc 0:1 overlays/"), would that help?
Cheers,
Andre
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-05-01 0:59 ` Andre Przywara
@ 2022-05-01 11:01 ` Mark Kettenis
2022-05-03 1:57 ` Samuel Holland
1 sibling, 0 replies; 41+ messages in thread
From: Mark Kettenis @ 2022-05-01 11:01 UTC (permalink / raw)
To: Andre Przywara; +Cc: samuel, trini, robh, u-boot, jagan, sjg
> Date: Sun, 1 May 2022 01:59:21 +0100
> From: Andre Przywara <andre.przywara@arm.com>
Hi Andre,
> On Fri, 29 Apr 2022 21:38:58 -0500
> Samuel Holland <samuel@sholland.org> wrote:
>
> Hi Samuel,
>
> > On 4/29/22 7:08 PM, Andre Przywara wrote:
> > > On Fri, 29 Apr 2022 14:14:19 -0400
> > > Tom Rini <trini@konsulko.com> wrote:
> > >
> > > Hi,
> > >
> > >> On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
> > >>>> Date: Fri, 29 Apr 2022 11:31:00 -0400
> > >>>> From: Tom Rini <trini@konsulko.com>
> > >>>>
> > >>>> On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> > >>>>> On Fri, 29 Apr 2022 10:57:10 -0400
> > >>>>> Tom Rini <trini@konsulko.com> wrote:
> > >>>>>
> > >>>>> Hi,
> > >>>>>
> > >>>>>> On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > >>>>>>> On Wed, 27 Apr 2022 15:31:19 -0500
> > >>>>>>> Samuel Holland <samuel@sholland.org> wrote:
> > >>>>>>>
> > >>>>>>> Hi Samuel, Tom,
> > >>>>>>>
> > >>>>>>>> This series brings all of our devicetrees up to date with Linux.
> > >>>>>>>>
> > >>>>>>>> Older SoCs (before A83T) have not been synchronized in over 3 years.
> > >>>>>>>> And I don't have any of this hardware to test. But there are not major
> > >>>>>>>> changes to those devicetrees either.
> > >>>>>>>>
> > >>>>>>>> The big motivation for including older SoCs in this update is converting
> > >>>>>>>> the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > >>>>>>>> devicetree instead of from a pin name in Kconfig. Many older boards had
> > >>>>>>>> those properties added or fixed since the last devicetree sync. This PHY
> > >>>>>>>> driver change is necessary to complete the DM_GPIO migration.
> > >>>>>>>>
> > >>>>>>>> A couple of breaking changes were made to several SoCs' devicetrees in
> > >>>>>>>> Linux relating to the "r_intc" interrupt controller. New kernels support
> > >>>>>>>> old devicetrees, but not the other way around. So to be most compatible
> > >>>>>>>> and avoid regressions, those changes are skipped here.
> > >>>>>>>
> > >>>>>>> Many thanks for considering this! I just skimmed over the A64 and H6
> > >>>>>>> patches, and this is indeed the only difference.
> > >>>>>>>
> > >>>>>>> But while I love this pragmatic approach, and would be happy to take this,
> > >>>>>>> this goes against our own rules, and more importantly against Tom's one's:
> > >>>>>>> to take only direct DT file copies from the kernel tree.
> > >>>>>>>
> > >>>>>>> Tom, can you give your opinion here? As Samuel mentioned above, the
> > >>>>>>> current mainline DTs wouldn't boot on older kernels (the changes affect
> > >>>>>>> critical devices), so this spoils stable distro and installer kernels,
> > >>>>>>> when using $fdtcontroladdr, for instance when booting via UEFI.
> > >>>>>>>
> > >>>>>>> As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > >>>>>>> use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > >>>>>>>
> > >>>>>>> For context, those changed properties were in the mainline kernel tree at
> > >>>>>>> some point, but have been amended since. So it's not some random change.
> > >>>>>>
> > >>>>>> So, this is I guess a bit annoying. But, we aren't at the point where
> > >>>>>> the common use case is the downstream OS using the DTB we've loaded and
> > >>>>>> are using, are we? I mean, we can't be, as ours are so far out of date,
> > >>>>>> so this will only be an option when we use a recent DT ourself. So we
> > >>>>>> should be able to sync in the changes and update our code, as they can't
> > >>>>>> be using $fdtcontroladdr in this case, right? Or am I missing the use
> > >>>>>> case that's in the wild atm? Thanks!
> > >>>>>
> > >>>>> While it sounds like the DTs are wildly out of date, this mostly affects
> > >>>>> secondary functionality. The mainline updates for the 64-bit SoCs are:
> > >>>>> - H6: adding the VP9 video h/w codec and an additional wakeup timer
> > >>>>> - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> > >>>>> digital audio interfaces, plus the wakeup timer
> > >>>>> Also there are cosmetic changes, like changing node names to make them
> > >>>>> binding compliant.
> >
> > The SoCs where the DTs are wildly out of date (v4.18-rc3) are:
> > A10 A10s/A13 A31 A20 A80 A23/A33 A83T
> >
> > The SoCs with the r_intc binding change are:
> > A31 A23/A33 A83T A64 H3/H5 H6
> >
> > For the SoCs which are in both lists, yes, it is unlikely that anyone is using
> > $fdtcontroladdr for Linux. So we could probably fully update those DTs. That
> > leaves just A64, H3/H5, and H6 which would temporarily need to exclude the
> > r_intc-related changes.
>
> Yes, I don't really care about those older SoCs, devices using them are
> probably not really distro / UEFI material anyway.
OpenBSD boots via UEFI on all of these SoCs (A31, A23/A33 and A83T are
not really supported though). That said, I just checked and OpenBSD
still boots on my NanoPi A64 with a device tree from mainline Linux.
Basically, we don't have a driver for the r_intc interrupt controller
yet and none of the drivers that are affected by change actually use
interrupts. So everything that's important still works ;).
So basically, don't let OpenBSD hold you back.
> > >>>>> So those DT updates are really only important for mobile devices like the
> > >>>>> Pinephone, which probably don't use UEFI booting.
> >
> > We would really like to use UEFI booting on the PinePhone, and the out-of-date
> > devicetree is one thing blocking that. We need to use $fdtcontroladdr to pick up
> > the CPU idle states that are added at runtime by TF-A.
>
> Yes, I was wondering about that. I could imagine that suspend/resume is
> a killer feature for the PinePhone. It probably sounds useful to fully
> update just the Pinephone .dts, giving up compatibility for older
> kernels. IIUC the PinePhone doesn't run normal "desktop" distros, but
> relies more on custom OSes, tailored to a Phone use case in general?
> What kernels are those OSes using?
> The only caveat would be that this adds to the mess and increases the
> diff to mainline, but maybe this could be solved by a
> sun50i-a64-pinephone-u-boot.dtsi?
>
> > >>>>> At the moment I boot distro grubs and installers just fine, and without
> > >>>>> losing any real functionality (minus suspend/resume, maybe). The
> > >>>>> out-of-the-box default boot works now, and would break when pulling in the
> > >>>>> pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> > >>>>> can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
> >
> > FreeBSD already supports the new binding for forwarding interrupts (everything
> > except NMI). Any version with this change should boot fine:
> >
> > https://cgit.freebsd.org/src/commit/?id=993e8236c30a
>
> Ah, sorry, my bad, I was looking at a stale repo (they stopped updating
> the original master branch and switched to main, for technical reasons).
>
> > >>>> I guess the first point is, yes, we should sync in what we can sync in,
> > >>>> to bring things closer to proper alignment. I further guess that given
> > >>>> that we have to support both "new Linux" and "not Linux", we have to
> > >>>> keep the old style DT information instead as that's how compatibility is
> > >>>> supposed to be handled? I'm adding in Rob here since this still reads a
> > >>>> bit confusing as to what's supposed to happen, but maybe we also just
> > >>>> need to check in with some other-OS folks to see what their plan is?
> > >>>
> > >>> My goal with OpenBSD has always been to make the OS boot with the DT
> > >>> built into U-Boot, but to allow users to use a more up-to-date Linux
> > >>> DT by putting the apropriate .dtb file on the ESP. However it is easy
> > >>> to miss changes that break backwards compatibility of the bindings in
> > >>> the noise of other changes. So in many cases we only notice this when
> > >>> the changes make it into U-Boot and we update the OpenBSD U-Boot port.
> > >>>
> > >>> I'll drag out one of my A64 boards and see what needs to be done to
> > >>> support the routing of these interrupts through r_intc.
> > >
> > > In FreeBSD the change would be fairly small, I think: just ignoring the
> > > first parameter of an r_intc interrupt specifier when it advertises
> > > #interrupt-cells = <3>.
> >
> > See above, FreeBSD already supports this.
> >
> > > In OpenBSD I don't find the allwinner,sun6i-a31-r-intc (or any other
> > > intc related) compatible string at all, and so far we just lose the NMI
> > > from the PMIC. But this would radically change with the new DT: now the
> > > two PIOs and the RTC are routed through that IRQ controller, so they
> > > would probably fail probing.
> > >
> > >> So, does that mean the plan is to keep the r_intc changes out of U-Boot
> > >> for now, but we can sync the rest, and come up with a plan to fully
> > >> update in time?
> > >
> > > That's one possible solution, yes, and so far the easiest, it provides
> > > a good balance between features and compatibility.
> >
> > This was my understanding of the plan as well.
> >
> > > Theoretically we can never fully sync, unless we decide to no longer
> > > support those older OSes (older Linux kernels and (current) *BSD).
> >
> > Do we have any guidance for when this could be? After the n+1 LTS kernel/BSD
> > release? After the distro/BSD installers update their kernels?
>
> More the latter, I'd say when major distros stop shipping those
> old kernels in relevant releases. Especially Debian is one to keep an
> eye on I guess, since they are on 5.10 *currently*, and their installer
> properly stays there for a while. Ubuntu 20.04 shipped with 5.4, and I'd
> like to support that say at least one more year still. Don't really
> keep track of the kernels in other distros, but I think these two are
> among the more conservative ones.
So as stated above, OpenBSD is unaffected by the r_intc changes. If
it would be affected, our release cycle is 6 months, so backwards
compatibility would be needed for a little bit longer than 6 months
probably.
> Samuel, since I have you here: With your new hat Linux hat on, can you
> say whether incompatible DT changes won't happen in the future anymore?
> From experience I'd say there are ways to avoid them, though possibly at
> some cost (less clean DT, or deviating from some DT rules).
>
> > > One thing we could explore is patching the DT at runtime, but U-Boot
> > > cannot know if the OS supports the new style or not, so it has to be
> > > manually triggered.
> >
> > Right, automatically handling this is not really feasible. Users that need the
> > r_intc changes for suspend/resume will have to load a DTB or overlay from disk.
> > (We could possibly build in such an overlay, and load it based on some
> > environment variable, but this seems like little benefit when most users load a
> > DTB from disk anyway.)
>
> But loading from disk would lose any manipulation that previous
> firmware did, for instance TF-A. Plus I think reserved memory is not
> properly propagated, at least last time I checked. Also the DT would
> really need to be loaded by U-Boot, loading it via grub would lose even
> more manipulations like the DRAM size and MAC address.
>
> So I believe an overlay is the way to go. I have a patch sitting here
> that applies all .dtbo files found in a directory on some block device
> (e.g. "fdt apply_all mmc 0:1 overlays/"), would that help?
>
> Cheers,
> Andre
>
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-30 0:08 ` Andre Przywara
2022-04-30 2:38 ` Samuel Holland
@ 2022-05-01 16:25 ` Tom Rini
1 sibling, 0 replies; 41+ messages in thread
From: Tom Rini @ 2022-05-01 16:25 UTC (permalink / raw)
To: Andre Przywara; +Cc: Mark Kettenis, robh, samuel, u-boot, jagan, sjg
[-- Attachment #1: Type: text/plain, Size: 7217 bytes --]
On Sat, Apr 30, 2022 at 01:08:43AM +0100, Andre Przywara wrote:
> On Fri, 29 Apr 2022 14:14:19 -0400
> Tom Rini <trini@konsulko.com> wrote:
>
> Hi,
>
> > On Fri, Apr 29, 2022 at 06:05:03PM +0200, Mark Kettenis wrote:
> > > > Date: Fri, 29 Apr 2022 11:31:00 -0400
> > > > From: Tom Rini <trini@konsulko.com>
> > > >
> > > > On Fri, Apr 29, 2022 at 04:25:51PM +0100, Andre Przywara wrote:
> > > > > On Fri, 29 Apr 2022 10:57:10 -0400
> > > > > Tom Rini <trini@konsulko.com> wrote:
> > > > >
> > > > > Hi,
> > > > >
> > > > > > On Fri, Apr 29, 2022 at 03:51:59PM +0100, Andre Przywara wrote:
> > > > > > > On Wed, 27 Apr 2022 15:31:19 -0500
> > > > > > > Samuel Holland <samuel@sholland.org> wrote:
> > > > > > >
> > > > > > > Hi Samuel, Tom,
> > > > > > >
> > > > > > > > This series brings all of our devicetrees up to date with Linux.
> > > > > > > >
> > > > > > > > Older SoCs (before A83T) have not been synchronized in over 3 years.
> > > > > > > > And I don't have any of this hardware to test. But there are not major
> > > > > > > > changes to those devicetrees either.
> > > > > > > >
> > > > > > > > The big motivation for including older SoCs in this update is converting
> > > > > > > > the USB PHY driver to get its VBUS detection GPIO/regulator from the
> > > > > > > > devicetree instead of from a pin name in Kconfig. Many older boards had
> > > > > > > > those properties added or fixed since the last devicetree sync. This PHY
> > > > > > > > driver change is necessary to complete the DM_GPIO migration.
> > > > > > > >
> > > > > > > > A couple of breaking changes were made to several SoCs' devicetrees in
> > > > > > > > Linux relating to the "r_intc" interrupt controller. New kernels support
> > > > > > > > old devicetrees, but not the other way around. So to be most compatible
> > > > > > > > and avoid regressions, those changes are skipped here.
> > > > > > >
> > > > > > > Many thanks for considering this! I just skimmed over the A64 and H6
> > > > > > > patches, and this is indeed the only difference.
> > > > > > >
> > > > > > > But while I love this pragmatic approach, and would be happy to take this,
> > > > > > > this goes against our own rules, and more importantly against Tom's one's:
> > > > > > > to take only direct DT file copies from the kernel tree.
> > > > > > >
> > > > > > > Tom, can you give your opinion here? As Samuel mentioned above, the
> > > > > > > current mainline DTs wouldn't boot on older kernels (the changes affect
> > > > > > > critical devices), so this spoils stable distro and installer kernels,
> > > > > > > when using $fdtcontroladdr, for instance when booting via UEFI.
> > > > > > >
> > > > > > > As a side effect of always defining SYS_SOC to "sunxi", we cannot easily
> > > > > > > use per-SoC DT overrides using sun50i-a64-u-boot.dtsi, for instance.
> > > > > > >
> > > > > > > For context, those changed properties were in the mainline kernel tree at
> > > > > > > some point, but have been amended since. So it's not some random change.
> > > > > >
> > > > > > So, this is I guess a bit annoying. But, we aren't at the point where
> > > > > > the common use case is the downstream OS using the DTB we've loaded and
> > > > > > are using, are we? I mean, we can't be, as ours are so far out of date,
> > > > > > so this will only be an option when we use a recent DT ourself. So we
> > > > > > should be able to sync in the changes and update our code, as they can't
> > > > > > be using $fdtcontroladdr in this case, right? Or am I missing the use
> > > > > > case that's in the wild atm? Thanks!
> > > > >
> > > > > While it sounds like the DTs are wildly out of date, this mostly affects
> > > > > secondary functionality. The mainline updates for the 64-bit SoCs are:
> > > > > - H6: adding the VP9 video h/w codec and an additional wakeup timer
> > > > > - A64: adding GPU DVFS, adding DRAM DVFS, add support for secondary
> > > > > digital audio interfaces, plus the wakeup timer
> > > > > Also there are cosmetic changes, like changing node names to make them
> > > > > binding compliant.
> > > > > So those DT updates are really only important for mobile devices like the
> > > > > Pinephone, which probably don't use UEFI booting.
> > > > >
> > > > > At the moment I boot distro grubs and installers just fine, and without
> > > > > losing any real functionality (minus suspend/resume, maybe). The
> > > > > out-of-the-box default boot works now, and would break when pulling in the
> > > > > pure mainline DTs. Plus FreeBSD (which relies more heavily on UEFI, IIUC),
> > > > > can only deal with the older DTs (#interrupt-cells for r_intc must be 2).
> > > >
> > > > I guess the first point is, yes, we should sync in what we can sync in,
> > > > to bring things closer to proper alignment. I further guess that given
> > > > that we have to support both "new Linux" and "not Linux", we have to
> > > > keep the old style DT information instead as that's how compatibility is
> > > > supposed to be handled? I'm adding in Rob here since this still reads a
> > > > bit confusing as to what's supposed to happen, but maybe we also just
> > > > need to check in with some other-OS folks to see what their plan is?
> > >
> > > My goal with OpenBSD has always been to make the OS boot with the DT
> > > built into U-Boot, but to allow users to use a more up-to-date Linux
> > > DT by putting the apropriate .dtb file on the ESP. However it is easy
> > > to miss changes that break backwards compatibility of the bindings in
> > > the noise of other changes. So in many cases we only notice this when
> > > the changes make it into U-Boot and we update the OpenBSD U-Boot port.
> > >
> > > I'll drag out one of my A64 boards and see what needs to be done to
> > > support the routing of these interrupts through r_intc.
>
> In FreeBSD the change would be fairly small, I think: just ignoring the
> first parameter of an r_intc interrupt specifier when it advertises
> #interrupt-cells = <3>.
> In OpenBSD I don't find the allwinner,sun6i-a31-r-intc (or any other
> intc related) compatible string at all, and so far we just lose the NMI
> from the PMIC. But this would radically change with the new DT: now the
> two PIOs and the RTC are routed through that IRQ controller, so they
> would probably fail probing.
>
> > So, does that mean the plan is to keep the r_intc changes out of U-Boot
> > for now, but we can sync the rest, and come up with a plan to fully
> > update in time?
>
> That's one possible solution, yes, and so far the easiest, it provides
> a good balance between features and compatibility.
> Theoretically we can never fully sync, unless we decide to no longer
> support those older OSes (older Linux kernels and (current) *BSD).
I believe saying older OSes need to load and pass their device tee,
rather than be able to rely on the run-time one, is reasonable. We need
to document this somewhere, and then specifically call this out in
release emails. But, it seems like a reasonable compromise for
supporting older OSes.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-05-01 0:59 ` Andre Przywara
2022-05-01 11:01 ` Mark Kettenis
@ 2022-05-03 1:57 ` Samuel Holland
2022-05-03 14:53 ` Andre Przywara
1 sibling, 1 reply; 41+ messages in thread
From: Samuel Holland @ 2022-05-03 1:57 UTC (permalink / raw)
To: Andre Przywara; +Cc: Tom Rini, Mark Kettenis, robh, u-boot, jagan, sjg, samuel
On 4/30/22 7:59 PM, Andre Przywara wrote:
>>>>>>> So those DT updates are really only important for mobile devices like the
>>>>>>> Pinephone, which probably don't use UEFI booting.
>>
>> We would really like to use UEFI booting on the PinePhone, and the out-of-date
>> devicetree is one thing blocking that. We need to use $fdtcontroladdr to pick up
>> the CPU idle states that are added at runtime by TF-A.
>
> Yes, I was wondering about that. I could imagine that suspend/resume is
> a killer feature for the PinePhone. It probably sounds useful to fully
> update just the Pinephone .dts, giving up compatibility for older
> kernels. IIUC the PinePhone doesn't run normal "desktop" distros, but
> relies more on custom OSes, tailored to a Phone use case in general?
There is a mix of desktop distros, mobile spins of desktop distros (the
largest/most popular category), and mobile-specific OSes[1].
[1]: https://wiki.pine64.org/wiki/PinePhone_Software_Releases
> What kernels are those OSes using?
Most are using Ondrej's fork[2]. Some (at least Mobian) maintain their own patch
set.
[2]: https://github.com/megous/linux/tags
> The only caveat would be that this adds to the mess and increases the
> diff to mainline, but maybe this could be solved by a
> sun50i-a64-pinephone-u-boot.dtsi?
Devicetree changes are still needed for camera and USB Type C support, so the
r_intc changes could go in with those. I don't think we need to do anything
special from the U-Boot side at this point.
>>>> So, does that mean the plan is to keep the r_intc changes out of U-Boot
>>>> for now, but we can sync the rest, and come up with a plan to fully
>>>> update in time?
>>>
>>> That's one possible solution, yes, and so far the easiest, it provides
>>> a good balance between features and compatibility.
>>
>> This was my understanding of the plan as well.
>>
>>> Theoretically we can never fully sync, unless we decide to no longer
>>> support those older OSes (older Linux kernels and (current) *BSD).
>>
>> Do we have any guidance for when this could be? After the n+1 LTS kernel/BSD
>> release? After the distro/BSD installers update their kernels?
>
> More the latter, I'd say when major distros stop shipping those
> old kernels in relevant releases. Especially Debian is one to keep an
> eye on I guess, since they are on 5.10 *currently*, and their installer
> properly stays there for a while. Ubuntu 20.04 shipped with 5.4, and I'd
> like to support that say at least one more year still. Don't really
> keep track of the kernels in other distros, but I think these two are
> among the more conservative ones.
OK, that makes sense.
> Samuel, since I have you here: With your new hat Linux hat on, can you
> say whether incompatible DT changes won't happen in the future anymore?
No, I really cannot.
As for major breaking changes, there is some push from the Linux clock
maintainers toward finishing the conversion from legacy to sunxi-ng clock
drivers. This affects A31, A23/A33, and A80. (In fact, this unfinished
conversion is causing me quite some trouble trying to expand the DM clock
drivers in U-Boot.)
And then there are always little easy-to-miss things (like adding references to
new ASoC widgets) that prevent drivers from loading on old kernels.
> From experience I'd say there are ways to avoid them, though possibly at
> some cost (less clean DT, or deviating from some DT rules).
and, as I'm sure you're painfully aware of, delays in adding support for new
hardware, until we can get the binding perfect, because we know we will be stuck
with it.
>>> One thing we could explore is patching the DT at runtime, but U-Boot
>>> cannot know if the OS supports the new style or not, so it has to be
>>> manually triggered.
>>
>> Right, automatically handling this is not really feasible. Users that need the
>> r_intc changes for suspend/resume will have to load a DTB or overlay from disk.
>> (We could possibly build in such an overlay, and load it based on some
>> environment variable, but this seems like little benefit when most users load a
>> DTB from disk anyway.)
>
> But loading from disk would lose any manipulation that previous
> firmware did, for instance TF-A. Plus I think reserved memory is not
> properly propagated, at least last time I checked. Also the DT would
> really need to be loaded by U-Boot, loading it via grub would lose even
> more manipulations like the DRAM size and MAC address.
>
> So I believe an overlay is the way to go. I have a patch sitting here
> that applies all .dtbo files found in a directory on some block device
> (e.g. "fdt apply_all mmc 0:1 overlays/"), would that help?
Possibly? I will defer to others on how devicetree overlays could/should be
integrated into the distro boot process.
Regards,
Samuel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-05-03 1:57 ` Samuel Holland
@ 2022-05-03 14:53 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-03 14:53 UTC (permalink / raw)
To: Samuel Holland; +Cc: Tom Rini, Mark Kettenis, robh, u-boot, jagan, sjg, samuel
On Mon, 2 May 2022 20:57:35 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi Samuel,
> On 4/30/22 7:59 PM, Andre Przywara wrote:
> >>>>>>> So those DT updates are really only important for mobile devices like the
> >>>>>>> Pinephone, which probably don't use UEFI booting.
> >>
> >> We would really like to use UEFI booting on the PinePhone, and the out-of-date
> >> devicetree is one thing blocking that. We need to use $fdtcontroladdr to pick up
> >> the CPU idle states that are added at runtime by TF-A.
> >
> > Yes, I was wondering about that. I could imagine that suspend/resume is
> > a killer feature for the PinePhone. It probably sounds useful to fully
> > update just the Pinephone .dts, giving up compatibility for older
> > kernels. IIUC the PinePhone doesn't run normal "desktop" distros, but
> > relies more on custom OSes, tailored to a Phone use case in general?
>
> There is a mix of desktop distros, mobile spins of desktop distros (the
> largest/most popular category), and mobile-specific OSes[1].
>
> [1]: https://wiki.pine64.org/wiki/PinePhone_Software_Releases
>
> > What kernels are those OSes using?
>
> Most are using Ondrej's fork[2]. Some (at least Mobian) maintain their own patch
> set.
So that means it's all quite Pinephone specific then, and none of
them are using actual mainline kernels? So people don't run a stock Debian
mini.iso on it, for instance?
When I was asking for "kernels", I was hoping for mainline kernel *version
numbers*, not forks, but I get the idea ;-)
> [2]: https://github.com/megous/linux/tags
>
> > The only caveat would be that this adds to the mess and increases the
> > diff to mainline, but maybe this could be solved by a
> > sun50i-a64-pinephone-u-boot.dtsi?
>
> Devicetree changes are still needed for camera and USB Type C support, so the
> r_intc changes could go in with those. I don't think we need to do anything
> special from the U-Boot side at this point.
I was thinking about putting the r_intc changes just in the
pinephone-u-boot.dtsi, so that the Pinephone gets them, but every other
(development) board does not. Sounds somewhat dodgy, but would
pragmatically solve the problem of stability for devboards *and* the
Pinephone being usable. Do Pinephone users actually use U-Boot?
Also I am not so much concerned about non-essential devices like a camera
or USB-C alternative functions, I guess those could even be fixed up using
DT overlays while running Linux already, from some script.
The problem with the r_intc changes is that last time I checked they break
already when booting an initrd, because of the pinctrl driver not probing.
> >>>> So, does that mean the plan is to keep the r_intc changes out of U-Boot
> >>>> for now, but we can sync the rest, and come up with a plan to fully
> >>>> update in time?
> >>>
> >>> That's one possible solution, yes, and so far the easiest, it provides
> >>> a good balance between features and compatibility.
> >>
> >> This was my understanding of the plan as well.
> >>
> >>> Theoretically we can never fully sync, unless we decide to no longer
> >>> support those older OSes (older Linux kernels and (current) *BSD).
> >>
> >> Do we have any guidance for when this could be? After the n+1 LTS kernel/BSD
> >> release? After the distro/BSD installers update their kernels?
> >
> > More the latter, I'd say when major distros stop shipping those
> > old kernels in relevant releases. Especially Debian is one to keep an
> > eye on I guess, since they are on 5.10 *currently*, and their installer
> > properly stays there for a while. Ubuntu 20.04 shipped with 5.4, and I'd
> > like to support that say at least one more year still. Don't really
> > keep track of the kernels in other distros, but I think these two are
> > among the more conservative ones.
>
> OK, that makes sense.
>
> > Samuel, since I have you here: With your new hat Linux hat on, can you
> > say whether incompatible DT changes won't happen in the future anymore?
>
> No, I really cannot.
>
> As for major breaking changes, there is some push from the Linux clock
> maintainers toward finishing the conversion from legacy to sunxi-ng clock
> drivers. This affects A31, A23/A33, and A80. (In fact, this unfinished
> conversion is causing me quite some trouble trying to expand the DM clock
> drivers in U-Boot.)
I am personally less concerned about those older devices, especially those
SoCs you mentioned, which were mostly somewhat "embedded" anyway. Plus
their DTs in the U-Boot tree are outdated already.
In my understanding the A10/A20/H3 devices see quite some more wide-spread
usage, some running off-the-shelf distros (I certainly do).
And I care more about the v8 devices, especially since arm64 has a more
grown-up boot story.
> And then there are always little easy-to-miss things (like adding references to
> new ASoC widgets) that prevent drivers from loading on old kernels.
As mentioned, if that affects secondary features like audio, video,
camera, that is less concerning to me. Not being able to boot at all
is a different story, though.
> > From experience I'd say there are ways to avoid them, though possibly at
> > some cost (less clean DT, or deviating from some DT rules).
>
> and, as I'm sure you're painfully aware of, delays in adding support for new
> hardware, until we can get the binding perfect, because we know we will be stuck
> with it.
Yes, I understand ;-)
I totally see that, and was already wondering about some kind of "grace
period" for new SoCs, so that we declare their DTs unstable initially, to
unblock development and gather experience with it in the field.
Just to make this clear: I understand that it's not easy to maintain DT
compatibility, but I think it's essential to make this a "serious"
platform.
I was just wondering if this compatibility goal is something that's
considered worth fighting for; in the past that was outright dismissed.
Cheers,
Andre
> >>> One thing we could explore is patching the DT at runtime, but U-Boot
> >>> cannot know if the OS supports the new style or not, so it has to be
> >>> manually triggered.
> >>
> >> Right, automatically handling this is not really feasible. Users that need the
> >> r_intc changes for suspend/resume will have to load a DTB or overlay from disk.
> >> (We could possibly build in such an overlay, and load it based on some
> >> environment variable, but this seems like little benefit when most users load a
> >> DTB from disk anyway.)
> >
> > But loading from disk would lose any manipulation that previous
> > firmware did, for instance TF-A. Plus I think reserved memory is not
> > properly propagated, at least last time I checked. Also the DT would
> > really need to be loaded by U-Boot, loading it via grub would lose even
> > more manipulations like the DRAM size and MAC address.
> >
> > So I believe an overlay is the way to go. I have a patch sitting here
> > that applies all .dtbo files found in a directory on some block device
> > (e.g. "fdt apply_all mmc 0:1 overlays/"), would that help?
>
> Possibly? I will defer to others on how devicetree overlays could/should be
> integrated into the distro boot process.
>
> Regards,
> Samuel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 01/12] dt-bindings: sunxi: Update clock/reset binding headers
2022-04-27 20:31 ` [PATCH 01/12] dt-bindings: sunxi: Update clock/reset binding headers Samuel Holland
@ 2022-05-06 0:39 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-06 0:39 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:20 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Some devicetree updates make use of newly-exposed clocks and resets.
> To support that, copy the binding headers from the Linux v5.18-rc1 tag.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Confirmed to be identical to the files in the Linux tree.
Also it only adds definitions, so is harmless to U-Boot.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> ---
>
> include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +-
> include/dt-bindings/clock/sun5i-ccu.h | 13 ++-----------
> include/dt-bindings/clock/sun6i-a31-ccu.h | 2 ++
> include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 2 ++
> include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +-
> include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 ++++
> include/dt-bindings/reset/sun5i-ccu.h | 11 +----------
> include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +++
> 8 files changed, 16 insertions(+), 23 deletions(-)
>
> diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h
> index 318eb15c41..175892189e 100644
> --- a/include/dt-bindings/clock/sun50i-a64-ccu.h
> +++ b/include/dt-bindings/clock/sun50i-a64-ccu.h
> @@ -113,7 +113,7 @@
> #define CLK_USB_OHCI0 91
>
> #define CLK_USB_OHCI1 93
> -
> +#define CLK_DRAM 94
> #define CLK_DRAM_VE 95
> #define CLK_DRAM_CSI 96
> #define CLK_DRAM_DEINTERLACE 97
> diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h
> index 81f34d477a..75fe5619c3 100644
> --- a/include/dt-bindings/clock/sun5i-ccu.h
> +++ b/include/dt-bindings/clock/sun5i-ccu.h
> @@ -1,17 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> /*
> * Copyright 2016 Maxime Ripard
> *
> * Maxime Ripard <maxime.ripard@free-electrons.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> */
>
> #ifndef _DT_BINDINGS_CLK_SUN5I_H_
> @@ -100,7 +91,7 @@
> #define CLK_AVS 96
> #define CLK_HDMI 97
> #define CLK_GPU 98
> -
> +#define CLK_MBUS 99
> #define CLK_IEP 100
>
> #endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
> diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
> index c5d1334018..39878d9dce 100644
> --- a/include/dt-bindings/clock/sun6i-a31-ccu.h
> +++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
> @@ -49,6 +49,8 @@
>
> #define CLK_PLL_VIDEO1_2X 13
>
> +#define CLK_PLL_MIPI 15
> +
> #define CLK_CPU 18
>
> #define CLK_AHB1_MIPIDSI 23
> diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
> index f8222b6b2c..eb524d0bbd 100644
> --- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
> +++ b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h
> @@ -43,6 +43,8 @@
> #ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
> #define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_
>
> +#define CLK_PLL_MIPI 13
> +
> #define CLK_CPUX 18
>
> #define CLK_BUS_MIPI_DSI 23
> diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
> index 30d2d15373..5d4ada2c22 100644
> --- a/include/dt-bindings/clock/sun8i-h3-ccu.h
> +++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
> @@ -126,7 +126,7 @@
> #define CLK_USB_OHCI1 93
> #define CLK_USB_OHCI2 94
> #define CLK_USB_OHCI3 95
> -
> +#define CLK_DRAM 96
> #define CLK_DRAM_VE 97
> #define CLK_DRAM_CSI 98
> #define CLK_DRAM_DEINTERLACE 99
> diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
> index c0d5d5599c..014ac6123d 100644
> --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
> +++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
> @@ -104,4 +104,8 @@
>
> #define CLK_MIPI_CSI 73
>
> +/* Clocks not available on V3s */
> +#define CLK_BUS_I2S0 75
> +#define CLK_I2S0 76
> +
> #endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
> diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h
> index c2b9726b50..40cc22ae76 100644
> --- a/include/dt-bindings/reset/sun5i-ccu.h
> +++ b/include/dt-bindings/reset/sun5i-ccu.h
> @@ -1,17 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> /*
> * Copyright 2016 Maxime Ripard
> *
> * Maxime Ripard <maxime.ripard@free-electrons.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License as published by
> - * the Free Software Foundation; either version 2 of the License, or
> - * (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> */
>
> #ifndef _RST_SUN5I_H_
> diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
> index b58ef21a2e..b6790173af 100644
> --- a/include/dt-bindings/reset/sun8i-v3s-ccu.h
> +++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h
> @@ -75,4 +75,7 @@
> #define RST_BUS_UART1 50
> #define RST_BUS_UART2 51
>
> +/* Reset lines not available on V3s */
> +#define RST_BUS_I2S0 52
> +
> #endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/12] ARM: dts: sunxi: Remove unused devicetree headers
2022-04-27 20:31 ` [PATCH 02/12] ARM: dts: sunxi: Remove unused devicetree headers Samuel Holland
@ 2022-05-06 0:39 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-06 0:39 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:21 -0500
Samuel Holland <samuel@sholland.org> wrote:
> These files are not included anywhere and do not exist in the Linux
> devicetree source.
Indeed, in contrast to sun8i-q8-common.dtsi, those files here are not
referenced anywhere in the U-Boot tree.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/sun5i-q8-common.dtsi | 180 ------------------------------
> arch/arm/dts/sunxi-q8-common.dtsi | 83 --------------
> 2 files changed, 263 deletions(-)
> delete mode 100644 arch/arm/dts/sun5i-q8-common.dtsi
> delete mode 100644 arch/arm/dts/sunxi-q8-common.dtsi
>
> diff --git a/arch/arm/dts/sun5i-q8-common.dtsi b/arch/arm/dts/sun5i-q8-common.dtsi
> deleted file mode 100644
> index a78e189f66..0000000000
> --- a/arch/arm/dts/sun5i-q8-common.dtsi
> +++ /dev/null
> @@ -1,180 +0,0 @@
> -/*
> - * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - * a) This file is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - * This file is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - * b) Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use,
> - * copy, modify, merge, publish, distribute, sublicense, and/or
> - * sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following
> - * conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - */
> -#include "sunxi-q8-common.dtsi"
> -
> -#include <dt-bindings/pwm/pwm.h>
> -
> -/ {
> - aliases {
> - serial0 = &uart1;
> - };
> -
> - backlight: backlight {
> - compatible = "pwm-backlight";
> - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
> - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> - default-brightness-level = <8>;
> - /* TODO: backlight uses axp gpio1 as enable pin */
> - };
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -};
> -
> -&cpu0 {
> - cpu-supply = <®_dcdc2>;
> -};
> -
> -&ehci0 {
> - status = "okay";
> -};
> -
> -&i2c0 {
> - axp209: pmic@34 {
> - reg = <0x34>;
> - interrupts = <0>;
> - };
> -};
> -
> -&i2c1 {
> - pcf8563: rtc@51 {
> - compatible = "nxp,pcf8563";
> - reg = <0x51>;
> - };
> -};
> -
> -#include "axp209.dtsi"
> -
> -&mmc0 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
> - vmmc-supply = <®_vcc3v0>;
> - bus-width = <4>;
> - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
> - cd-inverted;
> - status = "okay";
> -};
> -
> -&otg_sram {
> - status = "okay";
> -};
> -
> -&pio {
> - mmc0_cd_pin_q8: mmc0_cd_pin@0 {
> - allwinner,pins = "PG0";
> - allwinner,function = "gpio_in";
> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> - };
> -
> - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
> - allwinner,pins = "PG1";
> - allwinner,function = "gpio_in";
> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
> - };
> -
> - usb0_id_detect_pin: usb0_id_detect_pin@0 {
> - allwinner,pins = "PG2";
> - allwinner,function = "gpio_in";
> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
> - };
> -
> - usb0_vbus_pin_a: usb0_vbus_pin@0 {
> - allwinner,pins = "PG12";
> - allwinner,function = "gpio_out";
> - allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> - };
> -};
> -
> -®_dcdc2 {
> - regulator-always-on;
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1500000>;
> - regulator-name = "vdd-cpu";
> -};
> -
> -®_dcdc3 {
> - regulator-always-on;
> - regulator-min-microvolt = <1000000>;
> - regulator-max-microvolt = <1400000>;
> - regulator-name = "vdd-int-pll";
> -};
> -
> -®_ldo1 {
> - regulator-name = "vdd-rtc";
> -};
> -
> -®_ldo2 {
> - regulator-always-on;
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - regulator-name = "avcc";
> -};
> -
> -®_usb0_vbus {
> - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
> - status = "okay";
> -};
> -
> -&uart1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&uart1_pins_b>;
> - status = "okay";
> -};
> -
> -&usb_otg {
> - dr_mode = "otg";
> - status = "okay";
> -};
> -
> -&usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
> - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
> - usb0_vbus-supply = <®_usb0_vbus>;
> - status = "okay";
> -};
> diff --git a/arch/arm/dts/sunxi-q8-common.dtsi b/arch/arm/dts/sunxi-q8-common.dtsi
> deleted file mode 100644
> index b8241462fc..0000000000
> --- a/arch/arm/dts/sunxi-q8-common.dtsi
> +++ /dev/null
> @@ -1,83 +0,0 @@
> -/*
> - * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
> - *
> - * This file is dual-licensed: you can use it either under the terms
> - * of the GPL or the X11 license, at your option. Note that this dual
> - * licensing only applies to this file, and not this project as a
> - * whole.
> - *
> - * a) This file is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of the
> - * License, or (at your option) any later version.
> - *
> - * This file is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - * Or, alternatively,
> - *
> - * b) Permission is hereby granted, free of charge, to any person
> - * obtaining a copy of this software and associated documentation
> - * files (the "Software"), to deal in the Software without
> - * restriction, including without limitation the rights to use,
> - * copy, modify, merge, publish, distribute, sublicense, and/or
> - * sell copies of the Software, and to permit persons to whom the
> - * Software is furnished to do so, subject to the following
> - * conditions:
> - *
> - * The above copyright notice and this permission notice shall be
> - * included in all copies or substantial portions of the Software.
> - *
> - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> - * OTHER DEALINGS IN THE SOFTWARE.
> - */
> -
> -#include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/input/input.h>
> -#include <dt-bindings/pinctrl/sun4i-a10.h>
> -#include "sunxi-common-regulators.dtsi"
> -
> -&i2c0 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c0_pins_a>;
> - status = "okay";
> -};
> -
> -&i2c1 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&i2c1_pins_a>;
> - status = "okay";
> -};
> -
> -&lradc {
> - vref-supply = <®_vcc3v0>;
> - status = "okay";
> -
> - button@200 {
> - label = "Volume Up";
> - linux,code = <KEY_VOLUMEUP>;
> - channel = <0>;
> - voltage = <200000>;
> - };
> -
> - button@400 {
> - label = "Volume Down";
> - linux,code = <KEY_VOLUMEDOWN>;
> - channel = <0>;
> - voltage = <400000>;
> - };
> -};
> -
> -&pwm {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pwm0_pins>;
> - status = "okay";
> -};
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 03/12] ARM: dts: sun4i: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 03/12] ARM: dts: sun4i: Sync from Linux v5.18-rc1 Samuel Holland
@ 2022-05-06 0:39 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-06 0:39 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:22 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Copy the devicetree source for the A10 SoC and all existing boards
> verbatim from the Linux v5.18-rc1 tag.
>
> This commit also adds the following new board devicetree:
> - sun4i-a10-topwise-a721.dts
>
> While this update should not impact any existing U-Boot functionality,
> the changes to the USB PHY detection GPIO properties are needed to
> convert that driver to use the DM GPIO framework.
Interestingly Patchwork missed this patch, and saving it from my client
messed up the ISO8859/1 -> UTF8 conversion at the very top of
sun4i-a10-inet97fv2.dts. But I managed to fix that up manually. Other
than that there is indeed no diff compared to the kernel.
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/axp209.dtsi | 6 +-
> arch/arm/dts/sun4i-a10-a1000.dts | 31 ++-
> arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
> arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 20 +-
> arch/arm/dts/sun4i-a10-cubieboard.dts | 16 +-
> arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 21 +-
> arch/arm/dts/sun4i-a10-hackberry.dts | 2 +-
> arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 20 +-
> arch/arm/dts/sun4i-a10-inet1.dts | 21 +-
> arch/arm/dts/sun4i-a10-inet97fv2.dts | 22 +-
> arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 74 ++----
> .../dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +-
> arch/arm/dts/sun4i-a10-jesurun-q5.dts | 4 +-
> arch/arm/dts/sun4i-a10-marsboard.dts | 22 +-
> arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 33 +--
> arch/arm/dts/sun4i-a10-pcduino.dts | 20 +-
> arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 21 +-
> arch/arm/dts/sun4i-a10-topwise-a721.dts | 242 ++++++++++++++++++
> arch/arm/dts/sun4i-a10.dtsi | 135 +++++++++-
> 20 files changed, 462 insertions(+), 255 deletions(-)
> create mode 100644 arch/arm/dts/sun4i-a10-topwise-a721.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ab2d0da192..48ede8888e 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -539,7 +539,8 @@ dtb-$(CONFIG_MACH_SUN4I) += \
> sun4i-a10-olinuxino-lime.dtb \
> sun4i-a10-pcduino.dtb \
> sun4i-a10-pcduino2.dtb \
> - sun4i-a10-pov-protab2-ips9.dtb
> + sun4i-a10-pov-protab2-ips9.dtb \
> + sun4i-a10-topwise-a721.dtb
> dtb-$(CONFIG_MACH_SUN5I) += \
> sun5i-a10s-auxtek-t003.dtb \
> sun5i-a10s-auxtek-t004.dtb \
> diff --git a/arch/arm/dts/axp209.dtsi b/arch/arm/dts/axp209.dtsi
> index 0d9ff12bdf..ca240cd6f6 100644
> --- a/arch/arm/dts/axp209.dtsi
> +++ b/arch/arm/dts/axp209.dtsi
> @@ -53,7 +53,7 @@
> interrupt-controller;
> #interrupt-cells = <1>;
>
> - ac_power_supply: ac-power-supply {
> + ac_power_supply: ac-power {
> compatible = "x-powers,axp202-ac-power-supply";
> status = "disabled";
> };
> @@ -69,7 +69,7 @@
> #gpio-cells = <2>;
> };
>
> - battery_power_supply: battery-power-supply {
> + battery_power_supply: battery-power {
> compatible = "x-powers,axp209-battery-power-supply";
> status = "disabled";
> };
> @@ -112,7 +112,7 @@
> };
> };
>
> - usb_power_supply: usb-power-supply {
> + usb_power_supply: usb-power {
> compatible = "x-powers,axp202-usb-power-supply";
> status = "disabled";
> };
> diff --git a/arch/arm/dts/sun4i-a10-a1000.dts b/arch/arm/dts/sun4i-a10-a1000.dts
> index 6c254ec4c8..20f9ed2448 100644
> --- a/arch/arm/dts/sun4i-a10-a1000.dts
> +++ b/arch/arm/dts/sun4i-a10-a1000.dts
> @@ -60,15 +60,26 @@
> stdout-path = "serial0:115200n8";
> };
>
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> - red {
> + led-0 {
> label = "a1000:red:usr";
> gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>;
> };
>
> - blue {
> + led-1 {
> label = "a1000:blue:pwr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -125,7 +136,7 @@
> };
>
> &emac {
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> @@ -133,6 +144,20 @@
> status = "okay";
> };
>
> +&de {
> + status = "okay";
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> diff --git a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
> index 38a2c41349..816d534ac0 100644
> --- a/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
> +++ b/arch/arm/dts/sun4i-a10-ba10-tvbox.dts
> @@ -68,7 +68,7 @@
> };
>
> &emac {
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> diff --git a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
> index cf7b392dff..7426298888 100644
> --- a/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
> +++ b/arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts
> @@ -131,20 +131,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> -};
> -
> ®_usb0_vbus {
> status = "okay";
> };
> @@ -165,10 +151,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-cubieboard.dts b/arch/arm/dts/sun4i-a10-cubieboard.dts
> index 197a1f2b75..0645d60642 100644
> --- a/arch/arm/dts/sun4i-a10-cubieboard.dts
> +++ b/arch/arm/dts/sun4i-a10-cubieboard.dts
> @@ -75,12 +75,12 @@
> pinctrl-names = "default";
> pinctrl-0 = <&led_pins_cubieboard>;
>
> - blue {
> + led-0 {
> label = "cubieboard:blue:usr";
> gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>; /* LED1 */
> };
>
> - green {
> + led-1 {
> label = "cubieboard:green:usr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
> linux,default-trigger = "heartbeat";
> @@ -114,7 +114,7 @@
> };
>
> &emac {
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> @@ -184,12 +184,6 @@
> function = "gpio_out";
> drive-strength = <20>;
> };
> -
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> };
>
> ®_ahci_5v {
> @@ -254,9 +248,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
> index 896e27a087..63e77c05bf 100644
> --- a/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
> +++ b/arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts
> @@ -62,6 +62,7 @@
> brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> default-brightness-level = <8>;
> enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
> + power-supply = <®_vcc3v3>;
> };
>
> chosen {
> @@ -158,20 +159,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> -};
> -
> &pwm {
> pinctrl-names = "default";
> pinctrl-0 = <&pwm0_pin>;
> @@ -223,10 +210,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-hackberry.dts b/arch/arm/dts/sun4i-a10-hackberry.dts
> index cc988ccd5c..47dea09225 100644
> --- a/arch/arm/dts/sun4i-a10-hackberry.dts
> +++ b/arch/arm/dts/sun4i-a10-hackberry.dts
> @@ -80,7 +80,7 @@
> };
>
> &emac {
> - phy = <&phy0>;
> + phy-handle = <&phy0>;
> status = "okay";
> };
>
> diff --git a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
> index f63767cddd..bf2044bac4 100644
> --- a/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
> +++ b/arch/arm/dts/sun4i-a10-hyundai-a7hd.dts
> @@ -86,20 +86,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> -};
> -
> ®_usb0_vbus {
> status = "okay";
> };
> @@ -121,10 +107,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-inet1.dts b/arch/arm/dts/sun4i-a10-inet1.dts
> index 26d0c1d6a0..60e432a0ef 100644
> --- a/arch/arm/dts/sun4i-a10-inet1.dts
> +++ b/arch/arm/dts/sun4i-a10-inet1.dts
> @@ -62,6 +62,7 @@
> brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> default-brightness-level = <8>;
> enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
> + power-supply = <®_vcc3v3>;
> };
>
> chosen {
> @@ -164,20 +165,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> -};
> -
> &pwm {
> pinctrl-names = "default";
> pinctrl-0 = <&pwm0_pin>;
> @@ -233,10 +220,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> diff --git a/arch/arm/dts/sun4i-a10-inet97fv2.dts b/arch/arm/dts/sun4i-a10-inet97fv2.dts
> index 5d096528e7..76016f2ca2 100644
> --- a/arch/arm/dts/sun4i-a10-inet97fv2.dts
> +++ b/arch/arm/dts/sun4i-a10-inet97fv2.dts
> @@ -1,7 +1,7 @@
> /*
> * Copyright 2014 Open Source Support GmbH
> *
> - * David Lanzend�rfer <david.lanzendoerfer@o2s.ch>
> + * David Lanzendörfer <david.lanzendoerfer@o2s.ch>
> *
> * This file is dual-licensed: you can use it either under the terms
> * of the GPL or the X11 license, at your option. Note that this dual
> @@ -150,20 +150,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> -};
> -
> ®_dcdc2 {
> regulator-always-on;
> regulator-min-microvolt = <1000000>;
> @@ -209,10 +195,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
> index 221acd10f6..0a562b2cc5 100644
> --- a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
> +++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
> @@ -61,10 +61,6 @@
>
> gpio-keys {
> compatible = "gpio-keys-polled";
> - pinctrl-names = "default";
> - pinctrl-0 = <&key_pins_inet9f>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> poll-interval = <20>;
>
> left-joystick-left {
> @@ -72,7 +68,7 @@
> linux,code = <ABS_X>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <0xffffffff>; /* -1 */
> - gpios = <&pio 0 6 GPIO_ACTIVE_LOW>; /* PA6 */
> + gpios = <&pio 0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA6 */
> };
>
> left-joystick-right {
> @@ -80,7 +76,7 @@
> linux,code = <ABS_X>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <1>;
> - gpios = <&pio 0 5 GPIO_ACTIVE_LOW>; /* PA5 */
> + gpios = <&pio 0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA5 */
> };
>
> left-joystick-up {
> @@ -88,7 +84,7 @@
> linux,code = <ABS_Y>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <0xffffffff>; /* -1 */
> - gpios = <&pio 0 8 GPIO_ACTIVE_LOW>; /* PA8 */
> + gpios = <&pio 0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA8 */
> };
>
> left-joystick-down {
> @@ -96,7 +92,7 @@
> linux,code = <ABS_Y>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <1>;
> - gpios = <&pio 0 9 GPIO_ACTIVE_LOW>; /* PA9 */
> + gpios = <&pio 0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA9 */
> };
>
> right-joystick-left {
> @@ -104,7 +100,7 @@
> linux,code = <ABS_Z>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <0xffffffff>; /* -1 */
> - gpios = <&pio 0 1 GPIO_ACTIVE_LOW>; /* PA1 */
> + gpios = <&pio 0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA1 */
> };
>
> right-joystick-right {
> @@ -112,7 +108,7 @@
> linux,code = <ABS_Z>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <1>;
> - gpios = <&pio 0 0 GPIO_ACTIVE_LOW>; /* PA0 */
> + gpios = <&pio 0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA0 */
> };
>
> right-joystick-up {
> @@ -120,7 +116,7 @@
> linux,code = <ABS_RZ>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <0xffffffff>; /* -1 */
> - gpios = <&pio 0 3 GPIO_ACTIVE_LOW>; /* PA3 */
> + gpios = <&pio 0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA3 */
> };
>
> right-joystick-down {
> @@ -128,7 +124,7 @@
> linux,code = <ABS_RZ>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <1>;
> - gpios = <&pio 0 4 GPIO_ACTIVE_LOW>; /* PA4 */
> + gpios = <&pio 0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA4 */
> };
>
> dpad-left {
> @@ -136,7 +132,7 @@
> linux,code = <ABS_HAT0X>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <0xffffffff>; /* -1 */
> - gpios = <&pio 7 23 GPIO_ACTIVE_LOW>; /* PH23 */
> + gpios = <&pio 7 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH23 */
> };
>
> dpad-right {
> @@ -144,7 +140,7 @@
> linux,code = <ABS_HAT0X>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <1>;
> - gpios = <&pio 7 24 GPIO_ACTIVE_LOW>; /* PH24 */
> + gpios = <&pio 7 24 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH24 */
> };
>
> dpad-up {
> @@ -152,7 +148,7 @@
> linux,code = <ABS_HAT0Y>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <0xffffffff>; /* -1 */
> - gpios = <&pio 7 25 GPIO_ACTIVE_LOW>; /* PH25 */
> + gpios = <&pio 7 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH25 */
> };
>
> dpad-down {
> @@ -160,55 +156,55 @@
> linux,code = <ABS_HAT0Y>;
> linux,input-type = <EV_ABS>;
> linux,input-value = <1>;
> - gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
> + gpios = <&pio 7 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH26 */
> };
>
> x {
> label = "Button X";
> linux,code = <BTN_X>;
> - gpios = <&pio 0 16 GPIO_ACTIVE_LOW>; /* PA16 */
> + gpios = <&pio 0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA16 */
> };
>
> y {
> label = "Button Y";
> linux,code = <BTN_Y>;
> - gpios = <&pio 0 14 GPIO_ACTIVE_LOW>; /* PA14 */
> + gpios = <&pio 0 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA14 */
> };
>
> a {
> label = "Button A";
> linux,code = <BTN_A>;
> - gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
> + gpios = <&pio 0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA17 */
> };
>
> b {
> label = "Button B";
> linux,code = <BTN_B>;
> - gpios = <&pio 0 15 GPIO_ACTIVE_LOW>; /* PA15 */
> + gpios = <&pio 0 15 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA15 */
> };
>
> select {
> label = "Select Button";
> linux,code = <BTN_SELECT>;
> - gpios = <&pio 0 11 GPIO_ACTIVE_LOW>; /* PA11 */
> + gpios = <&pio 0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA11 */
> };
>
> start {
> label = "Start Button";
> linux,code = <BTN_START>;
> - gpios = <&pio 0 12 GPIO_ACTIVE_LOW>; /* PA12 */
> + gpios = <&pio 0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA12 */
> };
>
> top-left {
> label = "Top Left Button";
> linux,code = <BTN_TL>;
> - gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 */
> + gpios = <&pio 7 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PH22 */
> };
>
> top-right {
> label = "Top Right Button";
> linux,code = <BTN_TR>;
> - gpios = <&pio 0 13 GPIO_ACTIVE_LOW>; /* PA13 */
> + gpios = <&pio 0 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PA13 */
> };
> };
> };
> @@ -308,30 +304,6 @@
> status = "okay";
> };
>
> -&pio {
> - key_pins_inet9f: key-pins {
> - pins = "PA0", "PA1", "PA3", "PA4",
> - "PA5", "PA6", "PA8", "PA9",
> - "PA11", "PA12", "PA13",
> - "PA14", "PA15", "PA16", "PA17",
> - "PH22", "PH23", "PH24", "PH25", "PH26";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> -};
> -
> ®_dcdc2 {
> regulator-always-on;
> regulator-min-microvolt = <1000000>;
> @@ -377,10 +349,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
> index 80ecd78247..d4e319d16a 100644
> --- a/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
> +++ b/arch/arm/dts/sun4i-a10-itead-iteaduino-plus.dts
> @@ -58,7 +58,7 @@
> &emac {
> pinctrl-names = "default";
> pinctrl-0 = <&emac_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> diff --git a/arch/arm/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
> index 247fa27ef7..1aeb0bd551 100644
> --- a/arch/arm/dts/sun4i-a10-jesurun-q5.dts
> +++ b/arch/arm/dts/sun4i-a10-jesurun-q5.dts
> @@ -63,7 +63,7 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led {
> label = "q5:green:usr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* PH20 */
> };
> @@ -94,7 +94,7 @@
> };
>
> &emac {
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> diff --git a/arch/arm/dts/sun4i-a10-marsboard.dts b/arch/arm/dts/sun4i-a10-marsboard.dts
> index 0dbf695765..81fdb217d3 100644
> --- a/arch/arm/dts/sun4i-a10-marsboard.dts
> +++ b/arch/arm/dts/sun4i-a10-marsboard.dts
> @@ -62,22 +62,22 @@
> leds {
> compatible = "gpio-leds";
>
> - red1 {
> + led-0 {
> label = "marsboard:red1:usr";
> gpios = <&pio 1 5 GPIO_ACTIVE_HIGH>;
> };
>
> - red2 {
> + led-1 {
> label = "marsboard:red2:usr";
> gpios = <&pio 1 6 GPIO_ACTIVE_HIGH>;
> };
>
> - red3 {
> + led-2 {
> label = "marsboard:red3:usr";
> gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>;
> };
>
> - red4 {
> + led-3 {
> label = "marsboard:red4:usr";
> gpios = <&pio 1 8 GPIO_ACTIVE_HIGH>;
> };
> @@ -105,7 +105,7 @@
> };
>
> &emac {
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> @@ -148,14 +148,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> ®_usb1_vbus {
> status = "okay";
> };
> @@ -183,9 +175,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
> index b74a614965..83d283cf66 100644
> --- a/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
> +++ b/arch/arm/dts/sun4i-a10-olinuxino-lime.dts
> @@ -74,7 +74,7 @@
> pinctrl-names = "default";
> pinctrl-0 = <&led_pins_olinuxinolime>;
>
> - green {
> + led {
> label = "a10-olinuxino-lime:green:usr";
> gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -91,12 +91,11 @@
> /*
> * The A10-Lime is known to be unstable when running at 1008 MHz
> */
> - operating-points = <
> - /* kHz uV */
> - 912000 1350000
> - 864000 1300000
> - 624000 1250000
> - >;
> + operating-points =
> + /* kHz uV */
> + <912000 1350000>,
> + <864000 1300000>,
> + <624000 1250000>;
> };
>
> &de {
> @@ -112,7 +111,7 @@
> };
>
> &emac {
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> @@ -186,18 +185,6 @@
> function = "gpio_out";
> drive-strength = <20>;
> };
> -
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> };
>
> ®_ahci_5v {
> @@ -229,10 +216,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> diff --git a/arch/arm/dts/sun4i-a10-pcduino.dts b/arch/arm/dts/sun4i-a10-pcduino.dts
> index b97a0f2f20..1ac82376ba 100644
> --- a/arch/arm/dts/sun4i-a10-pcduino.dts
> +++ b/arch/arm/dts/sun4i-a10-pcduino.dts
> @@ -63,12 +63,12 @@
> leds {
> compatible = "gpio-leds";
>
> - tx {
> + led-0 {
> label = "pcduino:green:tx";
> gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
> };
>
> - rx {
> + led-1 {
> label = "pcduino:green:rx";
> gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
> };
> @@ -76,8 +76,6 @@
>
> gpio-keys {
> compatible = "gpio-keys";
> - #address-cells = <1>;
> - #size-cells = <0>;
>
> back {
> label = "Key Back";
> @@ -112,7 +110,7 @@
> };
>
> &emac {
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> status = "okay";
> };
>
> @@ -156,14 +154,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> #include "axp209.dtsi"
>
> ®_dcdc2 {
> @@ -203,9 +193,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */
> usb2_vbus-supply = <®_vcc5v0>; /* USB2 VBUS is always on */
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
> index 84b25be1ac..c325969476 100644
> --- a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
> +++ b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
> @@ -62,6 +62,7 @@
> brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> default-brightness-level = <8>;
> enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
> + power-supply = <®_vcc3v3>;
> };
>
> chosen {
> @@ -146,20 +147,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> -};
> -
> &pwm {
> pinctrl-names = "default";
> pinctrl-0 = <&pwm0_pin>;
> @@ -211,10 +198,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun4i-a10-topwise-a721.dts b/arch/arm/dts/sun4i-a10-topwise-a721.dts
> new file mode 100644
> index 0000000000..3628f12d25
> --- /dev/null
> +++ b/arch/arm/dts/sun4i-a10-topwise-a721.dts
> @@ -0,0 +1,242 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020 Pascal Roeleven <dev@pascalroeleven.nl>
> + */
> +
> +/dts-v1/;
> +#include "sun4i-a10.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/pwm/pwm.h>
> +
> +/ {
> + model = "Topwise A721";
> + compatible = "topwise,a721", "allwinner,sun4i-a10";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm 0 100000 PWM_POLARITY_INVERTED>;
> + power-supply = <®_vbat>;
> + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
> + brightness-levels = <0 30 40 50 60 70 80 90 100>;
> + default-brightness-level = <8>;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + panel {
> + compatible = "starry,kr070pe2t";
> + backlight = <&backlight>;
> + power-supply = <®_lcd_power>;
> +
> + port {
> + panel_input: endpoint {
> + remote-endpoint = <&tcon0_out_panel>;
> + };
> + };
> + };
> +
> + reg_lcd_power: reg-lcd-power {
> + compatible = "regulator-fixed";
> + regulator-name = "reg-lcd-power";
> + gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
> + enable-active-high;
> + };
> +
> + reg_vbat: reg-vbat {
> + compatible = "regulator-fixed";
> + regulator-name = "vbat";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + };
> +
> +};
> +
> +&codec {
> + status = "okay";
> +};
> +
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&de {
> + status = "okay";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + axp209: pmic@34 {
> + reg = <0x34>;
> + interrupts = <0>;
> + };
> +};
> +
> +#include "axp209.dtsi"
> +
> +&ac_power_supply {
> + status = "okay";
> +};
> +
> +&battery_power_supply {
> + status = "okay";
> +};
> +
> +&i2c1 {
> + status = "okay";
> +
> + accelerometer@4c {
> + compatible = "fsl,mma7660";
> + reg = <0x4c>;
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> +
> + touchscreen@38 {
> + compatible = "edt,edt-ft5406";
> + reg = <0x38>;
> + interrupt-parent = <&pio>;
> + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>;
> + touchscreen-size-x = <800>;
> + touchscreen-size-y = <480>;
> + vcc-supply = <®_vcc3v3>;
> + };
> +};
> +
> +&lradc {
> + vref-supply = <®_ldo2>;
> + status = "okay";
> +
> + button-571 {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + channel = <0>;
> + voltage = <571428>;
> + };
> +
> + button-761 {
> + label = "Volume Down";
> + linux,code = <KEY_VOLUMEDOWN>;
> + channel = <0>;
> + voltage = <761904>;
> + };
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH01 */
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&otg_sram {
> + status = "okay";
> +};
> +
> +&pio {
> + vcc-pb-supply = <®_vcc3v3>;
> + vcc-pf-supply = <®_vcc3v3>;
> + vcc-ph-supply = <®_vcc3v3>;
> +};
> +
> +&pwm {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0_pin>;
> + status = "okay";
> +};
> +
> +®_dcdc2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-name = "vdd-cpu";
> +};
> +
> +®_dcdc3 {
> + regulator-always-on;
> + regulator-min-microvolt = <1250000>;
> + regulator-max-microvolt = <1250000>;
> + regulator-name = "vdd-int-dll";
> +};
> +
> +®_ldo1 {
> + regulator-name = "vdd-rtc";
> +};
> +
> +®_ldo2 {
> + regulator-always-on;
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-name = "avcc";
> +};
> +
> +®_usb0_vbus {
> + status = "okay";
> +};
> +
> +®_usb1_vbus {
> + status = "okay";
> +};
> +
> +®_usb2_vbus {
> + status = "okay";
> +};
> +
> +&tcon0_out {
> + tcon0_out_panel: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&panel_input>;
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pb_pins>;
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usb_power_supply {
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_vbus-supply = <®_usb0_vbus>;
> + usb1_vbus-supply = <®_usb1_vbus>;
> + usb2_vbus-supply = <®_usb2_vbus>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun4i-a10.dtsi b/arch/arm/dts/sun4i-a10.dtsi
> index 3a1c6b45c9..51a6464aab 100644
> --- a/arch/arm/dts/sun4i-a10.dtsi
> +++ b/arch/arm/dts/sun4i-a10.dtsi
> @@ -115,13 +115,12 @@
> reg = <0x0>;
> clocks = <&ccu CLK_CPU>;
> clock-latency = <244144>; /* 8 32k periods */
> - operating-points = <
> + operating-points =
> /* kHz uV */
> - 1008000 1400000
> - 912000 1350000
> - 864000 1300000
> - 624000 1250000
> - >;
> + <1008000 1400000>,
> + <912000 1350000>,
> + <864000 1300000>,
> + <624000 1250000>;
> #cooling-cells = <2>;
> };
> };
> @@ -143,7 +142,7 @@
> trips {
> cpu_alert0: cpu-alert0 {
> /* milliCelsius */
> - temperature = <850000>;
> + temperature = <85000>;
> hysteresis = <2000>;
> type = "passive";
> };
> @@ -184,14 +183,34 @@
> status = "disabled";
> };
>
> + pmu {
> + compatible = "arm,cortex-a8-pmu";
> + interrupts = <3>;
> + };
> +
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
> + default-pool {
> + compatible = "shared-dma-pool";
> + size = <0x6000000>;
> + alloc-ranges = <0x40000000 0x10000000>;
> + reusable;
> + linux,cma-default;
> + };
> + };
> +
> soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> - sram-controller@1c00000 {
> - compatible = "allwinner,sun4i-a10-sram-controller";
> + system-control@1c00000 {
> + compatible = "allwinner,sun4i-a10-system-control";
> reg = <0x01c00000 0x30>;
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -224,6 +243,19 @@
> status = "disabled";
> };
> };
> +
> + sram_c: sram@1d00000 {
> + compatible = "mmio-sram";
> + reg = <0x01d00000 0xd0000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x01d00000 0xd0000>;
> +
> + ve_sram: sram-section@0 {
> + compatible = "allwinner,sun4i-a10-sram-c1";
> + reg = <0x000000 0x80000>;
> + };
> + };
> };
>
> dma: dma-controller@1c02000 {
> @@ -234,7 +266,7 @@
> #dma-cells = <2>;
> };
>
> - nfc: nand@1c03000 {
> + nfc: nand-controller@1c03000 {
> compatible = "allwinner,sun4i-a10-nand";
> reg = <0x01c03000 0x1000>;
> interrupts = <37>;
> @@ -309,6 +341,7 @@
> "tcon-ch0",
> "tcon-ch1";
> clock-output-names = "tcon0-pixel-clock";
> + #clock-cells = <0>;
> dmas = <&dma SUN4I_DMA_DEDICATED 14>;
>
> ports {
> @@ -358,6 +391,7 @@
> "tcon-ch0",
> "tcon-ch1";
> clock-output-names = "tcon1-pixel-clock";
> + #clock-cells = <0>;
> dmas = <&dma SUN4I_DMA_DEDICATED 15>;
>
> ports {
> @@ -394,6 +428,17 @@
> };
> };
>
> + video-codec@1c0e000 {
> + compatible = "allwinner,sun4i-a10-video-engine";
> + reg = <0x01c0e000 0x1000>;
> + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
> + <&ccu CLK_DRAM_VE>;
> + clock-names = "ahb", "mod", "ram";
> + resets = <&ccu RST_VE>;
> + interrupts = <53>;
> + allwinner,sram = <&ve_sram 1>;
> + };
> +
> mmc0: mmc@1c0f000 {
> compatible = "allwinner,sun4i-a10-mmc";
> reg = <0x01c0f000 0x1000>;
> @@ -450,13 +495,14 @@
> phy-names = "usb";
> extcon = <&usbphy 0>;
> allwinner,sram = <&otg_sram 1>;
> + dr_mode = "otg";
> status = "disabled";
> };
>
> usbphy: phy@1c13400 {
> #phy-cells = <1>;
> compatible = "allwinner,sun4i-a10-usb-phy";
> - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
> + reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
> reg-names = "phy_ctrl", "pmu1", "pmu2";
> clocks = <&ccu CLK_USB_PHY>;
> clock-names = "usb_phy";
> @@ -530,8 +576,6 @@
> };
>
> hdmi_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
> };
> };
> @@ -579,6 +623,16 @@
> status = "disabled";
> };
>
> + csi1: csi@1c1d000 {
> + compatible = "allwinner,sun4i-a10-csi1";
> + reg = <0x01c1d000 0x1000>;
> + interrupts = <43>;
> + clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
> + clock-names = "bus", "ram";
> + resets = <&ccu RST_CSI1>;
> + status = "disabled";
> + };
> +
> spi3: spi@1c1f000 {
> compatible = "allwinner,sun4i-a10-spi";
> reg = <0x01c1f000 0x1000>;
> @@ -625,6 +679,31 @@
> function = "can";
> };
>
> + /omit-if-no-ref/
> + csi1_8bits_pg_pins: csi1-8bits-pg-pins {
> + pins = "PG0", "PG2", "PG3", "PG4", "PG5",
> + "PG6", "PG7", "PG8", "PG9", "PG10",
> + "PG11";
> + function = "csi1";
> + };
> +
> + /omit-if-no-ref/
> + csi1_24bits_ph_pins: csi1-24bits-ph-pins {
> + pins = "PH0", "PH1", "PH2", "PH3", "PH4",
> + "PH5", "PH6", "PH7", "PH8", "PH9",
> + "PH10", "PH11", "PH12", "PH13", "PH14",
> + "PH15", "PH16", "PH17", "PH18", "PH19",
> + "PH20", "PH21", "PH22", "PH23", "PH24",
> + "PH25", "PH26", "PH27";
> + function = "csi1";
> + };
> +
> + /omit-if-no-ref/
> + csi1_clk_pg_pin: csi1-clk-pg-pin {
> + pins = "PG1";
> + function = "csi1";
> + };
> +
> emac_pins: emac0-pins {
> pins = "PA0", "PA1", "PA2",
> "PA3", "PA4", "PA5", "PA6",
> @@ -762,13 +841,20 @@
> timer@1c20c00 {
> compatible = "allwinner,sun4i-a10-timer";
> reg = <0x01c20c00 0x90>;
> - interrupts = <22>;
> + interrupts = <22>,
> + <23>,
> + <24>,
> + <25>,
> + <67>,
> + <68>;
> clocks = <&osc24M>;
> };
>
> wdt: watchdog@1c20c90 {
> compatible = "allwinner,sun4i-a10-wdt";
> reg = <0x01c20c90 0x10>;
> + interrupts = <24>;
> + clocks = <&osc24M>;
> };
>
> rtc: rtc@1c20d00 {
> @@ -1001,6 +1087,27 @@
> status = "disabled";
> };
>
> + mali: gpu@1c40000 {
> + compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
> + reg = <0x01c40000 0x10000>;
> + interrupts = <69>,
> + <70>,
> + <71>,
> + <72>,
> + <73>;
> + interrupt-names = "gp",
> + "gpmmu",
> + "pp0",
> + "ppmmu0",
> + "pmu";
> + clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
> + clock-names = "bus", "core";
> + resets = <&ccu RST_GPU>;
> +
> + assigned-clocks = <&ccu CLK_GPU>;
> + assigned-clock-rates = <384000000>;
> + };
> +
> fe0: display-frontend@1e00000 {
> compatible = "allwinner,sun4i-a10-display-frontend";
> reg = <0x01e00000 0x20000>;
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 04/12] ARM: dts: sun7i: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 04/12] ARM: dts: sun7i: " Samuel Holland
@ 2022-05-06 0:39 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-06 0:39 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:23 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Copy the devicetree source for the A20 SoC and all existing boards
> verbatim from the Linux v5.18-rc1 tag.
>
> This commit also adds the following new board devicetrees:
> - sun7i-a20-haoyu-marsboard.dts
> - sun7i-a20-linutronix-testbox-v2.dts
> - sun7i-a20-olinuxino-lime-emmc.dts
>
> This update includes changes to the USB PHY detection GPIO properties
> which are needed to convert that driver to use the DM GPIO framework.
This looks alright: compared the files to the Linux tree, also skimmed
over the changes, they look harmless. Boot tested on BananaPi M1:
Ethernet and USB work.
There is one thing, though:
the move of the PHY child node into an MDIO subnode also affects the
U-Boot-only sun7i-a20-m5.dts. As this DT gets build with every A20
build, there is now a dtc warning with every A20 board:
===============
arch/arm/dts/sun7i-a20-m5.dtb: Warning (reg_format):
/soc/ethernet@1c50000/ethernet-phy@1:reg: property has invalid length
(4 bytes) (#address-cells == 2, #size-cells == 1)
arch/arm/dts/sun7i-a20-m5.dtb: Warning (avoid_default_addr_size):
/soc/ethernet@1c50000/ethernet-phy@1: Relying on default #address-cells
value arch/arm/dts/sun7i-a20-m5.dtb: Warning (avoid_default_addr_size):
/soc/ethernet@1c50000/ethernet-phy@1: Relying on default #size-cells
value ===============
Below simple patch fixes that and lets buildman pass (on the whole
series):
===============
diff --git a/arch/arm/dts/sun7i-a20-m5.dts
b/arch/arm/dts/sun7i-a20-m5.dts index 6de52c7c314..cfbc50d9e55 100644
--- a/arch/arm/dts/sun7i-a20-m5.dts
+++ b/arch/arm/dts/sun7i-a20-m5.dts
@@ -39,7 +39,9 @@
phy = <&phy1>;
phy-mode = "mii";
status = "okay";
+};
+&gmac_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
===============
In case there is nothing else, I will just apply this when merging.
With that fixed:
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/Makefile | 3 +
> arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 16 +-
> arch/arm/dts/sun7i-a20-bananapi.dts | 41 ++-
> arch/arm/dts/sun7i-a20-bananapro.dts | 16 +-
> arch/arm/dts/sun7i-a20-cubieboard2.dts | 28 +-
> arch/arm/dts/sun7i-a20-cubietruck.dts | 20 +-
> arch/arm/dts/sun7i-a20-haoyu-marsboard.dts | 182 +++++++++++++
> arch/arm/dts/sun7i-a20-hummingbird.dts | 21 +-
> arch/arm/dts/sun7i-a20-i12-tvbox.dts | 16 +-
> arch/arm/dts/sun7i-a20-icnova-swac.dts | 15 +-
> arch/arm/dts/sun7i-a20-itead-ibox.dts | 8 +-
> arch/arm/dts/sun7i-a20-lamobo-r1.dts | 16 +-
> .../dts/sun7i-a20-linutronix-testbox-v2.dts | 47 ++++
> arch/arm/dts/sun7i-a20-m3.dts | 14 +-
> arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 14 +-
> arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 30 ++-
> .../arm/dts/sun7i-a20-olinuxino-lime-emmc.dts | 32 +++
> arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 32 +--
> arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 46 ++--
> arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 32 +--
> arch/arm/dts/sun7i-a20-orangepi-mini.dts | 28 +-
> arch/arm/dts/sun7i-a20-orangepi.dts | 26 +-
> arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 32 +--
> arch/arm/dts/sun7i-a20-pcduino3.dts | 28 +-
> arch/arm/dts/sun7i-a20-wexler-tab7200.dts | 13 +-
> arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts | 24 +-
> arch/arm/dts/sun7i-a20.dtsi | 254 ++++++++++++++++--
> 27 files changed, 707 insertions(+), 327 deletions(-)
> create mode 100644 arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
> create mode 100644 arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
> create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 48ede8888e..7120d6a3aa 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -583,11 +583,13 @@ dtb-$(CONFIG_MACH_SUN7I) += \
> sun7i-a20-bananapro.dtb \
> sun7i-a20-cubieboard2.dtb \
> sun7i-a20-cubietruck.dtb \
> + sun7i-a20-haoyu-marsboard.dtb \
> sun7i-a20-hummingbird.dtb \
> sun7i-a20-i12-tvbox.dtb \
> sun7i-a20-icnova-swac.dtb \
> sun7i-a20-itead-ibox.dtb \
> sun7i-a20-lamobo-r1.dtb \
> + sun7i-a20-linutronix-testbox-v2.dtb \
> sun7i-a20-m3.dtb \
> sun7i-a20-m5.dtb \
> sun7i-a20-mk808c.dtb \
> @@ -595,6 +597,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
> sun7i-a20-olimex-som204-evb.dtb \
> sun7i-a20-olimex-som204-evb-emmc.dtb \
> sun7i-a20-olinuxino-lime.dtb \
> + sun7i-a20-olinuxino-lime-emmc.dtb \
> sun7i-a20-olinuxino-lime2.dtb \
> sun7i-a20-olinuxino-lime2-emmc.dtb \
> sun7i-a20-olinuxino-micro.dtb \
> diff --git a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
> index 4dbcad1343..caa935ca4f 100644
> --- a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
> +++ b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts
> @@ -74,12 +74,12 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led-0 {
> label = "bananapi-m1-plus:green:usr";
> gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
> };
>
> - pwr {
> + led-1 {
> label = "bananapi-m1-plus:pwr:usr";
> gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -129,14 +129,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii-id";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -171,6 +167,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-bananapi.dts b/arch/arm/dts/sun7i-a20-bananapi.dts
> index 33040c43bc..46ecf9db23 100644
> --- a/arch/arm/dts/sun7i-a20-bananapi.dts
> +++ b/arch/arm/dts/sun7i-a20-bananapi.dts
> @@ -77,7 +77,7 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led {
> label = "bananapi:green:usr";
> gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
> };
> @@ -104,16 +104,15 @@
>
> &cpu0 {
> cpu-supply = <®_dcdc2>;
> - operating-points = <
> + operating-points =
> /* kHz uV */
> - 960000 1400000
> - 912000 1400000
> - 864000 1350000
> - 720000 1250000
> - 528000 1150000
> - 312000 1100000
> - 144000 1050000
> - >;
> + <960000 1400000>,
> + <912000 1400000>,
> + <864000 1350000>,
> + <720000 1250000>,
> + <528000 1150000>,
> + <312000 1100000>,
> + <144000 1050000>;
> };
>
> &de {
> @@ -131,14 +130,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii-id";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -171,6 +166,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -246,12 +247,6 @@
> "SPI-MISO", "SPI-CE1", "",
> "IO-6", "IO-3", "IO-2", "IO-0", "", "", "", "",
> "", "", "", "", "", "", "", "";
> -
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> };
>
> #include "axp209.dtsi"
> @@ -329,9 +324,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-bananapro.dts b/arch/arm/dts/sun7i-a20-bananapro.dts
> index 8a75545e22..e22f0e8bb1 100644
> --- a/arch/arm/dts/sun7i-a20-bananapro.dts
> +++ b/arch/arm/dts/sun7i-a20-bananapro.dts
> @@ -63,12 +63,12 @@
> leds {
> compatible = "gpio-leds";
>
> - blue {
> + led-0 {
> label = "bananapro:blue:usr";
> gpios = <&pio 6 2 GPIO_ACTIVE_HIGH>;
> };
>
> - green {
> + led-1 {
> label = "bananapro:green:usr";
> gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
> };
> @@ -109,14 +109,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii-id";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -143,6 +139,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-cubieboard2.dts b/arch/arm/dts/sun7i-a20-cubieboard2.dts
> index 200685b0b1..e35e6990c4 100644
> --- a/arch/arm/dts/sun7i-a20-cubieboard2.dts
> +++ b/arch/arm/dts/sun7i-a20-cubieboard2.dts
> @@ -75,12 +75,12 @@
> leds {
> compatible = "gpio-leds";
>
> - blue {
> + led-0 {
> label = "cubieboard2:blue:usr";
> gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
> };
>
> - green {
> + led-1 {
> label = "cubieboard2:green:usr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
> };
> @@ -115,13 +115,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -161,6 +157,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &ohci0 {
> status = "okay";
> };
> @@ -173,14 +175,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> ®_ahci_5v {
> status = "okay";
> };
> @@ -236,9 +230,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun7i-a20-cubietruck.dts b/arch/arm/dts/sun7i-a20-cubietruck.dts
> index 46a9f4669e..52160e3683 100644
> --- a/arch/arm/dts/sun7i-a20-cubietruck.dts
> +++ b/arch/arm/dts/sun7i-a20-cubietruck.dts
> @@ -75,22 +75,22 @@
> leds {
> compatible = "gpio-leds";
>
> - blue {
> + led-0 {
> label = "cubietruck:blue:usr";
> gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
> };
>
> - orange {
> + led-1 {
> label = "cubietruck:orange:usr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
> };
>
> - white {
> + led-2 {
> label = "cubietruck:white:usr";
> gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>;
> };
>
> - green {
> + led-3 {
> label = "cubietruck:green:usr";
> gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
> };
> @@ -150,13 +150,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii-id";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -194,6 +190,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-haoyu-marsboard.dts b/arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
> new file mode 100644
> index 0000000000..097e479c27
> --- /dev/null
> +++ b/arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
> @@ -0,0 +1,182 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2021 Conley Lee
> + * Conley Lee <conleylee@foxmail.com>
> + */
> +
> +/dts-v1/;
> +#include "sun7i-a20.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "HAOYU Electronics Marsboard A20";
> + compatible = "haoyu,a20-marsboard", "allwinner,sun7i-a20";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +};
> +
> +&ahci {
> + target-supply = <®_ahci_5v>;
> + status = "okay";
> +};
> +
> +&codec {
> + status = "okay";
> +};
> +
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&de {
> + status = "okay";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&gmac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
> + phy-handle = <&phy0>;
> + phy-mode = "mii";
> + status = "okay";
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + axp209: pmic@34 {
> + reg = <0x34>;
> + interrupt-parent = <&nmi_intc>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 7 10 GPIO_ACTIVE_LOW>; /* PH10 */
> + status = "okay";
> +};
> +
> +&gmac_mdio {
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&otg_sram {
> + status = "okay";
> +};
> +
> +&pio {
> + gmac_txerr: gmac-txerr-pin {
> + pins = "PA17";
> + function = "gmac";
> + };
> +};
> +
> +®_ahci_5v {
> + status = "okay";
> +};
> +
> +#include "axp209.dtsi"
> +
> +&ac_power_supply {
> + status = "okay";
> +};
> +
> +®_dcdc2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1450000>;
> + regulator-name = "vdd-cpu";
> +};
> +
> +®_dcdc3 {
> + regulator-always-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-name = "vdd-int-dll";
> +};
> +
> +®_ldo1 {
> + regulator-name = "vdd-rtc";
> +};
> +
> +®_ldo2 {
> + regulator-always-on;
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-name = "avcc";
> +};
> +
> +®_usb1_vbus {
> + status = "okay";
> +};
> +
> +®_usb2_vbus {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pb_pins>;
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb1_vbus-supply = <®_usb1_vbus>;
> + usb2_vbus-supply = <®_usb2_vbus>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun7i-a20-hummingbird.dts b/arch/arm/dts/sun7i-a20-hummingbird.dts
> index fd0153f656..3def2a3305 100644
> --- a/arch/arm/dts/sun7i-a20-hummingbird.dts
> +++ b/arch/arm/dts/sun7i-a20-hummingbird.dts
> @@ -100,19 +100,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii";
> phy-supply = <®_gmac_vdd>;
> - /* phy reset config */
> - snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
> - snps,reset-active-low;
> - /* wait 1s after reset, otherwise fail to read phy id */
> - snps,reset-delays-us = <0 10000 1000000>;
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -146,6 +137,16 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
> + reset-assert-us = <10000>;
> + /* wait 1s after reset, otherwise fail to read phy id */
> + reset-deassert-us = <1000000>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v0>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/dts/sun7i-a20-i12-tvbox.dts
> index 5f1c4f573d..b21ddd0ec1 100644
> --- a/arch/arm/dts/sun7i-a20-i12-tvbox.dts
> +++ b/arch/arm/dts/sun7i-a20-i12-tvbox.dts
> @@ -62,12 +62,12 @@
> leds {
> compatible = "gpio-leds";
>
> - red {
> + led-0 {
> label = "i12_tvbox:red:usr";
> gpios = <&pio 7 9 GPIO_ACTIVE_LOW>;
> };
>
> - blue {
> + led-1 {
> label = "i12_tvbox:blue:usr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
> };
> @@ -115,14 +115,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -145,6 +141,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-icnova-swac.dts b/arch/arm/dts/sun7i-a20-icnova-swac.dts
> index 949494730a..413505f45a 100644
> --- a/arch/arm/dts/sun7i-a20-icnova-swac.dts
> +++ b/arch/arm/dts/sun7i-a20-icnova-swac.dts
> @@ -49,7 +49,8 @@
>
> / {
> model = "ICnova-A20 SWAC";
> - compatible = "swac,icnova-a20-swac", "incircuit,icnova-a20", "allwinner,sun7i-a20";
> + compatible = "incircuit,icnova-a20-swac", "incircuit,icnova-a20",
> + "allwinner,sun7i-a20";
>
> aliases {
> serial0 = &uart0;
> @@ -75,13 +76,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -98,6 +95,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-itead-ibox.dts b/arch/arm/dts/sun7i-a20-itead-ibox.dts
> index b90a7607d0..8ff83016ff 100644
> --- a/arch/arm/dts/sun7i-a20-itead-ibox.dts
> +++ b/arch/arm/dts/sun7i-a20-itead-ibox.dts
> @@ -53,13 +53,13 @@
> pinctrl-names = "default";
> pinctrl-0 = <&led_pins_itead_core>;
>
> - green {
> + led-0 {
> label = "itead_core:green:usr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> };
>
> - blue {
> + led-1 {
> label = "itead_core:blue:usr";
> gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -97,10 +97,12 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> status = "okay";
> +};
>
> +&gmac_mdio {
> phy1: ethernet-phy@1 {
> reg = <1>;
> };
> diff --git a/arch/arm/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/dts/sun7i-a20-lamobo-r1.dts
> index f91e1bee44..97518afe46 100644
> --- a/arch/arm/dts/sun7i-a20-lamobo-r1.dts
> +++ b/arch/arm/dts/sun7i-a20-lamobo-r1.dts
> @@ -75,7 +75,7 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led {
> label = "lamobo_r1:green:usr";
> gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
> };
> @@ -123,8 +123,6 @@
> phy-mode = "rgmii";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
> - /delete-property/#address-cells;
> - /delete-property/#size-cells;
>
> fixed-link {
> speed = <1000>;
> @@ -229,14 +227,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> #include "axp209.dtsi"
>
> &ac_power_supply {
> @@ -322,9 +312,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_usb0_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts b/arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
> new file mode 100644
> index 0000000000..da5a2eea4c
> --- /dev/null
> +++ b/arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
> @@ -0,0 +1,47 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright 2020 Linutronix GmbH
> + * Author: Benedikt Spranger <b.spranger@linutronix.de>
> + */
> +
> +/dts-v1/;
> +#include "sun7i-a20-lamobo-r1.dts"
> +
> +/ {
> + model = "Lamobo R1";
> + compatible = "linutronix,testbox-v2", "lamobo,lamobo-r1", "allwinner,sun7i-a20";
> +
> + leds {
> + led-opto1 {
> + label = "lamobo_r1:opto:powerswitch";
> + gpios = <&pio 7 3 GPIO_ACTIVE_HIGH>;
> + };
> +
> + led-opto2 {
> + label = "lamobo_r1:opto:relay";
> + gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + eeprom: eeprom@50 {
> + compatible = "atmel,24c08";
> + reg = <0x50>;
> + status = "okay";
> + };
> +
> + atecc508a@60 {
> + compatible = "atmel,atecc508a";
> + reg = <0x60>;
> + };
> +};
> +
> +&can0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&can_ph_pins>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun7i-a20-m3.dts b/arch/arm/dts/sun7i-a20-m3.dts
> index b8a1aaaf39..f161d52388 100644
> --- a/arch/arm/dts/sun7i-a20-m3.dts
> +++ b/arch/arm/dts/sun7i-a20-m3.dts
> @@ -64,7 +64,7 @@
> leds {
> compatible = "gpio-leds";
>
> - blue {
> + led {
> label = "m3:blue:usr";
> gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
> };
> @@ -82,13 +82,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -111,6 +107,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
> index f0e6a96e57..f05ee32bc9 100644
> --- a/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
> +++ b/arch/arm/dts/sun7i-a20-olimex-som-evb.dts
> @@ -75,7 +75,7 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led {
> label = "a20-olimex-som-evb:green:usr";
> gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -111,13 +111,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -202,6 +198,12 @@
> };
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
> index 823aabce04..54af6c1807 100644
> --- a/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
> +++ b/arch/arm/dts/sun7i-a20-olimex-som204-evb.dts
> @@ -46,19 +46,19 @@
> leds {
> compatible = "gpio-leds";
>
> - stat {
> + led-0 {
> label = "a20-som204-evb:green:stat";
> gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> };
>
> - led1 {
> + led-1 {
> label = "a20-som204-evb:green:led1";
> gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> };
>
> - led2 {
> + led-2 {
> label = "a20-som204-evb:yellow:led2";
> gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -105,18 +105,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy3>;
> + phy-handle = <&phy3>;
> phy-mode = "rgmii";
> phy-supply = <®_vcc3v3>;
> -
> - snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
> - snps,reset-active-low;
> - snps,reset-delays-us = <0 10000 1000000>;
> status = "okay";
> -
> - phy3: ethernet-phy@3 {
> - reg = <3>;
> - };
> };
>
> &hdmi {
> @@ -161,6 +153,16 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy3: ethernet-phy@3 {
> + reg = <3>;
> + reset-gpios = <&pio 0 17 GPIO_ACTIVE_LOW>; /* PA17 */
> + reset-assert-us = <10000>;
> + /* wait 1s after reset, otherwise fail to read phy id */
> + reset-deassert-us = <1000000>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -314,8 +316,8 @@
> };
>
> &usbphy {
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
> new file mode 100644
> index 0000000000..033cab3443
> --- /dev/null
> +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2020 Olimex Ltd.
> + * Author: Stefan Mavrodiev <stefan@olimex.com>
> + */
> +
> +#include "sun7i-a20-olinuxino-lime.dts"
> +
> +/ {
> + model = "Olimex A20-OLinuXino-LIME-eMMC";
> + compatible = "olimex,a20-olinuxino-lime-emmc", "allwinner,sun7i-a20";
> +
> + mmc2_pwrseq: pwrseq {
> + compatible = "mmc-pwrseq-emmc";
> + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&mmc2 {
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + non-removable;
> + mmc-pwrseq = <&mmc2_pwrseq>;
> + status = "okay";
> +
> + emmc: emmc@0 {
> + reg = <0>;
> + compatible = "mmc-card";
> + broken-hpi;
> + };
> +};
> diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
> index 5e411194bf..92938d0222 100644
> --- a/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
> +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime.dts
> @@ -78,7 +78,7 @@
> pinctrl-names = "default";
> pinctrl-0 = <&led_pins_olinuxinolime>;
>
> - green {
> + led {
> label = "a20-olinuxino-lime:green:usr";
> gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -106,13 +106,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -149,6 +145,12 @@
> };
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -174,18 +176,6 @@
> function = "gpio_out";
> drive-strength = <20>;
> };
> -
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> };
>
> ®_ahci_5v {
> @@ -217,10 +207,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
> index 996201665b..ecb91fb899 100644
> --- a/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
> +++ b/arch/arm/dts/sun7i-a20-olinuxino-lime2.dts
> @@ -75,7 +75,7 @@
> pinctrl-names = "default";
> pinctrl-0 = <&led_pins_olinuxinolime>;
>
> - green {
> + led {
> label = "a20-olinuxino-lime2:green:usr";
> gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -111,13 +111,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii-id";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -154,6 +150,12 @@
> vref-supply = <®_vcc3v0>;
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -174,23 +176,17 @@
> };
>
> &pio {
> + vcc-pa-supply = <®_vcc3v3>;
> + vcc-pc-supply = <®_vcc3v3>;
> + vcc-pe-supply = <®_ldo3>;
> + vcc-pf-supply = <®_vcc3v3>;
> + vcc-pg-supply = <®_ldo4>;
> +
> led_pins_olinuxinolime: led-pins {
> pins = "PH2";
> function = "gpio_out";
> drive-strength = <20>;
> };
> -
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> };
>
> ®_ahci_5v {
> @@ -200,6 +196,14 @@
>
> #include "axp209.dtsi"
>
> +&ac_power_supply {
> + status = "okay";
> +};
> +
> +&battery_power_supply {
> + status = "okay";
> +};
> +
> ®_dcdc2 {
> regulator-always-on;
> regulator-min-microvolt = <1000000>;
> @@ -267,10 +271,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
> index 840ae1194a..a1b89b2a29 100644
> --- a/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
> +++ b/arch/arm/dts/sun7i-a20-olinuxino-micro.dts
> @@ -82,7 +82,7 @@
> pinctrl-names = "default";
> pinctrl-0 = <&led_pins_olinuxino>;
>
> - green {
> + led {
> label = "a20-olinuxino-micro:green:usr";
> gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>;
> default-state = "on";
> @@ -118,13 +118,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>, <&gmac_txerr>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -215,6 +211,12 @@
> };
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -252,18 +254,6 @@
> function = "gpio_out";
> drive-strength = <20>;
> };
> -
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> - usb0_vbus_detect_pin: usb0-vbus-detect-pin {
> - pins = "PH5";
> - function = "gpio_in";
> - bias-pull-down;
> - };
> };
>
> #include "axp209.dtsi"
> @@ -355,10 +345,8 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> - usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> + usb0_vbus_det-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PH5 */
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-orangepi-mini.dts b/arch/arm/dts/sun7i-a20-orangepi-mini.dts
> index 15881081ca..84efa01e7c 100644
> --- a/arch/arm/dts/sun7i-a20-orangepi-mini.dts
> +++ b/arch/arm/dts/sun7i-a20-orangepi-mini.dts
> @@ -75,12 +75,12 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led-0 {
> label = "orangepi:green:usr";
> gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
> };
>
> - blue {
> + led-1 {
> label = "orangepi:blue:usr";
> gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>; /* PH25 */
> };
> @@ -120,14 +120,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -158,6 +154,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -176,14 +178,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> ®_dcdc2 {
> regulator-always-on;
> regulator-min-microvolt = <1000000>;
> @@ -239,9 +233,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-orangepi.dts b/arch/arm/dts/sun7i-a20-orangepi.dts
> index d64de2e73a..5d77f1d981 100644
> --- a/arch/arm/dts/sun7i-a20-orangepi.dts
> +++ b/arch/arm/dts/sun7i-a20-orangepi.dts
> @@ -64,7 +64,7 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led {
> label = "orangepi:green:usr";
> gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>; /* PH24 */
> };
> @@ -96,14 +96,10 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -124,6 +120,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -135,14 +137,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> ®_dcdc2 {
> regulator-always-on;
> regulator-min-microvolt = <1000000>;
> @@ -198,9 +192,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
> index 205eaae44a..e40ecb48d7 100644
> --- a/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
> +++ b/arch/arm/dts/sun7i-a20-pcduino3-nano.dts
> @@ -1,5 +1,5 @@
> /*
> - * Copyright 2015 Adam Sampson <ats@offog.org>
> + * Copyright 2015-2020 Adam Sampson <ats@offog.org>
> *
> * This file is dual-licensed: you can use it either under the terms
> * of the GPL or the X11 license, at your option. Note that this dual
> @@ -72,14 +72,12 @@
> leds {
> compatible = "gpio-leds";
>
> - /* Marked "LED3" on the PCB. */
> - usr1 {
> + led-3 {
> label = "pcduino3-nano:green:usr1";
> gpios = <&pio 7 16 GPIO_ACTIVE_LOW>; /* PH16 */
> };
>
> - /* Marked "LED4" on the PCB. */
> - usr2 {
> + led-4 {
> label = "pcduino3-nano:green:usr2";
> gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */
> };
> @@ -114,13 +112,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii-id";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &hdmi {
> @@ -149,6 +143,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -168,14 +168,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> ®_ahci_5v {
> gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
> status = "okay";
> @@ -226,9 +218,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb1_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
> index a72ed4318d..4f8d55d3ba 100644
> --- a/arch/arm/dts/sun7i-a20-pcduino3.dts
> +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
> @@ -64,12 +64,12 @@
> leds {
> compatible = "gpio-leds";
>
> - tx {
> + led-0 {
> label = "pcduino3:green:tx";
> gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
> };
>
> - rx {
> + led-1 {
> label = "pcduino3:green:rx";
> gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
> };
> @@ -122,13 +122,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_mii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "mii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -149,6 +145,12 @@
> status = "okay";
> };
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -168,14 +170,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> ®_ahci_5v {
> gpio = <&pio 7 2 GPIO_ACTIVE_HIGH>;
> status = "okay";
> @@ -226,9 +220,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
> index ffade253d1..fef02fcbbd 100644
> --- a/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
> +++ b/arch/arm/dts/sun7i-a20-wexler-tab7200.dts
> @@ -64,6 +64,7 @@
> brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
> default-brightness-level = <8>;
> enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
> + power-supply = <®_vcc3v3>;
> };
>
> chosen {
> @@ -156,14 +157,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> &pwm {
> pinctrl-names = "default";
> pinctrl-0 = <&pwm0_pin>;
> @@ -223,9 +216,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
> index c27e56091f..3bfae98f3c 100644
> --- a/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
> +++ b/arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts
> @@ -81,13 +81,9 @@
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_rgmii_pins>;
> - phy = <&phy1>;
> + phy-handle = <&phy1>;
> phy-mode = "rgmii";
> status = "okay";
> -
> - phy1: ethernet-phy@1 {
> - reg = <1>;
> - };
> };
>
> &i2c0 {
> @@ -110,6 +106,12 @@
>
> #include "axp209.dtsi"
>
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> @@ -145,14 +147,6 @@
> status = "okay";
> };
>
> -&pio {
> - usb0_id_detect_pin: usb0-id-detect-pin {
> - pins = "PH4";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -};
> -
> ®_dcdc2 {
> regulator-always-on;
> regulator-min-microvolt = <1000000>;
> @@ -206,9 +200,7 @@
> };
>
> &usbphy {
> - pinctrl-names = "default";
> - pinctrl-0 = <&usb0_id_detect_pin>;
> - usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
> + usb0_id_det-gpios = <&pio 7 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH4 */
> usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_usb0_vbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> diff --git a/arch/arm/dts/sun7i-a20.dtsi b/arch/arm/dts/sun7i-a20.dtsi
> index 641a8fa6d4..5574299685 100644
> --- a/arch/arm/dts/sun7i-a20.dtsi
> +++ b/arch/arm/dts/sun7i-a20.dtsi
> @@ -47,6 +47,7 @@
> #include <dt-bindings/dma/sun4i-a10.h>
> #include <dt-bindings/clock/sun7i-a20-ccu.h>
> #include <dt-bindings/reset/sun4i-a10-ccu.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>
> / {
> interrupt-parent = <&gic>;
> @@ -105,16 +106,15 @@
> reg = <0>;
> clocks = <&ccu CLK_CPU>;
> clock-latency = <244144>; /* 8 32k periods */
> - operating-points = <
> + operating-points =
> /* kHz uV */
> - 960000 1400000
> - 912000 1400000
> - 864000 1300000
> - 720000 1200000
> - 528000 1100000
> - 312000 1000000
> - 144000 1000000
> - >;
> + <960000 1400000>,
> + <912000 1400000>,
> + <864000 1300000>,
> + <720000 1200000>,
> + <528000 1100000>,
> + <312000 1000000>,
> + <144000 1000000>;
> #cooling-cells = <2>;
> };
>
> @@ -124,22 +124,21 @@
> reg = <1>;
> clocks = <&ccu CLK_CPU>;
> clock-latency = <244144>; /* 8 32k periods */
> - operating-points = <
> + operating-points =
> /* kHz uV */
> - 960000 1400000
> - 912000 1400000
> - 864000 1300000
> - 720000 1200000
> - 528000 1100000
> - 312000 1000000
> - 144000 1000000
> - >;
> + <960000 1400000>,
> + <912000 1400000>,
> + <864000 1300000>,
> + <720000 1200000>,
> + <528000 1100000>,
> + <312000 1000000>,
> + <144000 1000000>;
> #cooling-cells = <2>;
> };
> };
>
> thermal-zones {
> - cpu_thermal {
> + cpu-thermal {
> /* milliseconds */
> polling-delay-passive = <250>;
> polling-delay = <1000>;
> @@ -180,7 +179,7 @@
> default-pool {
> compatible = "shared-dma-pool";
> size = <0x6000000>;
> - alloc-ranges = <0x4a000000 0x6000000>;
> + alloc-ranges = <0x40000000 0x10000000>;
> reusable;
> linux,cma-default;
> };
> @@ -333,7 +332,7 @@
> #dma-cells = <2>;
> };
>
> - nfc: nand@1c03000 {
> + nfc: nand-controller@1c03000 {
> compatible = "allwinner,sun4i-a10-nand";
> reg = <0x01c03000 0x1000>;
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> @@ -376,6 +375,16 @@
> num-cs = <1>;
> };
>
> + csi0: csi@1c09000 {
> + compatible = "allwinner,sun7i-a20-csi0";
> + reg = <0x01c09000 0x1000>;
> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
> + clock-names = "bus", "isp", "ram";
> + resets = <&ccu RST_CSI0>;
> + status = "disabled";
> + };
> +
> emac: ethernet@1c0b000 {
> compatible = "allwinner,sun4i-a10-emac";
> reg = <0x01c0b000 0x1000>;
> @@ -394,11 +403,12 @@
> };
>
> tcon0: lcd-controller@1c0c000 {
> - compatible = "allwinner,sun7i-a20-tcon";
> + compatible = "allwinner,sun7i-a20-tcon0",
> + "allwinner,sun7i-a20-tcon";
> reg = <0x01c0c000 0x1000>;
> interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> - resets = <&ccu RST_TCON0>;
> - reset-names = "lcd";
> + resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
> + reset-names = "lcd", "lvds";
> clocks = <&ccu CLK_AHB_LCD0>,
> <&ccu CLK_TCON0_CH0>,
> <&ccu CLK_TCON0_CH1>;
> @@ -406,6 +416,7 @@
> "tcon-ch0",
> "tcon-ch1";
> clock-output-names = "tcon0-pixel-clock";
> + #clock-cells = <0>;
> dmas = <&dma SUN4I_DMA_DEDICATED 14>;
>
> ports {
> @@ -443,7 +454,8 @@
> };
>
> tcon1: lcd-controller@1c0d000 {
> - compatible = "allwinner,sun7i-a20-tcon";
> + compatible = "allwinner,sun7i-a20-tcon1",
> + "allwinner,sun7i-a20-tcon";
> reg = <0x01c0d000 0x1000>;
> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> resets = <&ccu RST_TCON1>;
> @@ -455,6 +467,7 @@
> "tcon-ch0",
> "tcon-ch1";
> clock-output-names = "tcon1-pixel-clock";
> + #clock-cells = <0>;
> dmas = <&dma SUN4I_DMA_DEDICATED 15>;
>
> ports {
> @@ -586,13 +599,14 @@
> phy-names = "usb";
> extcon = <&usbphy 0>;
> allwinner,sram = <&otg_sram 1>;
> + dr_mode = "otg";
> status = "disabled";
> };
>
> usbphy: phy@1c13400 {
> #phy-cells = <1>;
> compatible = "allwinner,sun7i-a20-usb-phy";
> - reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
> + reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
> reg-names = "phy_ctrl", "pmu1", "pmu2";
> clocks = <&ccu CLK_USB_PHY>;
> clock-names = "usb_phy";
> @@ -716,6 +730,17 @@
> status = "disabled";
> };
>
> + csi1: csi@1c1d000 {
> + compatible = "allwinner,sun7i-a20-csi1",
> + "allwinner,sun4i-a10-csi1";
> + reg = <0x01c1d000 0x1000>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
> + clock-names = "bus", "ram";
> + resets = <&ccu RST_CSI1>;
> + status = "disabled";
> + };
> +
> spi3: spi@1c1f000 {
> compatible = "allwinner,sun4i-a10-spi";
> reg = <0x01c1f000 0x1000>;
> @@ -751,21 +776,70 @@
> #interrupt-cells = <3>;
> #gpio-cells = <3>;
>
> + /omit-if-no-ref/
> + can_pa_pins: can-pa-pins {
> + pins = "PA16", "PA17";
> + function = "can";
> + };
> +
> + /omit-if-no-ref/
> can_ph_pins: can-ph-pins {
> pins = "PH20", "PH21";
> function = "can";
> };
>
> + /omit-if-no-ref/
> clk_out_a_pin: clk-out-a-pin {
> pins = "PI12";
> function = "clk_out_a";
> };
>
> + /omit-if-no-ref/
> clk_out_b_pin: clk-out-b-pin {
> pins = "PI13";
> function = "clk_out_b";
> };
>
> + /omit-if-no-ref/
> + csi0_8bits_pins: csi-8bits-pins {
> + pins = "PE0", "PE2", "PE3", "PE4", "PE5",
> + "PE6", "PE7", "PE8", "PE9", "PE10",
> + "PE11";
> + function = "csi0";
> + };
> +
> + /omit-if-no-ref/
> + csi0_clk_pin: csi-clk-pin {
> + pins = "PE1";
> + function = "csi0";
> + };
> +
> + /omit-if-no-ref/
> + csi1_8bits_pg_pins: csi1-8bits-pg-pins {
> + pins = "PG0", "PG2", "PG3", "PG4", "PG5",
> + "PG6", "PG7", "PG8", "PG9", "PG10",
> + "PG11";
> + function = "csi1";
> + };
> +
> + /omit-if-no-ref/
> + csi1_24bits_ph_pins: csi1-24bits-ph-pins {
> + pins = "PH0", "PH1", "PH2", "PH3", "PH4",
> + "PH5", "PH6", "PH7", "PH8", "PH9",
> + "PH10", "PH11", "PH12", "PH13", "PH14",
> + "PH15", "PH16", "PH17", "PH18", "PH19",
> + "PH20", "PH21", "PH22", "PH23", "PH24",
> + "PH25", "PH26", "PH27";
> + function = "csi1";
> + };
> +
> + /omit-if-no-ref/
> + csi1_clk_pg_pin: csi1-clk-pg-pin {
> + pins = "PG1";
> + function = "csi1";
> + };
> +
> + /omit-if-no-ref/
> emac_pa_pins: emac-pa-pins {
> pins = "PA0", "PA1", "PA2",
> "PA3", "PA4", "PA5", "PA6",
> @@ -775,6 +849,17 @@
> function = "emac";
> };
>
> + /omit-if-no-ref/
> + emac_ph_pins: emac-ph-pins {
> + pins = "PH8", "PH9", "PH10", "PH11",
> + "PH14", "PH15", "PH16", "PH17",
> + "PH18", "PH19", "PH20", "PH21",
> + "PH22", "PH23", "PH24", "PH25",
> + "PH26";
> + function = "emac";
> + };
> +
> + /omit-if-no-ref/
> gmac_mii_pins: gmac-mii-pins {
> pins = "PA0", "PA1", "PA2",
> "PA3", "PA4", "PA5", "PA6",
> @@ -784,6 +869,7 @@
> function = "gmac";
> };
>
> + /omit-if-no-ref/
> gmac_rgmii_pins: gmac-rgmii-pins {
> pins = "PA0", "PA1", "PA2",
> "PA3", "PA4", "PA5", "PA6",
> @@ -798,46 +884,69 @@
> drive-strength = <40>;
> };
>
> + /omit-if-no-ref/
> i2c0_pins: i2c0-pins {
> pins = "PB0", "PB1";
> function = "i2c0";
> };
>
> + /omit-if-no-ref/
> i2c1_pins: i2c1-pins {
> pins = "PB18", "PB19";
> function = "i2c1";
> };
>
> + /omit-if-no-ref/
> i2c2_pins: i2c2-pins {
> pins = "PB20", "PB21";
> function = "i2c2";
> };
>
> + /omit-if-no-ref/
> i2c3_pins: i2c3-pins {
> pins = "PI0", "PI1";
> function = "i2c3";
> };
>
> + /omit-if-no-ref/
> ir0_rx_pin: ir0-rx-pin {
> pins = "PB4";
> function = "ir0";
> };
>
> + /omit-if-no-ref/
> ir0_tx_pin: ir0-tx-pin {
> pins = "PB3";
> function = "ir0";
> };
>
> + /omit-if-no-ref/
> ir1_rx_pin: ir1-rx-pin {
> pins = "PB23";
> function = "ir1";
> };
>
> + /omit-if-no-ref/
> ir1_tx_pin: ir1-tx-pin {
> pins = "PB22";
> function = "ir1";
> };
>
> + /omit-if-no-ref/
> + lcd_lvds0_pins: lcd-lvds0-pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> + "PD5", "PD6", "PD7", "PD8", "PD9";
> + function = "lvds0";
> + };
> +
> + /omit-if-no-ref/
> + lcd_lvds1_pins: lcd-lvds1-pins {
> + pins = "PD10", "PD11", "PD12", "PD13", "PD14",
> + "PD15", "PD16", "PD17", "PD18", "PD19";
> + function = "lvds1";
> + };
> +
> + /omit-if-no-ref/
> mmc0_pins: mmc0-pins {
> pins = "PF0", "PF1", "PF2",
> "PF3", "PF4", "PF5";
> @@ -846,6 +955,7 @@
> bias-pull-up;
> };
>
> + /omit-if-no-ref/
> mmc2_pins: mmc2-pins {
> pins = "PC6", "PC7", "PC8",
> "PC9", "PC10", "PC11";
> @@ -854,6 +964,7 @@
> bias-pull-up;
> };
>
> + /omit-if-no-ref/
> mmc3_pins: mmc3-pins {
> pins = "PI4", "PI5", "PI6",
> "PI7", "PI8", "PI9";
> @@ -862,127 +973,206 @@
> bias-pull-up;
> };
>
> + /omit-if-no-ref/
> ps2_0_pins: ps2-0-pins {
> pins = "PI20", "PI21";
> function = "ps2";
> };
>
> + /omit-if-no-ref/
> ps2_1_ph_pins: ps2-1-ph-pins {
> pins = "PH12", "PH13";
> function = "ps2";
> };
>
> + /omit-if-no-ref/
> pwm0_pin: pwm0-pin {
> pins = "PB2";
> function = "pwm";
> };
>
> + /omit-if-no-ref/
> pwm1_pin: pwm1-pin {
> pins = "PI3";
> function = "pwm";
> };
>
> + /omit-if-no-ref/
> spdif_tx_pin: spdif-tx-pin {
> pins = "PB13";
> function = "spdif";
> bias-pull-up;
> };
>
> + /omit-if-no-ref/
> spi0_pi_pins: spi0-pi-pins {
> pins = "PI11", "PI12", "PI13";
> function = "spi0";
> };
>
> + /omit-if-no-ref/
> spi0_cs0_pi_pin: spi0-cs0-pi-pin {
> pins = "PI10";
> function = "spi0";
> };
>
> + /omit-if-no-ref/
> spi0_cs1_pi_pin: spi0-cs1-pi-pin {
> pins = "PI14";
> function = "spi0";
> };
>
> + /omit-if-no-ref/
> spi1_pi_pins: spi1-pi-pins {
> pins = "PI17", "PI18", "PI19";
> function = "spi1";
> };
>
> + /omit-if-no-ref/
> spi1_cs0_pi_pin: spi1-cs0-pi-pin {
> pins = "PI16";
> function = "spi1";
> };
>
> + /omit-if-no-ref/
> spi2_pb_pins: spi2-pb-pins {
> pins = "PB15", "PB16", "PB17";
> function = "spi2";
> };
>
> + /omit-if-no-ref/
> spi2_cs0_pb_pin: spi2-cs0-pb-pin {
> pins = "PB14";
> function = "spi2";
> };
>
> + /omit-if-no-ref/
> spi2_pc_pins: spi2-pc-pins {
> pins = "PC20", "PC21", "PC22";
> function = "spi2";
> };
>
> + /omit-if-no-ref/
> spi2_cs0_pc_pin: spi2-cs0-pc-pin {
> pins = "PC19";
> function = "spi2";
> };
>
> + /omit-if-no-ref/
> uart0_pb_pins: uart0-pb-pins {
> pins = "PB22", "PB23";
> function = "uart0";
> };
>
> + /omit-if-no-ref/
> + uart0_pf_pins: uart0-pf-pins {
> + pins = "PF2", "PF4";
> + function = "uart0";
> + };
> +
> + /omit-if-no-ref/
> + uart1_pa_pins: uart1-pa-pins {
> + pins = "PA10", "PA11";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
> + pins = "PA12", "PA13";
> + function = "uart1";
> + };
> +
> + /omit-if-no-ref/
> + uart2_pa_pins: uart2-pa-pins {
> + pins = "PA2", "PA3";
> + function = "uart2";
> + };
> +
> + /omit-if-no-ref/
> + uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
> + pins = "PA0", "PA1";
> + function = "uart2";
> + };
> +
> + /omit-if-no-ref/
> uart2_pi_pins: uart2-pi-pins {
> pins = "PI18", "PI19";
> function = "uart2";
> };
>
> + /omit-if-no-ref/
> uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
> pins = "PI16", "PI17";
> function = "uart2";
> };
>
> + /omit-if-no-ref/
> uart3_pg_pins: uart3-pg-pins {
> pins = "PG6", "PG7";
> function = "uart3";
> };
>
> + /omit-if-no-ref/
> uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
> pins = "PG8", "PG9";
> function = "uart3";
> };
>
> + /omit-if-no-ref/
> uart3_ph_pins: uart3-ph-pins {
> pins = "PH0", "PH1";
> function = "uart3";
> };
>
> + /omit-if-no-ref/
> + uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
> + pins = "PH2", "PH3";
> + function = "uart3";
> + };
> +
> + /omit-if-no-ref/
> uart4_pg_pins: uart4-pg-pins {
> pins = "PG10", "PG11";
> function = "uart4";
> };
>
> + /omit-if-no-ref/
> uart4_ph_pins: uart4-ph-pins {
> pins = "PH4", "PH5";
> function = "uart4";
> };
>
> + /omit-if-no-ref/
> + uart5_ph_pins: uart5-ph-pins {
> + pins = "PH6", "PH7";
> + function = "uart5";
> + };
> +
> + /omit-if-no-ref/
> uart5_pi_pins: uart5-pi-pins {
> pins = "PI10", "PI11";
> function = "uart5";
> };
>
> + /omit-if-no-ref/
> + uart6_pa_pins: uart6-pa-pins {
> + pins = "PA12", "PA13";
> + function = "uart6";
> + };
> +
> + /omit-if-no-ref/
> uart6_pi_pins: uart6-pi-pins {
> pins = "PI12", "PI13";
> function = "uart6";
> };
>
> + /omit-if-no-ref/
> + uart7_pa_pins: uart7-pa-pins {
> + pins = "PA14", "PA15";
> + function = "uart7";
> + };
> +
> + /omit-if-no-ref/
> uart7_pi_pins: uart7-pi-pins {
> pins = "PI20", "PI21";
> function = "uart7";
> @@ -1004,6 +1194,8 @@
> wdt: watchdog@1c20c90 {
> compatible = "allwinner,sun4i-a10-wdt";
> reg = <0x01c20c90 0x10>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> rtc: rtc@1c20d00 {
> @@ -1326,8 +1518,12 @@
> snps,fixed-burst;
> snps,force_sf_dma_mode;
> status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> +
> + gmac_mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> };
>
> hstimer@1c60000 {
> @@ -1341,7 +1537,7 @@
> };
>
> gic: interrupt-controller@1c81000 {
> - compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + compatible = "arm,gic-400";
> reg = <0x01c81000 0x1000>,
> <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 06/12] ARM: dts: sun9i: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 06/12] ARM: dts: sun9i: " Samuel Holland
@ 2022-05-20 13:39 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-20 13:39 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:25 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> Copy the devicetree source for the A80 SoC and all existing boards
> verbatim from the Linux v5.18-rc1 tag.
>
> This update should not impact any existing U-Boot functionality.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Compared against the respective kernel tree's files, they are identical.
Change-wise the "dumb-vga-dac" compatible is dropped from the Cubieboard,
but the others are supported since v4.12, so that should not matter.
Also the new IR compatible string requires a v5.4 kernel, but since that's
not really a critical component, this is probably fine as well.
So with that:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks!
Andre
> ---
>
> arch/arm/dts/sun9i-a80-cubieboard4.dts | 67 ++++++---
> arch/arm/dts/sun9i-a80-optimus.dts | 50 ++++++-
> arch/arm/dts/sun9i-a80.dtsi | 195 +++++++++++++++----------
> 3 files changed, 212 insertions(+), 100 deletions(-)
>
> diff --git a/arch/arm/dts/sun9i-a80-cubieboard4.dts b/arch/arm/dts/sun9i-a80-cubieboard4.dts
> index 85da85faf8..c8ca8cb7f5 100644
> --- a/arch/arm/dts/sun9i-a80-cubieboard4.dts
> +++ b/arch/arm/dts/sun9i-a80-cubieboard4.dts
> @@ -63,12 +63,12 @@
> leds {
> compatible = "gpio-leds";
>
> - green {
> + led-0 {
> label = "cubieboard4:green:usr";
> gpios = <&pio 7 17 GPIO_ACTIVE_HIGH>; /* PH17 */
> };
>
> - red {
> + led-1 {
> label = "cubieboard4:red:usr";
> gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
> };
> @@ -87,33 +87,25 @@
> };
>
> vga-dac {
> - compatible = "corpro,gm7123", "adi,adv7123", "dumb-vga-dac";
> + compatible = "corpro,gm7123", "adi,adv7123";
> vdd-supply = <®_dcdc1>;
> - #address-cells = <1>;
> - #size-cells = <0>;
>
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - vga_dac_in: endpoint@0 {
> - reg = <0>;
> + vga_dac_in: endpoint {
> remote-endpoint = <&tcon0_out_vga>;
> };
> };
>
> port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - vga_dac_out: endpoint@0 {
> - reg = <0>;
> + vga_dac_out: endpoint {
> remote-endpoint = <&vga_con_in>;
> };
> };
> @@ -133,12 +125,27 @@
> status = "okay";
> };
>
> +&gmac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_rgmii_pins>;
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> + phy-supply = <®_cldo1>;
> + status = "okay";
> +};
> +
> &i2c3 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c3_pins>;
> status = "okay";
> };
>
> +&mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> @@ -183,10 +190,26 @@
> clocks = <&ac100_rtc 0>;
> };
>
> +&pio {
> + vcc-pa-supply = <®_ldo_io1>;
> + vcc-pb-supply = <®_aldo2>;
> + vcc-pc-supply = <®_dcdc1>;
> + vcc-pd-supply = <®_dc1sw>;
> + vcc-pe-supply = <®_eldo2>;
> + vcc-pf-supply = <®_dcdc1>;
> + vcc-pg-supply = <®_ldo_io0>;
> + vcc-ph-supply = <®_dcdc1>;
> +};
> +
> &r_ir {
> status = "okay";
> };
>
> +&r_pio {
> + vcc-pl-supply = <®_dldo2>;
> + vcc-pm-supply = <®_eldo3>;
> +};
> +
> &r_rsb {
> status = "okay";
>
> @@ -217,6 +240,10 @@
> /* unused */
> };
>
> + reg_dc1sw: dc1sw {
> + regulator-name = "vcc-pd";
> + };
> +
> reg_dc5ldo: dc5ldo {
> regulator-always-on;
> regulator-min-microvolt = <800000>;
> @@ -271,7 +298,6 @@
> };
>
> reg_dldo2: dldo2 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pl";
> @@ -290,14 +316,12 @@
> };
>
> reg_eldo3: eldo3 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pm-codec-io1";
> };
>
> reg_ldo_io0: ldo_io0 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pg";
> @@ -385,6 +409,14 @@
> */
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> + /*
> + * The PHY requires 20ms after all voltages
> + * are applied until core logic is ready and
> + * 30ms after the reset pin is de-asserted.
> + * Set a 100ms delay to account for PMIC
> + * ramp time and board traces.
> + */
> + regulator-enable-ramp-delay = <100000>;
> regulator-name = "vcc-gmac-phy";
> };
>
> @@ -464,8 +496,7 @@
> };
>
> &tcon0_out {
> - tcon0_out_vga: endpoint@0 {
> - reg = <0>;
> + tcon0_out_vga: endpoint {
> remote-endpoint = <&vga_dac_in>;
> };
> };
> diff --git a/arch/arm/dts/sun9i-a80-optimus.dts b/arch/arm/dts/sun9i-a80-optimus.dts
> index 58a199b0e4..5c3580d712 100644
> --- a/arch/arm/dts/sun9i-a80-optimus.dts
> +++ b/arch/arm/dts/sun9i-a80-optimus.dts
> @@ -82,7 +82,7 @@
>
> reg_usb1_vbus: usb1-vbus {
> compatible = "regulator-fixed";
> - pinctrl-names = "default";
> + regulator-name = "usb1-vbus";
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> enable-active-high;
> @@ -91,7 +91,7 @@
>
> reg_usb3_vbus: usb3-vbus {
> compatible = "regulator-fixed";
> - pinctrl-names = "default";
> + regulator-name = "usb3-vbus";
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> enable-active-high;
> @@ -120,6 +120,21 @@
> status = "okay";
> };
>
> +&gmac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_rgmii_pins>;
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> + phy-supply = <®_cldo1>;
> + status = "okay";
> +};
> +
> +&mdio {
> + phy1: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> @@ -172,10 +187,26 @@
> clocks = <&ac100_rtc 0>;
> };
>
> +&pio {
> + vcc-pa-supply = <®_ldo_io1>;
> + vcc-pb-supply = <®_aldo2>;
> + vcc-pc-supply = <®_dcdc1>;
> + vcc-pd-supply = <®_dcdc1>;
> + vcc-pe-supply = <®_eldo2>;
> + vcc-pf-supply = <®_dcdc1>;
> + vcc-pg-supply = <®_ldo_io0>;
> + vcc-ph-supply = <®_dcdc1>;
> +};
> +
> &r_ir {
> status = "okay";
> };
>
> +&r_pio {
> + vcc-pl-supply = <®_dldo2>;
> + vcc-pm-supply = <®_eldo3>;
> +};
> +
> &r_rsb {
> status = "okay";
>
> @@ -213,6 +244,10 @@
> regulator-name = "vdd-cpus-09-usbh";
> };
>
> + dc1sw {
> + /* unused */
> + };
> +
> reg_dcdc1: dcdc1 {
> regulator-always-on;
> regulator-min-microvolt = <3000000>;
> @@ -260,7 +295,6 @@
> };
>
> reg_dldo2: dldo2 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pl";
> @@ -279,14 +313,12 @@
> };
>
> reg_eldo3: eldo3 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pm-codec-io1";
> };
>
> reg_ldo_io0: ldo_io0 {
> - regulator-always-on;
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3000000>;
> regulator-name = "vcc-pg";
> @@ -374,6 +406,14 @@
> */
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> + /*
> + * The PHY requires 20ms after all voltages
> + * are applied until core logic is ready and
> + * 30ms after the reset pin is de-asserted.
> + * Set a 100ms delay to account for PMIC
> + * ramp time and board traces.
> + */
> + regulator-enable-ramp-delay = <100000>;
> regulator-name = "vcc-gmac-phy";
> };
>
> diff --git a/arch/arm/dts/sun9i-a80.dtsi b/arch/arm/dts/sun9i-a80.dtsi
> index 25591d6883..ce4fa6706d 100644
> --- a/arch/arm/dts/sun9i-a80.dtsi
> +++ b/arch/arm/dts/sun9i-a80.dtsi
> @@ -56,6 +56,10 @@
> #size-cells = <2>;
> interrupt-parent = <&gic>;
>
> + aliases {
> + ethernet0 = &gmac;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -183,6 +187,37 @@
> clock-output-names = "osc32k";
> };
>
> + /*
> + * The following two are dummy clocks, placeholders
> + * used in the gmac_tx clock. The gmac driver will
> + * choose one parent depending on the PHY interface
> + * mode, using clk_set_rate auto-reparenting.
> + *
> + * The actual TX clock rate is not controlled by the
> + * gmac_tx clock.
> + */
> + mii_phy_tx_clk: mii_phy_tx_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <25000000>;
> + clock-output-names = "mii_phy_tx";
> + };
> +
> + gmac_int_tx_clk: gmac_int_tx_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + clock-output-names = "gmac_int_tx";
> + };
> +
> + gmac_tx_clk: clk@800030 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun7i-a20-gmac-clk";
> + reg = <0x00800030 0x4>;
> + clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
> + clock-output-names = "gmac_tx";
> + };
> +
> cpus_clk: clk@8001410 {
> compatible = "allwinner,sun9i-a80-cpus-clk";
> reg = <0x08001410 0x4>;
> @@ -254,7 +289,7 @@
> status = "disabled";
> };
>
> - soc {
> + soc@20000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -283,6 +318,27 @@
> };
> };
>
> + gmac: ethernet@830000 {
> + compatible = "allwinner,sun7i-a20-gmac";
> + reg = <0x00830000 0x1054>;
> + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
> + clock-names = "stmmaceth", "allwinner_gmac_tx";
> + resets = <&ccu RST_BUS_GMAC>;
> + reset-names = "stmmaceth";
> + snps,pbl = <2>;
> + snps,fixed-burst;
> + snps,force_sf_dma_mode;
> + status = "disabled";
> +
> + mdio: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> ehci0: usb@a00000 {
> compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
> reg = <0x00a00000 0x100>;
> @@ -331,16 +387,16 @@
> usbphy2: phy@a01800 {
> compatible = "allwinner,sun9i-a80-usb-phy";
> reg = <0x00a01800 0x4>;
> - clocks = <&usb_clocks CLK_USB1_HSIC>,
> + clocks = <&usb_clocks CLK_USB1_PHY>,
> <&usb_clocks CLK_USB_HSIC>,
> - <&usb_clocks CLK_USB1_PHY>;
> - clock-names = "hsic_480M",
> + <&usb_clocks CLK_USB1_HSIC>;
> + clock-names = "phy",
> "hsic_12M",
> - "phy";
> - resets = <&usb_clocks RST_USB1_HSIC>,
> - <&usb_clocks RST_USB1_PHY>;
> - reset-names = "hsic",
> - "phy";
> + "hsic_480M";
> + resets = <&usb_clocks RST_USB1_PHY>,
> + <&usb_clocks RST_USB1_HSIC>;
> + reset-names = "phy",
> + "hsic";
> status = "disabled";
> #phy-cells = <0>;
> /* usb1 is always used with HSIC */
> @@ -373,16 +429,16 @@
> usbphy3: phy@a02800 {
> compatible = "allwinner,sun9i-a80-usb-phy";
> reg = <0x00a02800 0x4>;
> - clocks = <&usb_clocks CLK_USB2_HSIC>,
> + clocks = <&usb_clocks CLK_USB2_PHY>,
> <&usb_clocks CLK_USB_HSIC>,
> - <&usb_clocks CLK_USB2_PHY>;
> - clock-names = "hsic_480M",
> + <&usb_clocks CLK_USB2_HSIC>;
> + clock-names = "phy",
> "hsic_12M",
> - "phy";
> - resets = <&usb_clocks RST_USB2_HSIC>,
> - <&usb_clocks RST_USB2_PHY>;
> - reset-names = "hsic",
> - "phy";
> + "hsic_480M";
> + resets = <&usb_clocks RST_USB2_PHY>,
> + <&usb_clocks RST_USB2_HSIC>;
> + reset-names = "phy",
> + "hsic";
> status = "disabled";
> #phy-cells = <0>;
> };
> @@ -401,6 +457,15 @@
> reg = <0x01700000 0x100>;
> };
>
> + crypto: crypto@1c02000 {
> + compatible = "allwinner,sun9i-a80-crypto";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&ccu RST_BUS_SS>;
> + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
> + clock-names = "bus", "mod";
> + };
> +
> mmc0: mmc@1c0f000 {
> compatible = "allwinner,sun9i-a80-mmc";
> reg = <0x01c0f000 0x1000>;
> @@ -465,9 +530,7 @@
> compatible = "allwinner,sun9i-a80-mmc-config-clk";
> reg = <0x01c13000 0x10>;
> clocks = <&ccu CLK_BUS_MMC>;
> - clock-names = "ahb";
> resets = <&ccu RST_BUS_MMC>;
> - reset-names = "ahb";
> #clock-cells = <1>;
> #reset-cells = <1>;
> clock-output-names = "mmc0_config", "mmc1_config",
> @@ -475,7 +538,7 @@
> };
>
> gic: interrupt-controller@1c41000 {
> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + compatible = "arm,gic-400";
> reg = <0x01c41000 0x1000>,
> <0x01c42000 0x2000>,
> <0x01c44000 0x2000>,
> @@ -544,12 +607,9 @@
> #size-cells = <0>;
>
> fe0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - fe0_out_deu0: endpoint@0 {
> - reg = <0>;
> + fe0_out_deu0: endpoint {
> remote-endpoint = <&deu0_in_fe0>;
> };
> };
> @@ -571,12 +631,9 @@
> #size-cells = <0>;
>
> fe1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - fe1_out_deu1: endpoint@0 {
> - reg = <0>;
> + fe1_out_deu1: endpoint {
> remote-endpoint = <&deu1_in_fe1>;
> };
> };
> @@ -614,12 +671,9 @@
> };
>
> be0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - be0_out_drc0: endpoint@0 {
> - reg = <0>;
> + be0_out_drc0: endpoint {
> remote-endpoint = <&drc0_in_be0>;
> };
> };
> @@ -657,12 +711,9 @@
> };
>
> be1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - be1_out_drc1: endpoint@0 {
> - reg = <0>;
> + be1_out_drc1: endpoint {
> remote-endpoint = <&drc1_in_be1>;
> };
> };
> @@ -686,12 +737,9 @@
> #size-cells = <0>;
>
> deu0_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - deu0_in_fe0: endpoint@0 {
> - reg = <0>;
> + deu0_in_fe0: endpoint {
> remote-endpoint = <&fe0_out_deu0>;
> };
> };
> @@ -731,12 +779,9 @@
> #size-cells = <0>;
>
> deu1_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - deu1_in_fe1: endpoint@0 {
> - reg = <0>;
> + deu1_in_fe1: endpoint {
> remote-endpoint = <&fe1_out_deu1>;
> };
> };
> @@ -776,23 +821,17 @@
> #size-cells = <0>;
>
> drc0_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - drc0_in_be0: endpoint@0 {
> - reg = <0>;
> + drc0_in_be0: endpoint {
> remote-endpoint = <&be0_out_drc0>;
> };
> };
>
> drc0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - drc0_out_tcon0: endpoint@0 {
> - reg = <0>;
> + drc0_out_tcon0: endpoint {
> remote-endpoint = <&tcon0_in_drc0>;
> };
> };
> @@ -816,23 +855,17 @@
> #size-cells = <0>;
>
> drc1_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - drc1_in_be1: endpoint@0 {
> - reg = <0>;
> + drc1_in_be1: endpoint {
> remote-endpoint = <&be1_out_drc1>;
> };
> };
>
> drc1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
>
> - drc1_out_tcon1: endpoint@0 {
> - reg = <0>;
> + drc1_out_tcon1: endpoint {
> remote-endpoint = <&tcon1_in_drc1>;
> };
> };
> @@ -845,28 +878,28 @@
> interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
> clock-names = "ahb", "tcon-ch0";
> - resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
> - reset-names = "lcd", "edp";
> + resets = <&ccu RST_BUS_LCD0>,
> + <&ccu RST_BUS_EDP>,
> + <&ccu RST_BUS_LVDS>;
> + reset-names = "lcd",
> + "edp",
> + "lvds";
> clock-output-names = "tcon0-pixel-clock";
> + #clock-cells = <0>;
>
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> tcon0_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - tcon0_in_drc0: endpoint@0 {
> - reg = <0>;
> + tcon0_in_drc0: endpoint {
> remote-endpoint = <&drc0_out_tcon0>;
> };
> };
>
> tcon0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
> };
> };
> @@ -886,19 +919,14 @@
> #size-cells = <0>;
>
> tcon1_in: port@0 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <0>;
>
> - tcon1_in_drc1: endpoint@0 {
> - reg = <0>;
> + tcon1_in_drc1: endpoint {
> remote-endpoint = <&drc1_out_tcon1>;
> };
> };
>
> tcon1_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
> };
> };
> @@ -930,6 +958,7 @@
> compatible = "allwinner,sun6i-a31-wdt";
> reg = <0x06000ca0 0x20>;
> interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> pio: pinctrl@6000800 {
> @@ -945,9 +974,20 @@
> gpio-controller;
> interrupt-controller;
> #interrupt-cells = <3>;
> - #size-cells = <0>;
> #gpio-cells = <3>;
>
> + gmac_rgmii_pins: gmac-rgmii-pins {
> + pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5",
> + "PA7", "PA8", "PA9", "PA10", "PA12",
> + "PA13", "PA15", "PA16", "PA17";
> + function = "gmac";
> + /*
> + * data lines in RGMII mode use DDR mode
> + * and need a higher signal drive strength
> + */
> + drive-strength = <40>;
> + };
> +
> i2c3_pins: i2c3-pins {
> pins = "PG10", "PG11";
> function = "i2c3";
> @@ -1126,6 +1166,7 @@
> compatible = "allwinner,sun6i-a31-wdt";
> reg = <0x08001000 0x20>;
> interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> prcm@8001400 {
> @@ -1148,7 +1189,7 @@
> };
>
> r_ir: ir@8002000 {
> - compatible = "allwinner,sun5i-a13-ir";
> + compatible = "allwinner,sun6i-a31-ir";
> interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> pinctrl-names = "default";
> pinctrl-0 = <&r_ir_pins>;
> @@ -1196,7 +1237,7 @@
> };
> };
>
> - r_rsb: i2c@8003400 {
> + r_rsb: rsb@8003400 {
> compatible = "allwinner,sun8i-a23-rsb";
> reg = <0x08003400 0x400>;
> interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/12] ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 07/12] ARM: dts: sun8i: A83T: " Samuel Holland
@ 2022-05-20 13:48 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-20 13:48 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:26 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> Copy the devicetree source for the A83T SoC and all existing boards
> from the Linux v5.18-rc1 tag.
>
> To maintain ABI compatibility with existing LTS kernels, one change
> moving some IP blocks to the r_intc interrupt controller is excluded.
> This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
>
> As with the other SoCs, updates of note include adding detection GPIO
> properties in the USB PHY nodes.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Compared the files against the kernel tree, apart from the r_intc change
they are identical.
Change-wise there is a different timer compatible string, requiring Linux
v5.4 at least. This should not be fatal, since we have the arch timer, though.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/axp81x.dtsi | 15 +-
> .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 +
> arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 55 +++-
> arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 77 ++++-
> arch/arm/dts/sun8i-a83t-tbs-a711.dts | 101 +++++-
> arch/arm/dts/sun8i-a83t.dtsi | 311 ++++++++++++++++--
> 6 files changed, 515 insertions(+), 56 deletions(-)
>
> diff --git a/arch/arm/dts/axp81x.dtsi b/arch/arm/dts/axp81x.dtsi
> index 043c717dce..b93387b0c1 100644
> --- a/arch/arm/dts/axp81x.dtsi
> +++ b/arch/arm/dts/axp81x.dtsi
> @@ -48,6 +48,11 @@
> interrupt-controller;
> #interrupt-cells = <1>;
>
> + ac_power_supply: ac-power {
> + compatible = "x-powers,axp813-ac-power-supply";
> + status = "disabled";
> + };
> +
> axp_adc: adc {
> compatible = "x-powers,axp813-adc";
> #io-channel-cells = <1>;
> @@ -58,18 +63,18 @@
> gpio-controller;
> #gpio-cells = <2>;
>
> - gpio0_ldo: gpio0-ldo {
> + gpio0_ldo: gpio0-ldo-pin {
> pins = "GPIO0";
> function = "ldo";
> };
>
> - gpio1_ldo: gpio1-ldo {
> + gpio1_ldo: gpio1-ldo-pin {
> pins = "GPIO1";
> function = "ldo";
> };
> };
>
> - battery_power_supply: battery-power-supply {
> + battery_power_supply: battery-power {
> compatible = "x-powers,axp813-battery-power-supply";
> status = "disabled";
> };
> @@ -166,4 +171,8 @@
> status = "disabled";
> };
> };
> +
> + usb_power_supply: usb-power {
> + compatible = "x-powers,axp813-usb-power-supply";
> + };
> };
> diff --git a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> index 36ecebaff3..9c006fc188 100644
> --- a/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> +++ b/arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
> @@ -79,6 +79,14 @@
> };
> };
>
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&cpu100 {
> + cpu-supply = <®_dcdc3>;
> +};
> +
> &ehci0 {
> status = "okay";
> };
> @@ -146,6 +154,10 @@
>
> #include "axp81x.dtsi"
>
> +&ac_power_supply {
> + status = "okay";
> +};
> +
> ®_aldo1 {
> regulator-always-on;
> regulator-min-microvolt = <1800000>;
> diff --git a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
> index 2beafe3a31..b60016a442 100644
> --- a/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
> +++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts
> @@ -74,12 +74,12 @@
> leds {
> compatible = "gpio-leds";
>
> - blue {
> + led-0 {
> label = "bananapi-m3:blue:usr";
> gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
> };
>
> - green {
> + led-1 {
> label = "bananapi-m3:green:usr";
> gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
> };
> @@ -107,6 +107,14 @@
> };
> };
>
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&cpu100 {
> + cpu-supply = <®_dcdc3>;
> +};
> +
> &de {
> status = "okay";
> };
> @@ -183,6 +191,11 @@
> status = "okay";
> };
>
> +&r_cir {
> + clock-frequency = <3000000>;
> + status = "okay";
> +};
> +
> &r_rsb {
> status = "okay";
>
> @@ -224,6 +237,14 @@
>
> #include "axp81x.dtsi"
>
> +&ac_power_supply {
> + status = "okay";
> +};
> +
> +&battery_power_supply {
> + status = "okay";
> +};
> +
> ®_aldo1 {
> regulator-always-on;
> regulator-min-microvolt = <1800000>;
> @@ -301,8 +322,8 @@
>
> ®_dldo3 {
> regulator-always-on;
> - regulator-min-microvolt = <2500000>;
> - regulator-max-microvolt = <2500000>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> regulator-name = "vcc-pd";
> };
>
> @@ -350,11 +371,37 @@
> status = "okay";
> };
>
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + clocks = <&ac100_rtc 1>;
> + clock-names = "lpo";
> + vbat-supply = <®_dldo1>;
> + vddio-supply = <®_dldo1>;
> + device-wakeup-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
> + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
> + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
> + };
> +};
> +
> &usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usb_power_supply {
> status = "okay";
> };
>
> &usbphy {
> + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
> + usb0_vbus_power-supply = <&usb_power_supply>;
> + usb0_vbus-supply = <®_drivevbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> status = "okay";
> };
> diff --git a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> index ecd9ff38a8..e26af7cf10 100644
> --- a/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> +++ b/arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
> @@ -60,25 +60,36 @@
> stdout-path = "serial0:115200n8";
> };
>
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> - blue {
> + led-0 {
> label = "cubietruck-plus:blue:usr";
> gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
> };
>
> - orange {
> + led-1 {
> label = "cubietruck-plus:orange:usr";
> gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */
> };
>
> - white {
> + led-2 {
> label = "cubietruck-plus:white:usr";
> gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */
> };
>
> - green {
> + led-3 {
> label = "cubietruck-plus:green:usr";
> gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */
> };
> @@ -90,7 +101,7 @@
> initial-mode = <1>; /* initialize in HUB mode */
> disabled-ports = <1>;
> intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> - reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
> + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
> connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
> refclk-frequency = <19200000>;
> };
> @@ -145,6 +156,18 @@
> };
> };
>
> +&cpu0 {
> + cpu-supply = <®_dcdc2>;
> +};
> +
> +&cpu100 {
> + cpu-supply = <®_dcdc3>;
> +};
> +
> +&de {
> + status = "okay";
> +};
> +
> &ehci0 {
> /* GL830 USB-to-SATA bridge here */
> status = "okay";
> @@ -164,6 +187,16 @@
> status = "okay";
> };
>
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> &mdio {
> rgmii_phy: ethernet-phy@1 {
> compatible = "ethernet-phy-ieee802.3-c22";
> @@ -239,6 +272,14 @@
>
> #include "axp81x.dtsi"
>
> +&ac_power_supply {
> + status = "okay";
> +};
> +
> +&battery_power_supply {
> + status = "okay";
> +};
> +
> ®_aldo1 {
> regulator-always-on;
> regulator-min-microvolt = <1800000>;
> @@ -386,11 +427,37 @@
> status = "okay";
> };
>
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm4330-bt";
> + clocks = <&ac100_rtc 1>;
> + clock-names = "lpo";
> + vbat-supply = <®_dcdc1>;
> + vddio-supply = <®_sw>;
> + device-wakeup-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
> + host-wakeup-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
> + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
> + };
> +};
> +
> &usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usb_power_supply {
> status = "okay";
> };
>
> &usbphy {
> + usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
> + usb0_vbus_power-supply = <&usb_power_supply>;
> + usb0_vbus-supply = <®_drivevbus>;
> usb1_vbus-supply = <®_usb1_vbus>;
> usb2_vbus-supply = <®_usb2_vbus>;
> status = "okay";
> diff --git a/arch/arm/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/dts/sun8i-a83t-tbs-a711.dts
> index 1537ce148c..13ae10f60d 100644
> --- a/arch/arm/dts/sun8i-a83t-tbs-a711.dts
> +++ b/arch/arm/dts/sun8i-a83t-tbs-a711.dts
> @@ -46,6 +46,7 @@
>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/pwm/pwm.h>
> +#include <dt-bindings/input/input.h>
>
> / {
> model = "TBS A711 Tablet";
> @@ -64,7 +65,7 @@
> compatible = "pwm-backlight";
> pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
> enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;
> -
> + power-supply = <®_sw>;
> brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
> default-brightness-level = <9>;
> };
> @@ -98,6 +99,13 @@
> };
> };
>
> + reg_gps: reg-gps {
> + compatible = "regulator-fixed";
> + regulator-name = "gps";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> reg_vbat: reg-vbat {
> compatible = "regulator-fixed";
> regulator-name = "vbat";
> @@ -156,10 +164,39 @@
> status = "okay";
> };
>
> +&i2c0 {
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + touchscreen@38 {
> + compatible = "edt,edt-ft5206";
> + reg = <0x38>;
> + interrupt-parent = <&r_pio>;
> + interrupts = <0 7 IRQ_TYPE_EDGE_FALLING>; /* PL7 */
> + reset-gpios = <&pio 3 5 GPIO_ACTIVE_LOW>; /* PD5 */
> + vcc-supply = <®_ldo_io0>;
> + touchscreen-size-x = <1024>;
> + touchscreen-size-y = <600>;
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + accelerometer@18 {
> + compatible = "bosch,bma250";
> + reg = <0x18>;
> + interrupt-parent = <&pio>;
> + interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_dcdc1>;
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> + bus-width = <4>;
> cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
> status = "okay";
> };
> @@ -171,6 +208,7 @@
> vqmmc-supply = <®_dldo1>;
> non-removable;
> wakeup-source;
> + keep-power-in-suspend;
> status = "okay";
>
> brcmf: wifi@1 {
> @@ -199,6 +237,25 @@
> status = "okay";
> };
>
> +&r_lradc {
> + vref-supply = <®_aldo2>;
> + status = "okay";
> +
> + button-210 {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + channel = <0>;
> + voltage = <210000>;
> + };
> +
> + button-410 {
> + label = "Volume Down";
> + linux,code = <KEY_VOLUMEDOWN>;
> + channel = <0>;
> + voltage = <410000>;
> + };
> +};
> +
> &r_rsb {
> status = "okay";
>
> @@ -317,8 +374,8 @@
> };
>
> ®_dldo3 {
> - regulator-min-microvolt = <2800000>;
> - regulator-max-microvolt = <2800000>;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> regulator-name = "vdd-csi";
> };
>
> @@ -390,8 +447,7 @@
> };
>
> &tcon0_out {
> - tcon0_out_lcd: endpoint@0 {
> - reg = <0>;
> + tcon0_out_lcd: endpoint {
> remote-endpoint = <&panel_input>;
> };
> };
> @@ -406,18 +462,45 @@
> &uart1 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
> + uart-has-rtscts;
> status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm20702a1";
> + clocks = <&ac100_rtc 1>;
> + clock-names = "lpo";
> + vbat-supply = <®_vbat>;
> + vddio-supply = <®_dldo1>;
> + device-wakeup-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
> + host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
> + shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
> + max-speed = <1500000>;
> + };
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pb_pins>;
> + status = "okay";
> +
> + gnss {
> + compatible = "u-blox,neo-6m";
> +
> + v-bckp-supply = <®_rtc_ldo>;
> + vcc-supply = <®_gps>;
> + current-speed = <9600>;
> + };
> };
>
> &usb_otg {
> - dr_mode = "otg";
> status = "okay";
> };
>
> &usbphy {
> - usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
> + usb0_id_det-gpios = <&pio 7 11 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PH11 */
> + usb0_vbus_power-supply = <&usb_power_supply>;
> usb0_vbus-supply = <®_drivevbus>;
> - usb1_vbus_supply = <®_vmain>;
> - usb2_vbus_supply = <®_vmain>;
> + usb1_vbus-supply = <®_vmain>;
> + usb2_vbus-supply = <®_vmain>;
> status = "okay";
> };
> diff --git a/arch/arm/dts/sun8i-a83t.dtsi b/arch/arm/dts/sun8i-a83t.dtsi
> index 2be23d6009..9c07660080 100644
> --- a/arch/arm/dts/sun8i-a83t.dtsi
> +++ b/arch/arm/dts/sun8i-a83t.dtsi
> @@ -50,6 +50,7 @@
> #include <dt-bindings/reset/sun8i-a83t-ccu.h>
> #include <dt-bindings/reset/sun8i-de2.h>
> #include <dt-bindings/reset/sun8i-r-ccu.h>
> +#include <dt-bindings/thermal/thermal.h>
>
> / {
> interrupt-parent = <&gic>;
> @@ -61,79 +62,91 @@
> #size-cells = <0>;
>
> cpu0: cpu@0 {
> - clocks = <&ccu CLK_C0CPUX>;
> - clock-names = "cpu";
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C0CPUX>;
> operating-points-v2 = <&cpu0_opp_table>;
> cci-control-port = <&cci_control0>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <0>;
> + #cooling-cells = <2>;
> };
>
> - cpu@1 {
> + cpu1: cpu@1 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C0CPUX>;
> operating-points-v2 = <&cpu0_opp_table>;
> cci-control-port = <&cci_control0>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <1>;
> + #cooling-cells = <2>;
> };
>
> - cpu@2 {
> + cpu2: cpu@2 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C0CPUX>;
> operating-points-v2 = <&cpu0_opp_table>;
> cci-control-port = <&cci_control0>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <2>;
> + #cooling-cells = <2>;
> };
>
> - cpu@3 {
> + cpu3: cpu@3 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C0CPUX>;
> operating-points-v2 = <&cpu0_opp_table>;
> cci-control-port = <&cci_control0>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <3>;
> + #cooling-cells = <2>;
> };
>
> cpu100: cpu@100 {
> - clocks = <&ccu CLK_C1CPUX>;
> - clock-names = "cpu";
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C1CPUX>;
> operating-points-v2 = <&cpu1_opp_table>;
> cci-control-port = <&cci_control1>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <0x100>;
> + #cooling-cells = <2>;
> };
>
> - cpu@101 {
> + cpu101: cpu@101 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C1CPUX>;
> operating-points-v2 = <&cpu1_opp_table>;
> cci-control-port = <&cci_control1>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <0x101>;
> + #cooling-cells = <2>;
> };
>
> - cpu@102 {
> + cpu102: cpu@102 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C1CPUX>;
> operating-points-v2 = <&cpu1_opp_table>;
> cci-control-port = <&cci_control1>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <0x102>;
> + #cooling-cells = <2>;
> };
>
> - cpu@103 {
> + cpu103: cpu@103 {
> compatible = "arm,cortex-a7";
> device_type = "cpu";
> + clocks = <&ccu CLK_C1CPUX>;
> operating-points-v2 = <&cpu1_opp_table>;
> cci-control-port = <&cci_control1>;
> enable-method = "allwinner,sun8i-a83t-smp";
> reg = <0x103>;
> + #cooling-cells = <2>;
> };
> };
>
> @@ -187,12 +200,7 @@
> status = "disabled";
> };
>
> - memory {
> - reg = <0x40000000 0x80000000>;
> - device_type = "memory";
> - };
> -
> - cpu0_opp_table: opp_table0 {
> + cpu0_opp_table: opp-table-cluster0 {
> compatible = "operating-points-v2";
> opp-shared;
>
> @@ -245,7 +253,7 @@
> };
> };
>
> - cpu1_opp_table: opp_table1 {
> + cpu1_opp_table: opp-table-cluster1 {
> compatible = "operating-points-v2";
> opp-shared;
>
> @@ -306,16 +314,27 @@
>
> display_clocks: clock@1000000 {
> compatible = "allwinner,sun8i-a83t-de2-clk";
> - reg = <0x01000000 0x100000>;
> - clocks = <&ccu CLK_PLL_DE>,
> - <&ccu CLK_BUS_DE>;
> - clock-names = "mod",
> - "bus";
> + reg = <0x01000000 0x10000>;
> + clocks = <&ccu CLK_BUS_DE>,
> + <&ccu CLK_PLL_DE>;
> + clock-names = "bus",
> + "mod";
> resets = <&ccu RST_BUS_DE>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
>
> + rotate: rotate@1020000 {
> + compatible = "allwinner,sun8i-a83t-de2-rotate";
> + reg = <0x1020000 0x10000>;
> + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&display_clocks CLK_BUS_ROT>,
> + <&display_clocks CLK_ROT>;
> + clock-names = "bus",
> + "mod";
> + resets = <&display_clocks RST_ROT>;
> + };
> +
> mixer0: mixer@1100000 {
> compatible = "allwinner,sun8i-a83t-de2-mixer-0";
> reg = <0x01100000 0x100000>;
> @@ -338,6 +357,11 @@
> reg = <0>;
> remote-endpoint = <&tcon0_in_mixer0>;
> };
> +
> + mixer0_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&tcon1_in_mixer0>;
> + };
> };
> };
> };
> @@ -356,9 +380,17 @@
> #size-cells = <0>;
>
> mixer1_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> reg = <1>;
>
> - mixer1_out_tcon1: endpoint {
> + mixer1_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&tcon0_in_mixer1>;
> + };
> +
> + mixer1_out_tcon1: endpoint@1 {
> + reg = <1>;
> remote-endpoint = <&tcon1_in_mixer1>;
> };
> };
> @@ -425,6 +457,7 @@
> clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
> clock-names = "ahb", "tcon-ch0";
> clock-output-names = "tcon-pixel-clock";
> + #clock-cells = <0>;
> resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
> reset-names = "lcd", "lvds";
>
> @@ -441,11 +474,14 @@
> reg = <0>;
> remote-endpoint = <&mixer0_out_tcon0>;
> };
> +
> + tcon0_in_mixer1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&mixer1_out_tcon0>;
> + };
> };
>
> tcon0_out: port@1 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> reg = <1>;
> };
> };
> @@ -465,9 +501,17 @@
> #size-cells = <0>;
>
> tcon1_in: port@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> reg = <0>;
>
> - tcon1_in_mixer1: endpoint {
> + tcon1_in_mixer0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&mixer0_out_tcon1>;
> + };
> +
> + tcon1_in_mixer1: endpoint@1 {
> + reg = <1>;
> remote-endpoint = <&mixer1_out_tcon1>;
> };
> };
> @@ -549,6 +593,31 @@
> sid: eeprom@1c14000 {
> compatible = "allwinner,sun8i-a83t-sid";
> reg = <0x1c14000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + ths_calibration: thermal-sensor-calibration@34 {
> + reg = <0x34 8>;
> + };
> + };
> +
> + crypto: crypto@1c15000 {
> + compatible = "allwinner,sun8i-a83t-crypto";
> + reg = <0x01c15000 0x1000>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> + resets = <&ccu RST_BUS_SS>;
> + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
> + clock-names = "bus", "mod";
> + };
> +
> + msgbox: mailbox@1c17000 {
> + compatible = "allwinner,sun8i-a83t-msgbox",
> + "allwinner,sun6i-a31-msgbox";
> + reg = <0x01c17000 0x1000>;
> + clocks = <&ccu CLK_BUS_MSGBOX>;
> + resets = <&ccu RST_BUS_MSGBOX>;
> + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + #mbox-cells = <1>;
> };
>
> usb_otg: usb@1c19000 {
> @@ -562,6 +631,7 @@
> phys = <&usbphy 0>;
> phy-names = "usb";
> extcon = <&usbphy 0>;
> + dr_mode = "otg";
> status = "disabled";
> };
>
> @@ -649,6 +719,20 @@
> #interrupt-cells = <3>;
> #gpio-cells = <3>;
>
> + /omit-if-no-ref/
> + csi_8bit_parallel_pins: csi-8bit-parallel-pins {
> + pins = "PE0", "PE2", "PE3", "PE6", "PE7",
> + "PE8", "PE9", "PE10", "PE11",
> + "PE12", "PE13";
> + function = "csi";
> + };
> +
> + /omit-if-no-ref/
> + csi_mclk_pin: csi-mclk-pin {
> + pins = "PE1";
> + function = "csi";
> + };
> +
> emac_rgmii_pins: emac-rgmii-pins {
> pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
> "PD11", "PD12", "PD13", "PD14", "PD18",
> @@ -676,6 +760,12 @@
> function = "i2c1";
> };
>
> + /omit-if-no-ref/
> + i2c2_pe_pins: i2c2-pe-pins {
> + pins = "PE14", "PE15";
> + function = "i2c2";
> + };
> +
> i2c2_ph_pins: i2c2-ph-pins {
> pins = "PH4", "PH5";
> function = "i2c2";
> @@ -747,10 +837,16 @@
> pins = "PG8", "PG9";
> function = "uart1";
> };
> +
> + /omit-if-no-ref/
> + uart2_pb_pins: uart2-pb-pins {
> + pins = "PB0", "PB1";
> + function = "uart2";
> + };
> };
>
> timer@1c20c00 {
> - compatible = "allwinner,sun4i-a10-timer";
> + compatible = "allwinner,sun8i-a23-timer";
> reg = <0x01c20c00 0xa0>;
> interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> @@ -852,6 +948,39 @@
> status = "disabled";
> };
>
> + uart2: serial@1c28800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + status = "disabled";
> + };
> +
> + uart3: serial@1c28c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c28c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + status = "disabled";
> + };
> +
> + uart4: serial@1c29000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01c29000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + status = "disabled";
> + };
> +
> i2c0: i2c@1c2ac00 {
> compatible = "allwinner,sun8i-a83t-i2c",
> "allwinner,sun6i-a31-i2c";
> @@ -898,12 +1027,10 @@
> reg = <0x01c30000 0x104>;
> interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "macirq";
> - resets = <&ccu 13>;
> - reset-names = "stmmaceth";
> - clocks = <&ccu 27>;
> + clocks = <&ccu CLK_BUS_EMAC>;
> clock-names = "stmmaceth";
> - #address-cells = <1>;
> - #size-cells = <0>;
> + resets = <&ccu RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> status = "disabled";
>
> mdio: mdio {
> @@ -914,7 +1041,7 @@
> };
>
> gic: interrupt-controller@1c81000 {
> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + compatible = "arm,gic-400";
> reg = <0x01c81000 0x1000>,
> <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
> @@ -924,6 +1051,18 @@
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + csi: camera@1cb0000 {
> + compatible = "allwinner,sun8i-a83t-csi";
> + reg = <0x01cb0000 0x1000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> + status = "disabled";
> + };
> +
> hdmi: hdmi@1ee0000 {
> compatible = "allwinner,sun8i-a83t-dw-hdmi";
> reg = <0x01ee0000 0x10000>;
> @@ -935,7 +1074,7 @@
> resets = <&ccu RST_BUS_HDMI1>;
> reset-names = "ctrl";
> phys = <&hdmi_phy>;
> - phy-names = "hdmi-phy";
> + phy-names = "phy";
> pinctrl-names = "default";
> pinctrl-0 = <&hdmi_pins>;
> status = "disabled";
> @@ -981,7 +1120,7 @@
> compatible = "allwinner,sun8i-a83t-r-ccu";
> reg = <0x01f01400 0x400>;
> clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
> - <&ccu 6>;
> + <&ccu CLK_PLL_PERIPH>;
> clock-names = "hosc", "losc", "iosc", "pll-periph";
> #clock-cells = <1>;
> #reset-cells = <1>;
> @@ -992,6 +1131,26 @@
> reg = <0x1f01c00 0x400>;
> };
>
> + r_cir: ir@1f02000 {
> + compatible = "allwinner,sun8i-a83t-ir",
> + "allwinner,sun6i-a31-ir";
> + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_APB0_IR>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x01f02000 0x400>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_cir_pin>;
> + status = "disabled";
> + };
> +
> + r_lradc: lradc@1f03c00 {
> + compatible = "allwinner,sun8i-a83t-r-lradc";
> + reg = <0x01f03c00 0x100>;
> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> r_pio: pinctrl@1f02c00 {
> compatible = "allwinner,sun8i-a83t-r-pinctrl";
> reg = <0x01f02c00 0x400>;
> @@ -1004,6 +1163,11 @@
> interrupt-controller;
> #interrupt-cells = <3>;
>
> + r_cir_pin: r-cir-pin {
> + pins = "PL12";
> + function = "s_cir_rx";
> + };
> +
> r_rsb_pins: r-rsb-pins {
> pins = "PL0", "PL1";
> function = "s_rsb";
> @@ -1026,5 +1190,82 @@
> #address-cells = <1>;
> #size-cells = <0>;
> };
> +
> + ths: thermal-sensor@1f04000 {
> + compatible = "allwinner,sun8i-a83t-ths";
> + reg = <0x01f04000 0x100>;
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> + nvmem-cells = <&ths_calibration>;
> + nvmem-cell-names = "calibration";
> + #thermal-sensor-cells = <1>;
> + };
> + };
> +
> + thermal-zones {
> + cpu0_thermal: cpu0-thermal {
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 0>;
> +
> + trips {
> + cpu0_hot: cpu-hot {
> + temperature = <80000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu0_very_hot: cpu-very-hot {
> + temperature = <100000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + cpu-hot-limit {
> + trip = <&cpu0_hot>;
> + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + cpu1_thermal: cpu1-thermal {
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 1>;
> +
> + trips {
> + cpu1_hot: cpu-hot {
> + temperature = <80000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu1_very_hot: cpu-very-hot {
> + temperature = <100000>;
> + hysteresis = <0>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + cpu-hot-limit {
> + trip = <&cpu1_hot>;
> + cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + gpu_thermal: gpu-thermal {
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + thermal-sensors = <&ths 2>;
> + };
> };
> };
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 11/12] ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 11/12] ARM: dts: sun50i: A64: " Samuel Holland
@ 2022-05-20 14:01 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-20 14:01 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:30 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Copy the devicetree source for the A64 SoC and all existing boards
> from the Linux v5.18-rc1 tag.
>
> To maintain ABI compatibility with existing LTS kernels, one change
> moving some IP blocks to the r_intc interrupt controller is excluded.
> This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.
>
> This update should not impact any existing U-Boot functionality.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Compared against the files in the kernel tree, apart from the r_intc
change they are identical.
Change-wise I cannot find any compatibility breaking change.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/axp803.dtsi | 10 +--
> arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-a64-orangepi-win.dts | 2 +-
> arch/arm/dts/sun50i-a64-pinebook.dts | 1 +
> arch/arm/dts/sun50i-a64-pinephone.dtsi | 27 +++++++
> arch/arm/dts/sun50i-a64-pinetab.dts | 29 +++++++-
> arch/arm/dts/sun50i-a64-teres-i.dts | 4 +-
> arch/arm/dts/sun50i-a64.dtsi | 93 ++++++++++++++++++------
> 8 files changed, 137 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/dts/axp803.dtsi b/arch/arm/dts/axp803.dtsi
> index 10e9186a76..578ef368e2 100644
> --- a/arch/arm/dts/axp803.dtsi
> +++ b/arch/arm/dts/axp803.dtsi
> @@ -10,7 +10,7 @@
> interrupt-controller;
> #interrupt-cells = <1>;
>
> - ac_power_supply: ac-power-supply {
> + ac_power_supply: ac-power {
> compatible = "x-powers,axp803-ac-power-supply",
> "x-powers,axp813-ac-power-supply";
> status = "disabled";
> @@ -26,18 +26,18 @@
> gpio-controller;
> #gpio-cells = <2>;
>
> - gpio0_ldo: gpio0-ldo {
> + gpio0_ldo: gpio0-ldo-pin {
> pins = "GPIO0";
> function = "ldo";
> };
>
> - gpio1_ldo: gpio1-ldo {
> + gpio1_ldo: gpio1-ldo-pin {
> pins = "GPIO1";
> function = "ldo";
> };
> };
>
> - battery_power_supply: battery-power-supply {
> + battery_power_supply: battery-power {
> compatible = "x-powers,axp803-battery-power-supply",
> "x-powers,axp813-battery-power-supply";
> status = "disabled";
> @@ -147,7 +147,7 @@
> };
> };
>
> - usb_power_supply: usb-power-supply {
> + usb_power_supply: usb-power {
> compatible = "x-powers,axp803-usb-power-supply",
> "x-powers,axp813-usb-power-supply";
> status = "disabled";
> diff --git a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
> index 578c37490d..e39db51eb4 100644
> --- a/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
> +++ b/arch/arm/dts/sun50i-a64-cpu-opp.dtsi
> @@ -4,7 +4,7 @@
> */
>
> / {
> - cpu0_opp_table: opp_table0 {
> + cpu0_opp_table: opp-table-cpu {
> compatible = "operating-points-v2";
> opp-shared;
>
> diff --git a/arch/arm/dts/sun50i-a64-orangepi-win.dts b/arch/arm/dts/sun50i-a64-orangepi-win.dts
> index 70e31743f0..8eee8051ac 100644
> --- a/arch/arm/dts/sun50i-a64-orangepi-win.dts
> +++ b/arch/arm/dts/sun50i-a64-orangepi-win.dts
> @@ -343,7 +343,7 @@
> &spi0 {
> status = "okay";
>
> - spi-flash@0 {
> + flash@0 {
> compatible = "mxicy,mx25l1606e", "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <80000000>;
> diff --git a/arch/arm/dts/sun50i-a64-pinebook.dts b/arch/arm/dts/sun50i-a64-pinebook.dts
> index 7ae16541d1..68b6ab4707 100644
> --- a/arch/arm/dts/sun50i-a64-pinebook.dts
> +++ b/arch/arm/dts/sun50i-a64-pinebook.dts
> @@ -15,6 +15,7 @@
> / {
> model = "Pinebook";
> compatible = "pine64,pinebook", "allwinner,sun50i-a64";
> + chassis-type = "laptop";
>
> aliases {
> serial0 = &uart0;
> diff --git a/arch/arm/dts/sun50i-a64-pinephone.dtsi b/arch/arm/dts/sun50i-a64-pinephone.dtsi
> index 9f69d489a8..b25e7913f5 100644
> --- a/arch/arm/dts/sun50i-a64-pinephone.dtsi
> +++ b/arch/arm/dts/sun50i-a64-pinephone.dtsi
> @@ -12,6 +12,8 @@
> #include <dt-bindings/pwm/pwm.h>
>
> / {
> + chassis-type = "handset";
> +
> aliases {
> ethernet0 = &rtl8723cs;
> serial0 = &uart0;
> @@ -25,6 +27,11 @@
> /* Backlight configuration differs per PinePhone revision. */
> };
>
> + bt_sco_codec: bt-sco-codec {
> + #sound-dai-cells = <1>;
> + compatible = "linux,bt-sco";
> + };
> +
> chosen {
> stdout-path = "serial0:115200n8";
> };
> @@ -91,6 +98,8 @@
> };
>
> &codec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&aif3_pins>;
> status = "okay";
> };
>
> @@ -426,6 +435,7 @@
>
> &sound {
> status = "okay";
> + simple-audio-card,name = "PinePhone";
> simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
> simple-audio-card,widgets = "Microphone", "Headset Microphone",
> "Microphone", "Internal Microphone",
> @@ -447,6 +457,23 @@
> "MIC1", "Internal Microphone",
> "Headset Microphone", "HBIAS",
> "MIC2", "Headset Microphone";
> +
> + simple-audio-card,dai-link@2 {
> + format = "dsp_a";
> + frame-master = <&link2_codec>;
> + bitclock-master = <&link2_codec>;
> + bitclock-inversion;
> +
> + link2_cpu: cpu {
> + sound-dai = <&bt_sco_codec 0>;
> + };
> +
> + link2_codec: codec {
> + sound-dai = <&codec 2>;
> + dai-tdm-slot-num = <1>;
> + dai-tdm-slot-width = <32>;
> + };
> + };
> };
>
> &uart0 {
> diff --git a/arch/arm/dts/sun50i-a64-pinetab.dts b/arch/arm/dts/sun50i-a64-pinetab.dts
> index 422a8507f6..0b2258ef88 100644
> --- a/arch/arm/dts/sun50i-a64-pinetab.dts
> +++ b/arch/arm/dts/sun50i-a64-pinetab.dts
> @@ -16,6 +16,7 @@
> / {
> model = "PineTab, Development Sample";
> compatible = "pine64,pinetab", "allwinner,sun50i-a64";
> + chassis-type = "tablet";
>
> aliases {
> serial0 = &uart0;
> @@ -35,6 +36,17 @@
> stdout-path = "serial0:115200n8";
> };
>
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + type = "c";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> i2c-csi {
> compatible = "i2c-gpio";
> sda-gpios = <&pio 4 13 GPIO_ACTIVE_HIGH>; /* PE13 */
> @@ -77,7 +89,7 @@
> sound-name-prefix = "Speaker Amp";
> };
>
> - vdd_bl: regulator@0 {
> + vdd_bl: regulator {
> compatible = "regulator-fixed";
> regulator-name = "bl-3v3";
> regulator-min-microvolt = <3300000>;
> @@ -410,6 +422,21 @@
> regulator-name = "vcc-rtc";
> };
>
> +&simplefb_hdmi {
> + vcc-hdmi-supply = <®_dldo1>;
> +};
> +
> +&hdmi {
> + hvcc-supply = <®_dldo1>;
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> &sound {
> status = "okay";
> simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
> diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts b/arch/arm/dts/sun50i-a64-teres-i.dts
> index f0a16f355e..6668431dcb 100644
> --- a/arch/arm/dts/sun50i-a64-teres-i.dts
> +++ b/arch/arm/dts/sun50i-a64-teres-i.dts
> @@ -14,6 +14,7 @@
> / {
> model = "Olimex A64 Teres-I";
> compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
> + chassis-type = "laptop";
>
> aliases {
> serial0 = &uart0;
> @@ -139,6 +140,8 @@
> #size-cells = <0>;
>
> port@0 {
> + reg = <0>;
> +
> anx6345_in: endpoint {
> remote-endpoint = <&tcon0_out_anx6345>;
> };
> @@ -206,7 +209,6 @@
> reg = <0x3a3>;
> interrupt-parent = <&r_intc>;
> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> - wakeup-source;
> };
> };
>
> diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
> index 57786fc120..555bc92a6f 100644
> --- a/arch/arm/dts/sun50i-a64.dtsi
> +++ b/arch/arm/dts/sun50i-a64.dtsi
> @@ -102,6 +102,22 @@
> status = "disabled";
> };
>
> + gpu_opp_table: opp-table-gpu {
> + compatible = "operating-points-v2";
> +
> + opp-120000000 {
> + opp-hz = /bits/ 64 <120000000>;
> + };
> +
> + opp-312000000 {
> + opp-hz = /bits/ 64 <312000000>;
> + };
> +
> + opp-432000000 {
> + opp-hz = /bits/ 64 <432000000>;
> + };
> + };
> +
> osc24M: osc24M_clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> @@ -131,12 +147,10 @@
> };
>
> sound: sound {
> + #address-cells = <1>;
> + #size-cells = <0>;
> compatible = "simple-audio-card";
> simple-audio-card,name = "sun50i-a64-audio";
> - simple-audio-card,format = "i2s";
> - simple-audio-card,frame-master = <&cpudai>;
> - simple-audio-card,bitclock-master = <&cpudai>;
> - simple-audio-card,mclk-fs = <128>;
> simple-audio-card,aux-devs = <&codec_analog>;
> simple-audio-card,routing =
> "Left DAC", "DACL",
> @@ -145,12 +159,19 @@
> "ADCR", "Right ADC";
> status = "disabled";
>
> - cpudai: simple-audio-card,cpu {
> - sound-dai = <&dai>;
> - };
> + simple-audio-card,dai-link@0 {
> + format = "i2s";
> + frame-master = <&link0_cpu>;
> + bitclock-master = <&link0_cpu>;
> + mclk-fs = <128>;
> +
> + link0_cpu: cpu {
> + sound-dai = <&dai>;
> + };
>
> - link_codec: simple-audio-card,codec {
> - sound-dai = <&codec>;
> + link0_codec: codec {
> + sound-dai = <&codec 0>;
> + };
> };
> };
>
> @@ -658,6 +679,18 @@
> interrupt-controller;
> #interrupt-cells = <3>;
>
> + /omit-if-no-ref/
> + aif2_pins: aif2-pins {
> + pins = "PB4", "PB5", "PB6", "PB7";
> + function = "aif2";
> + };
> +
> + /omit-if-no-ref/
> + aif3_pins: aif3-pins {
> + pins = "PG10", "PG11", "PG12", "PG13";
> + function = "aif3";
> + };
> +
> csi_pins: csi-pins {
> pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
> "PE7", "PE8", "PE9", "PE10", "PE11";
> @@ -798,6 +831,23 @@
> };
> };
>
> + timer@1c20c00 {
> + compatible = "allwinner,sun50i-a64-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x01c20c00 0xa0>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> + wdt0: watchdog@1c20ca0 {
> + compatible = "allwinner,sun50i-a64-wdt",
> + "allwinner,sun6i-a31-wdt";
> + reg = <0x01c20ca0 0x20>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> spdif: spdif@1c21000 {
> #sound-dai-cells = <0>;
> compatible = "allwinner,sun50i-a64-spdif",
> @@ -878,7 +928,7 @@
> };
>
> codec: codec@1c22e00 {
> - #sound-dai-cells = <0>;
> + #sound-dai-cells = <1>;
> compatible = "allwinner,sun50i-a64-codec",
> "allwinner,sun8i-a33-codec";
> reg = <0x01c22e00 0x600>;
> @@ -1067,6 +1117,7 @@
> clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
> clock-names = "bus", "core";
> resets = <&ccu RST_BUS_GPU>;
> + operating-points-v2 = <&gpu_opp_table>;
> };
>
> gic: interrupt-controller@1c81000 {
> @@ -1093,8 +1144,14 @@
>
> mbus: dram-controller@1c62000 {
> compatible = "allwinner,sun50i-a64-mbus";
> - reg = <0x01c62000 0x1000>;
> - clocks = <&ccu 112>;
> + reg = <0x01c62000 0x1000>,
> + <0x01c63000 0x1000>;
> + reg-names = "mbus", "dram";
> + clocks = <&ccu CLK_MBUS>,
> + <&ccu CLK_DRAM>,
> + <&ccu CLK_BUS_DRAM>;
> + clock-names = "mbus", "dram", "bus";
> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x00000000 0x40000000 0xc0000000>;
> @@ -1167,8 +1224,8 @@
> reg-io-width = <1>;
> interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> - <&ccu CLK_HDMI>;
> - clock-names = "iahb", "isfr", "tmds";
> + <&ccu CLK_HDMI>, <&rtc 0>;
> + clock-names = "iahb", "isfr", "tmds", "cec";
> resets = <&ccu RST_BUS_HDMI1>;
> reset-names = "ctrl";
> phys = <&hdmi_phy>;
> @@ -1321,13 +1378,5 @@
> #address-cells = <1>;
> #size-cells = <0>;
> };
> -
> - wdt0: watchdog@1c20ca0 {
> - compatible = "allwinner,sun50i-a64-wdt",
> - "allwinner,sun6i-a31-wdt";
> - reg = <0x01c20ca0 0x20>;
> - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&osc24M>;
> - };
> };
> };
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 12/12] ARM: dts: sun50i: H6: " Samuel Holland
@ 2022-05-20 14:14 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-20 14:14 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:31 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Copy the devicetree source for the H6 SoC and all existing boards
> from the Linux v5.18-rc1 tag.
>
> To maintain ABI compatibility with existing LTS kernels, one change
> moving some IP blocks to the r_intc interrupt controller is excluded.
> This effectively reverts Linux commits 189bef235dd3 and 73088dfee635.
>
> This commit also adds the following new board devicetrees:
> - sun50i-h6-pine-h64-model-b.dts
> - sun50i-h6-tanix-tx6-mini.dts
>
> This update should not impact any existing U-Boot functionality.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Compared against the Linux kernel, apart from the r_intc changes they are
the same.
The changes look innocent, and shouldn't affect U-Boot or Linux kernel
compatibility.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/Makefile | 4 +-
> arch/arm/dts/sun50i-h6-beelink-gs1.dts | 38 ++--
> arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-h6-orangepi-3.dts | 14 +-
> arch/arm/dts/sun50i-h6-orangepi.dtsi | 22 +--
> arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 51 ++++++
> arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts | 15 ++
> arch/arm/dts/sun50i-h6-tanix-tx6.dts | 115 ++----------
> arch/arm/dts/sun50i-h6-tanix.dtsi | 189 ++++++++++++++++++++
> arch/arm/dts/sun50i-h6.dtsi | 26 ++-
> 10 files changed, 328 insertions(+), 148 deletions(-)
> create mode 100644 arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
> create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
> create mode 100644 arch/arm/dts/sun50i-h6-tanix.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 95909ef037..85e731aec9 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -695,7 +695,9 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
> sun50i-h6-orangepi-lite2.dtb \
> sun50i-h6-orangepi-one-plus.dtb \
> sun50i-h6-pine-h64.dtb \
> - sun50i-h6-tanix-tx6.dtb
> + sun50i-h6-pine-h64-model-b.dtb \
> + sun50i-h6-tanix-tx6.dtb \
> + sun50i-h6-tanix-tx6-mini.dtb
> dtb-$(CONFIG_MACH_SUN50I_H616) += \
> sun50i-h616-orangepi-zero2.dtb
> dtb-$(CONFIG_MACH_SUN50I) += \
> diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
> index b5808047d6..649b146dff 100644
> --- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
> +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
> @@ -150,12 +150,28 @@
> vcc-pg-supply = <®_aldo1>;
> };
>
> -&r_i2c {
> +&r_ir {
> + linux,rc-map-name = "rc-beelink-gs1";
> + status = "okay";
> +};
> +
> +&r_pio {
> + /*
> + * FIXME: We can't add that supply for now since it would
> + * create a circular dependency between pinctrl, the regulator
> + * and the RSB Bus.
> + *
> + * vcc-pl-supply = <®_aldo1>;
> + */
> + vcc-pm-supply = <®_aldo1>;
> +};
> +
> +&r_rsb {
> status = "okay";
>
> - axp805: pmic@36 {
> + axp805: pmic@745 {
> compatible = "x-powers,axp805", "x-powers,axp806";
> - reg = <0x36>;
> + reg = <0x745>;
> interrupt-parent = <&r_intc>;
> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> interrupt-controller;
> @@ -273,22 +289,6 @@
> };
> };
>
> -&r_ir {
> - linux,rc-map-name = "rc-beelink-gs1";
> - status = "okay";
> -};
> -
> -&r_pio {
> - /*
> - * PL0 and PL1 are used for PMIC I2C
> - * don't enable the pl-supply else
> - * it will fail at boot
> - *
> - * vcc-pl-supply = <®_aldo1>;
> - */
> - vcc-pm-supply = <®_aldo1>;
> -};
> -
> &spdif {
> status = "okay";
> };
> diff --git a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
> index 8c6e8536b6..0baf0f8e4d 100644
> --- a/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
> +++ b/arch/arm/dts/sun50i-h6-cpu-opp.dtsi
> @@ -3,7 +3,7 @@
> // Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
>
> / {
> - cpu_opp_table: cpu-opp-table {
> + cpu_opp_table: opp-table-cpu {
> compatible = "allwinner,sun50i-h6-operating-points";
> nvmem-cells = <&cpu_speed_grade>;
> opp-shared;
> diff --git a/arch/arm/dts/sun50i-h6-orangepi-3.dts b/arch/arm/dts/sun50i-h6-orangepi-3.dts
> index 7e83f6146f..9f12c05e21 100644
> --- a/arch/arm/dts/sun50i-h6-orangepi-3.dts
> +++ b/arch/arm/dts/sun50i-h6-orangepi-3.dts
> @@ -175,12 +175,16 @@
> vcc-pg-supply = <®_vcc_wifi_io>;
> };
>
> -&r_i2c {
> +&r_ir {
> + status = "okay";
> +};
> +
> +&r_rsb {
> status = "okay";
>
> - axp805: pmic@36 {
> + axp805: pmic@745 {
> compatible = "x-powers,axp805", "x-powers,axp806";
> - reg = <0x36>;
> + reg = <0x745>;
> interrupt-parent = <&r_intc>;
> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> interrupt-controller;
> @@ -291,10 +295,6 @@
> };
> };
>
> -&r_ir {
> - status = "okay";
> -};
> -
> &rtc {
> clocks = <&ext_osc32k>;
> };
> diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi
> index da0875bd38..a5811d55bb 100644
> --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi
> +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi
> @@ -112,12 +112,20 @@
> vcc-pg-supply = <®_aldo1>;
> };
>
> -&r_i2c {
> +&r_ir {
> + status = "okay";
> +};
> +
> +&r_pio {
> + vcc-pm-supply = <®_bldo3>;
> +};
> +
> +&r_rsb {
> status = "okay";
>
> - axp805: pmic@36 {
> + axp805: pmic@745 {
> compatible = "x-powers,axp805", "x-powers,axp806";
> - reg = <0x36>;
> + reg = <0x745>;
> interrupt-parent = <&r_intc>;
> interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> interrupt-controller;
> @@ -232,14 +240,6 @@
> };
> };
>
> -&r_ir {
> - status = "okay";
> -};
> -
> -&r_pio {
> - vcc-pm-supply = <®_bldo3>;
> -};
> -
> &rtc {
> clocks = <&ext_osc32k>;
> };
> diff --git a/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
> new file mode 100644
> index 0000000000..686f58e770
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
> @@ -0,0 +1,51 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2019 Corentin LABBE <clabbe@baylibre.com>
> + */
> +
> +#include "sun50i-h6-pine-h64.dts"
> +
> +/ {
> + model = "Pine H64 model B";
> + compatible = "pine64,pine-h64-model-b", "allwinner,sun50i-h6";
> +
> + /delete-node/ reg_gmac_3v3;
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
> + post-power-on-delay-ms = <200>;
> + };
> +};
> +
> +&hdmi_connector {
> + /delete-property/ ddc-en-gpios;
> +};
> +
> +&emac {
> + phy-supply = <®_aldo2>;
> +};
> +
> +&mmc1 {
> + vmmc-supply = <®_cldo3>;
> + vqmmc-supply = <®_aldo1>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "realtek,rtl8723bs-bt";
> + device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
> + host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
> + enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
> + max-speed = <1500000>;
> + };
> +};
> diff --git a/arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts b/arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
> new file mode 100644
> index 0000000000..08d84160d8
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
> @@ -0,0 +1,15 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
> +
> +/dts-v1/;
> +
> +#include "sun50i-h6-tanix.dtsi"
> +
> +/ {
> + model = "Tanix TX6 mini";
> + compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6";
> +};
> +
> +&r_ir {
> + linux,rc-map-name = "rc-tanix-tx3mini";
> +};
> diff --git a/arch/arm/dts/sun50i-h6-tanix-tx6.dts b/arch/arm/dts/sun50i-h6-tanix-tx6.dts
> index be81330db1..9a38ff9b3f 100644
> --- a/arch/arm/dts/sun50i-h6-tanix-tx6.dts
> +++ b/arch/arm/dts/sun50i-h6-tanix-tx6.dts
> @@ -3,122 +3,27 @@
>
> /dts-v1/;
>
> -#include "sun50i-h6.dtsi"
> -#include "sun50i-h6-cpu-opp.dtsi"
> -
> -#include <dt-bindings/gpio/gpio.h>
> +#include "sun50i-h6-tanix.dtsi"
>
> / {
> model = "Tanix TX6";
> compatible = "oranth,tanix-tx6", "allwinner,sun50i-h6";
> -
> - aliases {
> - serial0 = &uart0;
> - };
> -
> - chosen {
> - stdout-path = "serial0:115200n8";
> - };
> -
> - connector {
> - compatible = "hdmi-connector";
> - ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
> - type = "a";
> -
> - port {
> - hdmi_con_in: endpoint {
> - remote-endpoint = <&hdmi_out_con>;
> - };
> - };
> - };
> -
> - reg_vcc3v3: vcc3v3 {
> - compatible = "regulator-fixed";
> - regulator-name = "vcc3v3";
> - regulator-min-microvolt = <3300000>;
> - regulator-max-microvolt = <3300000>;
> - };
> -
> - reg_vdd_cpu_gpu: vdd-cpu-gpu {
> - compatible = "regulator-fixed";
> - regulator-name = "vdd-cpu-gpu";
> - regulator-min-microvolt = <1135000>;
> - regulator-max-microvolt = <1135000>;
> - };
> -};
> -
> -&cpu0 {
> - cpu-supply = <®_vdd_cpu_gpu>;
> -};
> -
> -&de {
> - status = "okay";
> -};
> -
> -&dwc3 {
> - status = "okay";
> -};
> -
> -&ehci0 {
> - status = "okay";
> -};
> -
> -&ehci3 {
> - status = "okay";
> -};
> -
> -&gpu {
> - mali-supply = <®_vdd_cpu_gpu>;
> - status = "okay";
> -};
> -
> -&hdmi {
> - status = "okay";
> -};
> -
> -&hdmi_out {
> - hdmi_out_con: endpoint {
> - remote-endpoint = <&hdmi_con_in>;
> - };
> -};
> -
> -&mmc0 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins>;
> - vmmc-supply = <®_vcc3v3>;
> - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
> - bus-width = <4>;
> - status = "okay";
> -};
> -
> -&ohci0 {
> - status = "okay";
> -};
> -
> -&ohci3 {
> - status = "okay";
> };
>
> &r_ir {
> linux,rc-map-name = "rc-tanix-tx5max";
> - status = "okay";
> };
>
> -&uart0 {
> +&uart1 {
> pinctrl-names = "default";
> - pinctrl-0 = <&uart0_ph_pins>;
> + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
> + uart-has-rtscts;
> status = "okay";
> -};
>
> -&usb2otg {
> - dr_mode = "host";
> - status = "okay";
> -};
> -
> -&usb2phy {
> - status = "okay";
> -};
> -
> -&usb3phy {
> - status = "okay";
> + bluetooth {
> + compatible = "realtek,rtl8822cs-bt";
> + device-wake-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */
> + host-wake-gpios = <&r_pio 1 1 GPIO_ACTIVE_HIGH>; /* PM1 */
> + enable-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */
> + };
> };
> diff --git a/arch/arm/dts/sun50i-h6-tanix.dtsi b/arch/arm/dts/sun50i-h6-tanix.dtsi
> new file mode 100644
> index 0000000000..edb71e4a03
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-h6-tanix.dtsi
> @@ -0,0 +1,189 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
> +
> +/dts-v1/;
> +
> +#include "sun50i-h6.dtsi"
> +#include "sun50i-h6-cpu-opp.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + connector {
> + compatible = "hdmi-connector";
> + ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> + /* used for FD650 LED display driver */
> + i2c {
> + compatible = "i2c-gpio";
> + sda-gpios = <&pio 7 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH6 */
> + scl-gpios = <&pio 7 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PH5 */
> + i2c-gpio,delay-us = <5>;
> + };
> +
> + reg_vcc1v8: regulator-vcc1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + reg_vcc3v3: regulator-vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd-cpu-gpu";
> + regulator-min-microvolt = <1135000>;
> + regulator-max-microvolt = <1135000>;
> + };
> +
> + sound-spdif {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "sun50i-h6-spdif";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&spdif>;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&spdif_out>;
> + };
> + };
> +
> + spdif_out: spdif-out {
> + #sound-dai-cells = <0>;
> + compatible = "linux,spdif-dit";
> + };
> +
> + wifi_pwrseq: wifi-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = <&rtc 1>;
> + clock-names = "ext_clock";
> + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <®_vdd_cpu_gpu>;
> +};
> +
> +&de {
> + status = "okay";
> +};
> +
> +&dwc3 {
> + status = "okay";
> +};
> +
> +&ehci0 {
> + status = "okay";
> +};
> +
> +&ehci3 {
> + status = "okay";
> +};
> +
> +&gpu {
> + mali-supply = <®_vdd_cpu_gpu>;
> + status = "okay";
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + vmmc-supply = <®_vcc3v3>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
> + bus-width = <4>;
> + status = "okay";
> +};
> +
> +&mmc1 {
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc1v8>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&mmc2 {
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc1v8>;
> + bus-width = <8>;
> + non-removable;
> + cap-mmc-hw-reset;
> + mmc-hs200-1_8v;
> + status = "okay";
> +};
> +
> +&ohci0 {
> + status = "okay";
> +};
> +
> +&ohci3 {
> + status = "okay";
> +};
> +
> +&pio {
> + vcc-pc-supply = <®_vcc1v8>;
> + vcc-pd-supply = <®_vcc3v3>;
> + vcc-pg-supply = <®_vcc1v8>;
> +};
> +
> +&r_ir {
> + status = "okay";
> +};
> +
> +&spdif {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_ph_pins>;
> + status = "okay";
> +};
> +
> +&usb2otg {
> + dr_mode = "host";
> + status = "okay";
> +};
> +
> +&usb2phy {
> + status = "okay";
> +};
> +
> +&usb3phy {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
> index af8b7d0ef7..71a45a624d 100644
> --- a/arch/arm/dts/sun50i-h6.dtsi
> +++ b/arch/arm/dts/sun50i-h6.dtsi
> @@ -119,10 +119,10 @@
> display_clocks: clock@0 {
> compatible = "allwinner,sun50i-h6-de3-clk";
> reg = <0x0 0x10000>;
> - clocks = <&ccu CLK_DE>,
> - <&ccu CLK_BUS_DE>;
> - clock-names = "mod",
> - "bus";
> + clocks = <&ccu CLK_BUS_DE>,
> + <&ccu CLK_DE>;
> + clock-names = "bus",
> + "mod";
> resets = <&ccu RST_BUS_DE>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> @@ -153,6 +153,15 @@
> };
> };
>
> + video-codec-g2@1c00000 {
> + compatible = "allwinner,sun50i-h6-vpu-g2";
> + reg = <0x01c00000 0x1000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_VP9>;
> + };
> +
> video-codec@1c0e000 {
> compatible = "allwinner,sun50i-h6-video-engine";
> reg = <0x01c0e000 0x2000>;
> @@ -271,6 +280,15 @@
> };
> };
>
> + timer@3009000 {
> + compatible = "allwinner,sun50i-h6-timer",
> + "allwinner,sun8i-a23-timer";
> + reg = <0x03009000 0xa0>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + };
> +
> watchdog: watchdog@30090a0 {
> compatible = "allwinner,sun50i-h6-wdt",
> "allwinner,sun6i-a31-wdt";
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 05/12] ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 05/12] ARM: dts: sunxi: A13/A31/A23/A33: " Samuel Holland
@ 2022-05-20 15:34 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-20 15:34 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:24 -0500
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> Copy the devicetree source for the A10s/A13/GR8, A31(s), and A23/A33/R16
> SoCs and all existing boards from the Linux v5.18-rc1 tag.
>
> These changes are combined into one commit due to interdependencies:
> - The unit addresses were removed from bitbanged I2C buses, which
> drives a Kconfig default change. This affects sun5i-a13-utoo-p66.dts
> and sun6i-a31-colombus.dts.
> - The pinctrl nodes were renamed, including some used by the shared
> header sunxi-reference-design-tablet.dtsi.
>
> To maintain ABI compatibility with existing LTS kernels, one change
> moving some IP blocks to the r_intc interrupt controller is excluded.
> This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
>
> This commit renames the file sun8i-r16-nintendo-nes-classic-edition.dts
> to sun8i-r16-nintendo-nes-classic.dts to match the Linux tree.
>
> This commit also adds the following new board devicetrees:
> - sun5i-a13-licheepi-one.dts
> - sun5i-a13-pocketbook-touch-lux-3.dts
> - sun5i-gr8-evb.dts
> - sun8i-a23-ippo-q8h-v1.2.dts
> - sun8i-a23-ippo-q8h-v5.dts
> - sun8i-a33-et-q8-v1.6.dts
> - sun8i-a33-ippo-q8h-v1.2.dts
> - sun8i-r16-nintendo-super-nes-classic.dts
>
> As with the other SoCs, updates of note are conversion of GPIO pull-up
> from pinconf to GPIO flags and renaming the detection GPIO properties in
> the USB PHY nodes.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
So that's a big one. The sync part looks good, I compared the files
against the kernel, and the r_intc change is the only difference.
Most of the changes are about node names and GPIO / pinctrl usage, which
*should* be fine, especially for U-Boot.
However there are a number of incompatible changes, I marked them below in
the patch, for reference, but enumerate them here for easier discussion:
- "allwinner,sun4i-a10-sram-controller" got replaced with
"allwinner,sun5i-a13-system-control", in sun5i-a13.dtsi. U-Boot doesn't
care, and the Linux driver interestingly doesn't make a difference. So not
sure why the new name wasn't just *added*. This would affect pre v4.19
kernels, only, so I wouldn't consider this a real problem.
- "urt,umsh-8596md-t", "simple-panel" was changed to
"bananapi,s070wv20-ct16", in sun5i-a13-q8-tablet.dts. I think U-Boot
shouldn't be affected, as panel usage is controlled via Kconfig.
For the kernel it seems to be v4.20 adding support.
- A23/A33 suffer from a change in the timer compatible string (in
sun8i-a23-a33.dtsi), requiring Linux v5.4 at least. I am not sure how
fatal this is, since we have the arch timer in those SoCs.
- More problematic seems to be the rtc compatible string change in
sun8i-a23-a33.dtsi, which restricts kernel compatibility to v5.0 and later.
I am not sure if that prevents the CCU and pinctrl to probe (because they
use the first rtc provided clock as one of their input clocks).
I wonder if having the old compatible string as a fallback is feasible: I
don't the second RTC clock used anywhere, and the RTC/clock driver doesn't
seem to make a difference between the two compatibles otherwise.
So overall this might look bad, but the breakages are:
a) only for those older generation of devices, which probably don't use
UEFI boot or otherwise rely on $fdtcontroladdr for the kernel, and
b) will probably work fine with kernel v5.4 onwards, which seems to be
reasonably old and well spread by now.
So for the sake of getting our DTs much closer to the kernel copy, I am
happy with this change.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/Makefile | 10 +-
> arch/arm/dts/axp22x.dtsi | 11 +-
> arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 16 +-
> arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 35 +-
> arch/arm/dts/sun5i-a10s-mk802.dts | 31 +-
> arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 68 +---
> arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +-
> arch/arm/dts/sun5i-a10s-wobo-i5.dts | 34 +-
> arch/arm/dts/sun5i-a10s.dtsi | 30 +-
> arch/arm/dts/sun5i-a13-ampe-a76.dts | 2 +-
> .../dts/sun5i-a13-empire-electronix-d709.dts | 41 +--
> arch/arm/dts/sun5i-a13-hsg-h702.dts | 37 +-
> arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +-
> arch/arm/dts/sun5i-a13-licheepi-one.dts | 214 +++++++++++
> arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 50 +--
> arch/arm/dts/sun5i-a13-olinuxino.dts | 56 +--
> .../dts/sun5i-a13-pocketbook-touch-lux-3.dts | 258 ++++++++++++++
> arch/arm/dts/sun5i-a13-q8-tablet.dts | 18 +-
> arch/arm/dts/sun5i-a13-utoo-p66.dts | 26 +-
> arch/arm/dts/sun5i-a13.dtsi | 23 +-
> arch/arm/dts/sun5i-gr8-chip-pro.dts | 38 +-
> arch/arm/dts/sun5i-gr8-evb.dts | 333 ++++++++++++++++++
> arch/arm/dts/sun5i-gr8.dtsi | 12 +-
> arch/arm/dts/sun5i-r8-chip.dts | 52 +--
> .../dts/sun5i-reference-design-tablet.dtsi | 57 +--
> arch/arm/dts/sun5i.dtsi | 209 +++++++----
> arch/arm/dts/sun6i-a31-app4-evb1.dts | 10 +-
> arch/arm/dts/sun6i-a31-colombus.dts | 57 +--
> arch/arm/dts/sun6i-a31-hummingbird.dts | 75 +---
> arch/arm/dts/sun6i-a31-i7.dts | 47 +--
> arch/arm/dts/sun6i-a31-m9.dts | 46 +--
> arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts | 46 +--
> arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 6 +-
> arch/arm/dts/sun6i-a31.dtsi | 218 +++++++-----
> arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts | 2 +-
> arch/arm/dts/sun6i-a31s-cs908.dts | 17 +-
> arch/arm/dts/sun6i-a31s-inet-q972.dts | 8 +-
> arch/arm/dts/sun6i-a31s-primo81.dts | 32 +-
> arch/arm/dts/sun6i-a31s-sina31s-core.dtsi | 4 +-
> arch/arm/dts/sun6i-a31s-sina31s.dts | 39 +-
> arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 144 +++++---
> .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 22 +-
> .../dts/sun6i-reference-design-tablet.dtsi | 22 +-
> arch/arm/dts/sun8i-a23-a33.dtsi | 308 ++++++++++++----
> arch/arm/dts/sun8i-a23-evb.dts | 20 +-
> arch/arm/dts/sun8i-a23-gt90h-v4.dts | 2 +-
> arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts | 73 ++++
> arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts | 73 ++++
> .../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 15 +-
> .../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 15 +-
> arch/arm/dts/sun8i-a23-q8-tablet.dts | 10 +
> arch/arm/dts/sun8i-a23.dtsi | 26 +-
> ...c-edition.dts => sun8i-a33-et-q8-v1.6.dts} | 32 +-
> arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 4 +-
> arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 14 +-
> arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts | 57 +++
> arch/arm/dts/sun8i-a33-olinuxino.dts | 12 +-
> arch/arm/dts/sun8i-a33-q8-tablet.dts | 7 +
> arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 34 +-
> arch/arm/dts/sun8i-a33.dtsi | 270 +++++---------
> arch/arm/dts/sun8i-q8-common.dtsi | 31 +-
> arch/arm/dts/sun8i-r16-bananapi-m2m.dts | 55 ++-
> .../dts/sun8i-r16-nintendo-nes-classic.dts | 54 +++
> .../sun8i-r16-nintendo-super-nes-classic.dts | 11 +
> arch/arm/dts/sun8i-r16-parrot.dts | 62 +---
> .../dts/sun8i-reference-design-tablet.dtsi | 33 +-
> arch/arm/dts/sunxi-common-regulators.dtsi | 39 --
> .../dts/sunxi-reference-design-tablet.dtsi | 11 +-
> arch/arm/mach-sunxi/Kconfig | 2 +-
> .../Nintendo_NES_Classic_Edition_defconfig | 2 +-
> 70 files changed, 2149 insertions(+), 1603 deletions(-)
> create mode 100644 arch/arm/dts/sun5i-a13-licheepi-one.dts
> create mode 100644 arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts
> create mode 100644 arch/arm/dts/sun5i-gr8-evb.dts
> create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v1.2.dts
> create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
> rename arch/arm/dts/{sun8i-r16-nintendo-nes-classic-edition.dts => sun8i-a33-et-q8-v1.6.dts} (81%)
> create mode 100644 arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
> create mode 100644 arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts
> create mode 100644 arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
>
...
> diff --git a/arch/arm/dts/sun5i-a13-q8-tablet.dts b/arch/arm/dts/sun5i-a13-q8-tablet.dts
> index a89f29fa3e..f9fc1c8b60 100644
> --- a/arch/arm/dts/sun5i-a13-q8-tablet.dts
> +++ b/arch/arm/dts/sun5i-a13-q8-tablet.dts
> @@ -49,19 +49,13 @@
> compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
>
> panel: panel {
> - compatible = "urt,umsh-8596md-t", "simple-panel";
> - #address-cells = <1>;
> - #size-cells = <0>;
> + compatible = "bananapi,s070wv20-ct16";
This drops the "simple-panel" fallback compatible, and replaces it just a
device specific one. This means you need at least Linux v4.20 to use the
display.
> + power-supply = <®_vcc3v3>;
> + enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
> + backlight = <&backlight>;
>
> - port@0 {
> - reg = <0>;
> - /* TODO: lcd panel uses axp gpio0 as enable pin */
> - backlight = <&backlight>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - panel_input: endpoint@0 {
> - reg = <0>;
> + port {
> + panel_input: endpoint {
> remote-endpoint = <&tcon0_out_lcd>;
> };
> };
[ ... ]
> diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi
> index 07f2248ed5..250d6b87ab 100644
> --- a/arch/arm/dts/sun5i.dtsi
> +++ b/arch/arm/dts/sun5i.dtsi
> @@ -42,14 +42,14 @@
> * OTHER DEALINGS IN THE SOFTWARE.
> */
>
> -#include "skeleton.dtsi"
> -
> #include <dt-bindings/clock/sun5i-ccu.h>
> #include <dt-bindings/dma/sun4i-a10.h>
> #include <dt-bindings/reset/sun5i-ccu.h>
>
> / {
> interrupt-parent = <&intc>;
> + #address-cells = <1>;
> + #size-cells = <1>;
>
> cpus {
> #address-cells = <1>;
> @@ -68,7 +68,7 @@
> #size-cells = <1>;
> ranges;
>
> - framebuffer@0 {
> + framebuffer-lcd0 {
> compatible = "allwinner,simple-framebuffer",
> "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0";
> @@ -77,7 +77,7 @@
> status = "disabled";
> };
>
> - framebuffer@1 {
> + framebuffer-lcd0-tve0 {
> compatible = "allwinner,simple-framebuffer",
> "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0-tve0";
> @@ -93,14 +93,14 @@
> #size-cells = <1>;
> ranges;
>
> - osc24M: clk@1c20050 {
> + osc24M: clk-24M {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <24000000>;
> clock-output-names = "osc24M";
> };
>
> - osc32k: clk@0 {
> + osc32k: clk-32k {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <32768>;
> @@ -108,14 +108,30 @@
> };
> };
>
> - soc@1c00000 {
> + reserved-memory {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
> + default-pool {
> + compatible = "shared-dma-pool";
> + size = <0x6000000>;
> + alloc-ranges = <0x40000000 0x10000000>;
> + reusable;
> + linux,cma-default;
> + };
> + };
> +
> + soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> + dma-ranges;
> ranges;
>
> - sram-controller@1c00000 {
> - compatible = "allwinner,sun4i-a10-sram-controller";
> + system-control@1c00000 {
> + compatible = "allwinner,sun5i-a13-system-control";
This is a change in the compatible string. Linux kernels before v4.19 won't
have a driver matching this new string, so will fail to use that device.
This would affect USB OTG and EMAC operation.
> reg = <0x01c00000 0x30>;
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -127,12 +143,13 @@
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0x00000000 0xc000>;
> - };
>
> - emac_sram: sram-section@8000 {
> - compatible = "allwinner,sun4i-a10-sram-a3-a4";
> - reg = <0x8000 0x4000>;
> - status = "disabled";
> + emac_sram: sram-section@8000 {
> + compatible = "allwinner,sun5i-a13-sram-a3-a4",
> + "allwinner,sun4i-a10-sram-a3-a4";
> + reg = <0x8000 0x4000>;
> + status = "disabled";
> + };
> };
>
> sram_d: sram@10000 {
[ ... ]
> diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi
> index 44f3cad3de..a42fac676b 100644
> --- a/arch/arm/dts/sun8i-a23-a33.dtsi
> +++ b/arch/arm/dts/sun8i-a23-a33.dtsi
> @@ -42,8 +42,6 @@
> * OTHER DEALINGS IN THE SOFTWARE.
> */
>
> -#include "skeleton.dtsi"
> -
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
> @@ -51,13 +49,15 @@
>
> / {
> interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
>
> chosen {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> - simplefb_lcd: framebuffer@0 {
> + simplefb_lcd: framebuffer-lcd0 {
> compatible = "allwinner,simple-framebuffer",
> "simple-framebuffer";
> allwinner,pipeline = "de_be0-lcd0";
> @@ -68,6 +68,12 @@
> };
> };
>
> + de: display-engine {
> + /* compatible gets set in SoC specific dtsi file */
> + allwinner,pipelines = <&fe0>;
> + status = "disabled";
> + };
> +
> timer {
> compatible = "arm,armv7-timer";
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> @@ -118,12 +124,34 @@
> };
> };
>
> - soc@1c00000 {
> + soc {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
>
> + system-control@1c00000 {
> + compatible = "allwinner,sun8i-a23-system-control";
> + reg = <0x01c00000 0x30>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_c: sram@1d00000 {
> + compatible = "mmio-sram";
> + reg = <0x01d00000 0x80000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x01d00000 0x80000>;
> +
> + ve_sram: sram-section@0 {
> + compatible = "allwinner,sun8i-a23-sram-c1",
> + "allwinner,sun4i-a10-sram-c1";
> + reg = <0x000000 0x80000>;
> + };
> + };
> + };
> +
> dma: dma-controller@1c02000 {
> compatible = "allwinner,sun8i-a23-dma";
> reg = <0x01c02000 0x1000>;
> @@ -133,6 +161,60 @@
> #dma-cells = <1>;
> };
>
> + nfc: nand-controller@1c03000 {
> + compatible = "allwinner,sun8i-a23-nand-controller";
> + reg = <0x01c03000 0x1000>;
> + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_NAND>;
> + reset-names = "ahb";
> + dmas = <&dma 5>;
> + dma-names = "rxtx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&nand_pins &nand_cs0_pin &nand_rb0_pin>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + tcon0: lcd-controller@1c0c000 {
> + /* compatible gets set in SoC specific dtsi file */
> + reg = <0x01c0c000 0x1000>;
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma 12>;
> + clocks = <&ccu CLK_BUS_LCD>,
> + <&ccu CLK_LCD_CH0>,
> + <&ccu 13>;
> + clock-names = "ahb",
> + "tcon-ch0",
> + "lvds-alt";
> + clock-output-names = "tcon-pixel-clock";
> + #clock-cells = <0>;
> + resets = <&ccu RST_BUS_LCD>,
> + <&ccu RST_BUS_LVDS>;
> + reset-names = "lcd",
> + "lvds";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tcon0_in: port@0 {
> + reg = <0>;
> +
> + tcon0_in_drc0: endpoint {
> + remote-endpoint = <&drc0_out_tcon0>;
> + };
> + };
> +
> + tcon0_out: port@1 {
> + reg = <1>;
> + };
> + };
> + };
> +
> mmc0: mmc@1c0f000 {
> compatible = "allwinner,sun7i-a20-mmc";
> reg = <0x01c0f000 0x1000>;
> @@ -147,6 +229,8 @@
> resets = <&ccu RST_BUS_MMC0>;
> reset-names = "ahb";
> interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -190,21 +274,6 @@
> #size-cells = <0>;
> };
>
> - nfc: nand@1c03000 {
> - compatible = "allwinner,sun4i-a10-nand";
> - reg = <0x01c03000 0x1000>;
> - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
> - clock-names = "ahb", "mod";
> - resets = <&ccu RST_BUS_NAND>;
> - reset-names = "ahb";
> - pinctrl-names = "default";
> - pinctrl-0 = <&nand_pins &nand_pins_cs0 &nand_pins_rb0>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> usb_otg: usb@1c19000 {
> /* compatible gets set in SoC specific dtsi file */
> reg = <0x01c19000 0x0400>;
> @@ -215,6 +284,7 @@
> phys = <&usbphy 0>;
> phy-names = "usb";
> extcon = <&usbphy 0>;
> + dr_mode = "otg";
> status = "disabled";
> };
>
> @@ -276,22 +346,30 @@
> #interrupt-cells = <3>;
> #gpio-cells = <3>;
>
> - uart0_pins_a: uart0@0 {
> - pins = "PF2", "PF4";
> - function = "uart0";
> + i2c0_pins: i2c0-pins {
> + pins = "PH2", "PH3";
> + function = "i2c0";
> };
>
> - uart1_pins_a: uart1@0 {
> - pins = "PG6", "PG7";
> - function = "uart1";
> + i2c1_pins: i2c1-pins {
> + pins = "PH4", "PH5";
> + function = "i2c1";
> };
>
> - uart1_pins_cts_rts_a: uart1-cts-rts@0 {
> - pins = "PG8", "PG9";
> - function = "uart1";
> + i2c2_pins: i2c2-pins {
> + pins = "PE12", "PE13";
> + function = "i2c2";
> };
>
> - mmc0_pins_a: mmc0@0 {
> + lcd_rgb666_pins: lcd-rgb666-pins {
> + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
> + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
> + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
> + "PD24", "PD25", "PD26", "PD27";
> + function = "lcd0";
> + };
> +
> + mmc0_pins: mmc0-pins {
> pins = "PF0", "PF1", "PF2",
> "PF3", "PF4", "PF5";
> function = "mmc0";
> @@ -299,7 +377,7 @@
> bias-pull-up;
> };
>
> - mmc1_pins_a: mmc1@0 {
> + mmc1_pg_pins: mmc1-pg-pins {
> pins = "PG0", "PG1", "PG2",
> "PG3", "PG4", "PG5";
> function = "mmc1";
> @@ -307,7 +385,7 @@
> bias-pull-up;
> };
>
> - mmc2_8bit_pins: mmc2_8bit {
> + mmc2_8bit_pins: mmc2-8bit-pins {
> pins = "PC5", "PC6", "PC8",
> "PC9", "PC10", "PC11",
> "PC12", "PC13", "PC14",
> @@ -324,61 +402,53 @@
> function = "nand0";
> };
>
> - nand_pins_cs0: nand-pins-cs0 {
> + nand_cs0_pin: nand-cs0-pin {
> pins = "PC4";
> function = "nand0";
> bias-pull-up;
> };
>
> - nand_pins_cs1: nand-pins-cs1 {
> + nand_cs1_pin: nand-cs1-pin {
> pins = "PC3";
> function = "nand0";
> bias-pull-up;
> };
>
> - nand_pins_rb0: nand-pins-rb0 {
> + nand_rb0_pin: nand-rb0-pin {
> pins = "PC6";
> function = "nand0";
> bias-pull-up;
> };
>
> - nand_pins_rb1: nand-pins-rb1 {
> + nand_rb1_pin: nand-rb1-pin {
> pins = "PC7";
> function = "nand0";
> bias-pull-up;
> };
>
> - pwm0_pins: pwm0 {
> + pwm0_pin: pwm0-pin {
> pins = "PH0";
> function = "pwm0";
> };
>
> - i2c0_pins_a: i2c0@0 {
> - pins = "PH2", "PH3";
> - function = "i2c0";
> - };
> -
> - i2c1_pins_a: i2c1@0 {
> - pins = "PH4", "PH5";
> - function = "i2c1";
> + uart0_pf_pins: uart0-pf-pins {
> + pins = "PF2", "PF4";
> + function = "uart0";
> };
>
> - i2c2_pins_a: i2c2@0 {
> - pins = "PE12", "PE13";
> - function = "i2c2";
> + uart1_pg_pins: uart1-pg-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> };
>
> - lcd_rgb666_pins: lcd-rgb666@0 {
> - pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
> - "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
> - "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
> - "PD24", "PD25", "PD26", "PD27";
> - function = "lcd0";
> + uart1_cts_rts_pg_pins: uart1-cts-rts-pg-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> };
> };
>
> timer@1c20c00 {
> - compatible = "allwinner,sun4i-a10-timer";
> + compatible = "allwinner,sun8i-a23-timer";
This changes the compatible string, which only started to be supported
with Linux v5.4. Any older kernel would not be able to use that timer, but
with the arch timer stepping up, we don't lose too much, I guess?
> reg = <0x01c20c00 0xa0>;
> interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> @@ -389,6 +459,7 @@
> compatible = "allwinner,sun6i-a31-wdt";
> reg = <0x01c20ca0 0x20>;
> interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> pwm: pwm@1c21400 {
> @@ -477,6 +548,8 @@
> interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_I2C0>;
> resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -488,6 +561,8 @@
> interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_I2C1>;
> resets = <&ccu RST_BUS_I2C1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins>;
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -499,6 +574,8 @@
> interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_I2C2>;
> resets = <&ccu RST_BUS_I2C2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins>;
> status = "disabled";
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -532,7 +609,7 @@
> };
>
> gic: interrupt-controller@1c81000 {
> - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> + compatible = "arm,gic-400";
> reg = <0x01c81000 0x1000>,
> <0x01c82000 0x2000>,
> <0x01c84000 0x2000>,
> @@ -542,17 +619,104 @@
> interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> };
>
> + fe0: display-frontend@1e00000 {
> + /* compatible gets set in SoC specific dtsi file */
> + reg = <0x01e00000 0x20000>;
> + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>,
> + <&ccu CLK_DRAM_DE_FE>;
> + clock-names = "ahb", "mod",
> + "ram";
> + resets = <&ccu RST_BUS_DE_FE>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + fe0_out: port@1 {
> + reg = <1>;
> +
> + fe0_out_be0: endpoint {
> + remote-endpoint = <&be0_in_fe0>;
> + };
> + };
> + };
> + };
> +
> + be0: display-backend@1e60000 {
> + /* compatible gets set in SoC specific dtsi file */
> + reg = <0x01e60000 0x10000>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>,
> + <&ccu CLK_DRAM_DE_BE>;
> + clock-names = "ahb", "mod",
> + "ram";
> + resets = <&ccu RST_BUS_DE_BE>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + be0_in: port@0 {
> + reg = <0>;
> +
> + be0_in_fe0: endpoint {
> + remote-endpoint = <&fe0_out_be0>;
> + };
> + };
> +
> + be0_out: port@1 {
> + reg = <1>;
> +
> + be0_out_drc0: endpoint {
> + remote-endpoint = <&drc0_in_be0>;
> + };
> + };
> + };
> + };
> +
> + drc0: drc@1e70000 {
> + /* compatible gets set in SoC specific dtsi file */
> + reg = <0x01e70000 0x10000>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>,
> + <&ccu CLK_DRAM_DRC>;
> + clock-names = "ahb", "mod", "ram";
> + resets = <&ccu RST_BUS_DRC>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + drc0_in: port@0 {
> + reg = <0>;
> +
> + drc0_in_be0: endpoint {
> + remote-endpoint = <&be0_out_drc0>;
> + };
> + };
> +
> + drc0_out: port@1 {
> + reg = <1>;
> +
> + drc0_out_tcon0: endpoint {
> + remote-endpoint = <&tcon0_in_drc0>;
> + };
> + };
> + };
> + };
> +
> rtc: rtc@1f00000 {
> - compatible = "allwinner,sun6i-a31-rtc";
> - reg = <0x01f00000 0x54>;
> + compatible = "allwinner,sun8i-a23-rtc";
This changes the compatible string, requiring a Linux v5.0 kernel or later
to work. While we can probably get over the loss of the actual real-time
clock, it is also a clock provider, and the provided clock is used by the
CCU and pinctrl drivers.
> + reg = <0x01f00000 0x400>;
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> - clock-output-names = "osc32k";
> + clock-output-names = "osc32k", "osc32k-out";
> clocks = <&ext_osc32k>;
> #clock-cells = <1>;
> };
>
> - nmi_intc: interrupt-controller@1f00c00 {
> + r_intc: interrupt-controller@1f00c00 {
> compatible = "allwinner,sun6i-a31-r-intc";
> interrupt-controller;
> #interrupt-cells = <2>;
> @@ -624,6 +788,20 @@
> status = "disabled";
> };
>
> + r_i2c: i2c@1f02400 {
> + compatible = "allwinner,sun8i-a23-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x01f02400 0x400>;
> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_i2c_pins>;
> + clocks = <&apb0_gates 6>;
> + resets = <&apb0_rst 6>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> r_pio: pinctrl@1f02c00 {
> compatible = "allwinner,sun8i-a23-r-pinctrl";
> reg = <0x01f02c00 0x400>;
> @@ -634,18 +812,22 @@
> gpio-controller;
> interrupt-controller;
> #interrupt-cells = <3>;
> - #address-cells = <1>;
> - #size-cells = <0>;
> #gpio-cells = <3>;
>
> - r_rsb_pins: r_rsb {
> + r_i2c_pins: r-i2c-pins {
> + pins = "PL0", "PL1";
> + function = "s_i2c";
> + bias-pull-up;
> + };
> +
> + r_rsb_pins: r-rsb-pins {
> pins = "PL0", "PL1";
> function = "s_rsb";
> drive-strength = <20>;
> bias-pull-up;
> };
>
> - r_uart_pins_a: r_uart@0 {
> + r_uart_pins_a: r-uart-pins {
> pins = "PL2", "PL3";
> function = "s_uart";
> };
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 09/12] ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 09/12] ARM: dts: sun8i: V3/V3s/S3: " Samuel Holland
@ 2022-05-22 22:22 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-22 22:22 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:28 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Copy the devicetree source for the V3(s)/S3 SoCs and all existing boards
> verbatim from the Linux v5.18-rc1 tag.
>
> This commit also adds the following new board devicetrees:
> - sun8i-s3-elimo-initium.dts
> - sun8i-v3-sl631-imx179.dts
>
> This update should not impact any existing U-Boot functionality.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
The files are identical to those in the kernel tree, and the changes
look fine, from a compatibility point of view.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/sun8i-s3-elimo-impetus.dtsi | 44 ++++++
> arch/arm/dts/sun8i-s3-elimo-initium.dts | 29 ++++
> arch/arm/dts/sun8i-s3-pinecube.dts | 13 +-
> arch/arm/dts/sun8i-v3-sl631-imx179.dts | 12 ++
> arch/arm/dts/sun8i-v3-sl631.dtsi | 138 ++++++++++++++++++
> arch/arm/dts/sun8i-v3.dtsi | 36 +++++
> arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 17 ++-
> arch/arm/dts/sun8i-v3s.dtsi | 93 ++++++++++--
> 9 files changed, 358 insertions(+), 26 deletions(-)
> create mode 100644 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
> create mode 100644 arch/arm/dts/sun8i-s3-elimo-initium.dts
> create mode 100644 arch/arm/dts/sun8i-v3-sl631-imx179.dts
> create mode 100644 arch/arm/dts/sun8i-v3-sl631.dtsi
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index bbd69d3a67..059ac7fad8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -670,7 +670,9 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \
> sun8i-r40-bananapi-m2-ultra.dtb \
> sun8i-v40-bananapi-m2-berry.dtb
> dtb-$(CONFIG_MACH_SUN8I_V3S) += \
> + sun8i-s3-elimo-initium.dtb \
> sun8i-s3-pinecube.dtb \
> + sun8i-v3-sl631-imx179.dtb \
> sun8i-v3s-licheepi-zero.dtb
> dtb-$(CONFIG_MACH_SUN50I_H5) += \
> sun50i-h5-bananapi-m2-plus.dtb \
> diff --git a/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
> new file mode 100644
> index 0000000000..052b010a56
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
> @@ -0,0 +1,44 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
> + */
> +
> +/dts-v1/;
> +#include "sun8i-v3.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +/ {
> + model = "Elimo Impetus SoM";
> + compatible = "elimo,impetus", "sochip,s3", "allwinner,sun8i-v3";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&mmc0 {
> + broken-cd;
> + bus-width = <4>;
> + vmmc-supply = <®_vcc3v3>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun8i-s3-elimo-initium.dts b/arch/arm/dts/sun8i-s3-elimo-initium.dts
> new file mode 100644
> index 0000000000..039677c2cc
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-s3-elimo-initium.dts
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2020 Matteo Scordino <matteo@elimo.io>
> + */
> +
> +/dts-v1/;
> +#include "sun8i-s3-elimo-impetus.dtsi"
> +
> +/ {
> + model = "Elimo Initium";
> + compatible = "elimo,initium", "elimo,impetus", "sochip,s3",
> + "allwinner,sun8i-v3";
> +
> + aliases {
> + serial1 = &uart1;
> + };
> +};
> +
> +&uart1 {
> + pinctrl-0 = <&uart1_pg_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&emac {
> + phy-handle = <&int_mii_phy>;
> + phy-mode = "mii";
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts b/arch/arm/dts/sun8i-s3-pinecube.dts
> index 9bab6b7f40..20966e954e 100644
> --- a/arch/arm/dts/sun8i-s3-pinecube.dts
> +++ b/arch/arm/dts/sun8i-s3-pinecube.dts
> @@ -10,7 +10,7 @@
>
> / {
> model = "PineCube IP Camera";
> - compatible = "pine64,pinecube", "allwinner,sun8i-s3";
> + compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
>
> aliases {
> serial0 = &uart2;
> @@ -64,9 +64,6 @@
> status = "okay";
>
> port {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> csi1_ep: endpoint {
> remote-endpoint = <&ov5640_ep>;
> bus-width = <8>;
> @@ -88,13 +85,9 @@
> status = "okay";
>
> axp209: pmic@34 {
> - compatible = "x-powers,axp203",
> - "x-powers,axp209";
> reg = <0x34>;
> - interrupt-parent = <&gic>;
> - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-controller;
> - #interrupt-cells = <1>;
> + interrupt-parent = <&nmi_intc>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> };
> };
>
> diff --git a/arch/arm/dts/sun8i-v3-sl631-imx179.dts b/arch/arm/dts/sun8i-v3-sl631-imx179.dts
> new file mode 100644
> index 0000000000..117aeece4e
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-v3-sl631-imx179.dts
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> +/*
> + * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
> + */
> +
> +#include "sun8i-v3-sl631.dtsi"
> +
> +/ {
> + model = "SL631 Action Camera with IMX179";
> + compatible = "allwinner,sl631-imx179", "allwinner,sl631",
> + "allwinner,sun8i-v3";
> +};
> diff --git a/arch/arm/dts/sun8i-v3-sl631.dtsi b/arch/arm/dts/sun8i-v3-sl631.dtsi
> new file mode 100644
> index 0000000000..6f93f8c49f
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-v3-sl631.dtsi
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR X11)
> +/*
> + * Copyright 2020 Paul Kocialkowski <contact@paulk.fr>
> + */
> +
> +/dts-v1/;
> +
> +#include "sun8i-v3.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "SL631 Action Camera";
> + compatible = "allwinner,sl631", "allwinner,sun8i-v3";
> +
> + aliases {
> + serial0 = &uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + axp209: pmic@34 {
> + reg = <0x34>;
> + interrupt-parent = <&nmi_intc>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pb_pins>;
> + status = "okay";
> +};
> +
> +&lradc {
> + vref-supply = <®_ldo2>;
> + status = "okay";
> +
> + button-174 {
> + label = "Down";
> + linux,code = <KEY_DOWN>;
> + channel = <0>;
> + voltage = <174603>;
> + };
> +
> + button-384 {
> + label = "Up";
> + linux,code = <KEY_UP>;
> + channel = <0>;
> + voltage = <384126>;
> + };
> +
> + button-593 {
> + label = "OK";
> + linux,code = <KEY_OK>;
> + channel = <0>;
> + voltage = <593650>;
> + };
> +};
> +
> +&mmc0 {
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> + bus-width = <4>;
> + vmmc-supply = <®_dcdc3>;
> + status = "okay";
> +};
> +
> +&pio {
> + vcc-pd-supply = <®_dcdc3>;
> + vcc-pe-supply = <®_dcdc3>;
> +};
> +
> +#include "axp209.dtsi"
> +
> +&ac_power_supply {
> + status = "okay";
> +};
> +
> +&battery_power_supply {
> + status = "okay";
> +};
> +
> +®_dcdc2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1250000>;
> + regulator-max-microvolt = <1250000>;
> + regulator-name = "vdd-sys-cpu";
> +};
> +
> +®_dcdc3 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vdd-3v3";
> +};
> +
> +®_ldo1 {
> + regulator-name = "vdd-rtc";
> +};
> +
> +®_ldo2 {
> + regulator-always-on;
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-name = "avcc";
> +};
> +
> +&spi0 {
> + status = "okay";
> +
> + flash@0 {
> + reg = <0>;
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + };
> +};
> +
> +&uart1 {
> + pinctrl-0 = <&uart1_pg_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "peripheral";
> + status = "okay";
> +};
> +
> +&usbphy {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun8i-v3.dtsi b/arch/arm/dts/sun8i-v3.dtsi
> index ca4672ed2e..186c30cbe6 100644
> --- a/arch/arm/dts/sun8i-v3.dtsi
> +++ b/arch/arm/dts/sun8i-v3.dtsi
> @@ -1,14 +1,40 @@
> // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> /*
> * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
> + * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
> */
>
> #include "sun8i-v3s.dtsi"
>
> +/ {
> + soc {
> + i2s0: i2s@1c22000 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun8i-v3-i2s",
> + "allwinner,sun8i-h3-i2s";
> + reg = <0x01c22000 0x400>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
> + clock-names = "apb", "mod";
> + dmas = <&dma 3>, <&dma 3>;
> + dma-names = "rx", "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0_pins>;
> + resets = <&ccu RST_BUS_I2S0>;
> + status = "disabled";
> + };
> + };
> +};
> +
> &ccu {
> compatible = "allwinner,sun8i-v3-ccu";
> };
>
> +&codec_analog {
> + compatible = "allwinner,sun8i-v3-codec-analog",
> + "allwinner,sun8i-h3-codec-analog";
> +};
> +
> &emac {
> /delete-property/ phy-handle;
> /delete-property/ phy-mode;
> @@ -24,4 +50,14 @@
>
> &pio {
> compatible = "allwinner,sun8i-v3-pinctrl";
> +
> + i2s0_pins: i2s0-pins {
> + pins = "PG10", "PG11", "PG12", "PG13";
> + function = "i2s";
> + };
> +
> + uart1_pg_pins: uart1-pg-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> };
> diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
> index db5cd0b857..752ad05c8f 100644
> --- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
> +++ b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
> @@ -49,16 +49,18 @@
> compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
> "allwinner,sun8i-v3s";
>
> + aliases {
> + ethernet0 = &emac;
> + };
> +
> leds {
> /* The LEDs use PG0~2 pins, which conflict with MMC1 */
> status = "disabled";
> };
> };
>
> -&mmc1 {
> - broken-cd;
> - bus-width = <4>;
> - vmmc-supply = <®_vcc3v3>;
> +&emac {
> + allwinner,leds-active-low;
> status = "okay";
> };
>
> @@ -94,3 +96,10 @@
> voltage = <800000>;
> };
> };
> +
> +&mmc1 {
> + broken-cd;
> + bus-width = <4>;
> + vmmc-supply = <®_vcc3v3>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun8i-v3s.dtsi b/arch/arm/dts/sun8i-v3s.dtsi
> index 0c73416769..084323d5c6 100644
> --- a/arch/arm/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/dts/sun8i-v3s.dtsi
> @@ -1,5 +1,6 @@
> /*
> * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> + * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
> *
> * This file is dual-licensed: you can use it either under the terms
> * of the GPL or the X11 license, at your option. Note that this dual
> @@ -157,12 +158,30 @@
> syscon: system-control@1c00000 {
> compatible = "allwinner,sun8i-v3s-system-control",
> "allwinner,sun8i-h3-system-control";
> - reg = <0x01c00000 0x1000>;
> + reg = <0x01c00000 0xd0>;
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
> };
>
> + nmi_intc: interrupt-controller@1c000d0 {
> + compatible = "allwinner,sun8i-v3s-nmi",
> + "allwinner,sun9i-a80-nmi";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x01c000d0 0x0c>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + dma: dma-controller@1c02000 {
> + compatible = "allwinner,sun8i-v3s-dma";
> + reg = <0x01c02000 0x1000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_DMA>;
> + resets = <&ccu RST_BUS_DMA>;
> + #dma-cells = <1>;
> + };
> +
> tcon0: lcd-controller@1c0c000 {
> compatible = "allwinner,sun8i-v3s-tcon";
> reg = <0x01c0c000 0x1000>;
> @@ -266,6 +285,8 @@
> interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
> clock-names = "ahb", "mod";
> + dmas = <&dma 16>, <&dma 16>;
> + dma-names = "rx", "tx";
> resets = <&ccu RST_BUS_CE>;
> reset-names = "ahb";
> };
> @@ -328,6 +349,12 @@
> interrupt-controller;
> #interrupt-cells = <3>;
>
> + /omit-if-no-ref/
> + csi0_mclk_pin: csi0-mclk-pin {
> + pins = "PE20";
> + function = "csi_mipi";
> + };
> +
> /omit-if-no-ref/
> csi1_8bit_pins: csi1-8bit-pins {
> pins = "PE0", "PE2", "PE3", "PE8", "PE9",
> @@ -347,6 +374,12 @@
> function = "i2c0";
> };
>
> + /omit-if-no-ref/
> + i2c1_pb_pins: i2c1-pb-pins {
> + pins = "PB8", "PB9";
> + function = "i2c1";
> + };
> +
> /omit-if-no-ref/
> i2c1_pe_pins: i2c1-pe-pins {
> pins = "PE21", "PE22";
> @@ -401,6 +434,15 @@
> clocks = <&osc24M>;
> };
>
> + pwm: pwm@1c21400 {
> + compatible = "allwinner,sun8i-v3s-pwm",
> + "allwinner,sun7i-a20-pwm";
> + reg = <0x01c21400 0xc>;
> + clocks = <&osc24M>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> lradc: lradc@1c22800 {
> compatible = "allwinner,sun4i-a10-lradc-keys";
> reg = <0x01c22800 0x400>;
> @@ -408,6 +450,25 @@
> status = "disabled";
> };
>
> + codec: codec@1c22c00 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun8i-v3s-codec";
> + reg = <0x01c22c00 0x400>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
> + clock-names = "apb", "codec";
> + resets = <&ccu RST_BUS_CODEC>;
> + dmas = <&dma 15>, <&dma 15>;
> + dma-names = "rx", "tx";
> + allwinner,codec-analog-controls = <&codec_analog>;
> + status = "disabled";
> + };
> +
> + codec_analog: codec-analog@1c23000 {
> + compatible = "allwinner,sun8i-v3s-codec-analog";
> + reg = <0x01c23000 0x4>;
> + };
> +
> uart0: serial@1c28000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x01c28000 0x400>;
> @@ -415,6 +476,8 @@
> reg-shift = <2>;
> reg-io-width = <4>;
> clocks = <&ccu CLK_BUS_UART0>;
> + dmas = <&dma 6>, <&dma 6>;
> + dma-names = "rx", "tx";
> resets = <&ccu RST_BUS_UART0>;
> status = "disabled";
> };
> @@ -426,6 +489,8 @@
> reg-shift = <2>;
> reg-io-width = <4>;
> clocks = <&ccu CLK_BUS_UART1>;
> + dmas = <&dma 7>, <&dma 7>;
> + dma-names = "rx", "tx";
> resets = <&ccu RST_BUS_UART1>;
> status = "disabled";
> };
> @@ -437,6 +502,8 @@
> reg-shift = <2>;
> reg-io-width = <4>;
> clocks = <&ccu CLK_BUS_UART2>;
> + dmas = <&dma 8>, <&dma 8>;
> + dma-names = "rx", "tx";
> resets = <&ccu RST_BUS_UART2>;
> pinctrl-0 = <&uart2_pins>;
> pinctrl-names = "default";
> @@ -516,6 +583,8 @@
> interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> clock-names = "ahb", "mod";
> + dmas = <&dma 23>, <&dma 23>;
> + dma-names = "rx", "tx";
> pinctrl-names = "default";
> pinctrl-0 = <&spi0_pins>;
> resets = <&ccu RST_BUS_SPI0>;
> @@ -524,6 +593,17 @@
> #size-cells = <0>;
> };
>
> + gic: interrupt-controller@1c81000 {
> + compatible = "arm,gic-400";
> + reg = <0x01c81000 0x1000>,
> + <0x01c82000 0x2000>,
> + <0x01c84000 0x2000>,
> + <0x01c86000 0x2000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> csi1: camera@1cb4000 {
> compatible = "allwinner,sun8i-v3s-csi";
> reg = <0x01cb4000 0x3000>;
> @@ -535,16 +615,5 @@
> resets = <&ccu RST_BUS_CSI>;
> status = "disabled";
> };
> -
> - gic: interrupt-controller@1c81000 {
> - compatible = "arm,gic-400";
> - reg = <0x01c81000 0x1000>,
> - <0x01c82000 0x1000>,
> - <0x01c84000 0x2000>,
> - <0x01c86000 0x2000>;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> - };
> };
> };
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 10/12] ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 10/12] ARM: dts: sun8i: R40/T3: " Samuel Holland
@ 2022-05-22 22:38 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-22 22:38 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:29 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Copy the devicetree for the R40/T3 SoC verbatim from the Linux v5.18-rc1
> tag. None of the existing boards had any devicetree updates.
>
> This commit adds the following new board devicetrees:
> - sun8i-r40-oka40i-c.dts
> - sun8i-t3-cqa3t-bv3.dts
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
The files are identical to the kernel versions, and I see only
additions, so there should be no change of behaviour.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/sun8i-r40-feta40i.dtsi | 106 +++++++++++++
> arch/arm/dts/sun8i-r40-oka40i-c.dts | 203 +++++++++++++++++++++++++
> arch/arm/dts/sun8i-r40.dtsi | 118 ++++++++++++++-
> arch/arm/dts/sun8i-t3-cqa3t-bv3.dts | 226 ++++++++++++++++++++++++++++
> 5 files changed, 653 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm/dts/sun8i-r40-feta40i.dtsi
> create mode 100644 arch/arm/dts/sun8i-r40-oka40i-c.dts
> create mode 100644 arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 059ac7fad8..95909ef037 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -668,6 +668,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
> sun8i-h3-zeropi.dtb
> dtb-$(CONFIG_MACH_SUN8I_R40) += \
> sun8i-r40-bananapi-m2-ultra.dtb \
> + sun8i-r40-oka40i-c.dtb \
> + sun8i-t3-cqa3t-bv3.dtb \
> sun8i-v40-bananapi-m2-berry.dtb
> dtb-$(CONFIG_MACH_SUN8I_V3S) += \
> sun8i-s3-elimo-initium.dtb \
> diff --git a/arch/arm/dts/sun8i-r40-feta40i.dtsi b/arch/arm/dts/sun8i-r40-feta40i.dtsi
> new file mode 100644
> index 0000000000..265e0fa57a
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-r40-feta40i.dtsi
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
> +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +#include "sun8i-r40.dtsi"
> +
> +&i2c0 {
> + status = "okay";
> +
> + axp22x: pmic@34 {
> + compatible = "x-powers,axp221";
> + reg = <0x34>;
> + interrupt-parent = <&nmi_intc>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +#include "axp22x.dtsi"
> +
> +&mmc2 {
> + vmmc-supply = <®_dcdc1>;
> + vqmmc-supply = <®_aldo2>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&pio {
> + pinctrl-names = "default";
> + pinctrl-0 = <&clk_out_a_pin>;
> + vcc-pa-supply = <®_dcdc1>;
> + vcc-pc-supply = <®_aldo2>;
> + vcc-pd-supply = <®_dcdc1>;
> + vcc-pf-supply = <®_dldo4>;
> + vcc-pg-supply = <®_dldo1>;
> +};
> +
> +®_aldo2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc-pa";
> +};
> +
> +®_aldo3 {
> + regulator-always-on;
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-name = "avcc";
> +};
> +
> +®_dcdc1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-3v3";
> +};
> +
> +®_dcdc2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-name = "vdd-cpu";
> +};
> +
> +®_dcdc3 {
> + regulator-always-on;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-name = "vdd-sys";
> +};
> +
> +®_dcdc5 {
> + regulator-always-on;
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-name = "vcc-dram";
> +};
> +
> +®_dldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-wifi-io";
> +};
> +
> +®_dldo4 {
> + regulator-always-on;
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-name = "vdd2v5-sata";
> +};
> +
> +®_eldo2 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-name = "vdd1v2-sata";
> +};
> +
> +®_eldo3 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-name = "vcc-pe";
> +};
> diff --git a/arch/arm/dts/sun8i-r40-oka40i-c.dts b/arch/arm/dts/sun8i-r40-oka40i-c.dts
> new file mode 100644
> index 0000000000..0bd1336206
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-r40-oka40i-c.dts
> @@ -0,0 +1,203 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
> +// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
> +// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> +// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> +
> +/dts-v1/;
> +#include "sun8i-r40-feta40i.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> + model = "Forlinx OKA40i-C";
> + compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40";
> +
> + aliases {
> + ethernet0 = &gmac;
> + serial0 = &uart0;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5; /* RS485 */
> + serial7 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + connector {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + led-5 { /* this is how the leds are labeled on the board */
> + gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
> + color = <LED_COLOR_ID_GREEN>;
> + function = LED_FUNCTION_STATUS;
> + };
> +
> + led-6 {
> + gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
> + color = <LED_COLOR_ID_BLUE>;
> + function = LED_FUNCTION_STATUS;
> + };
> + };
> +
> + reg_vcc5v0: vcc5v0 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
> + clocks = <&ccu CLK_OUTA>;
> + clock-names = "ext_clock";
> + };
> +};
> +
> +&ahci {
> + ahci-supply = <®_dldo4>;
> + phy-supply = <®_eldo2>;
> + status = "okay";
> +};
> +
> +&de {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci2 {
> + status = "okay";
> +};
> +
> +&gmac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&gmac_rgmii_pins>;
> + phy-handle = <&phy1>;
> + phy-mode = "rgmii-id";
> + phy-supply = <®_dcdc1>;
> + status = "okay";
> +};
> +
> +&gmac_mdio {
> + phy1: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + };
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + vmmc-supply = <®_dcdc1>;
> + vqmmc-supply = <®_dcdc1>;
> + bus-width = <4>;
> + cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
> + status = "okay";
> +};
> +
> +&mmc3 {
> + vmmc-supply = <®_dcdc1>;
> + vqmmc-supply = <®_dcdc1>;
> + bus-width = <4>;
> + cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&ohci2 {
> + status = "okay";
> +};
> +
> +®_dc1sw {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-lcd";
> +};
> +
> +®_dldo2 {
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-wifi";
> +};
> +
> +&tcon_tv0 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pb_pins>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart4_pg_pins>;
> + status = "okay";
> +};
> +
> +&uart5 { /* RS485 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart5_ph_pins>;
> + status = "okay";
> +};
> +
> +&uart7 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart7_pi_pins>;
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb1_vbus-supply = <®_vcc5v0>;
> + usb2_vbus-supply = <®_vcc5v0>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi
> index d5ad3b9efd..03d3e5f45a 100644
> --- a/arch/arm/dts/sun8i-r40.dtsi
> +++ b/arch/arm/dts/sun8i-r40.dtsi
> @@ -357,6 +357,8 @@
> clock-names = "ahb", "mmc";
> resets = <&ccu RST_BUS_MMC3>;
> reset-names = "ahb";
> + pinctrl-0 = <&mmc3_pins>;
> + pinctrl-names = "default";
> interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> #address-cells = <1>;
> @@ -509,6 +511,16 @@
> #interrupt-cells = <3>;
> #gpio-cells = <3>;
>
> + can_ph_pins: can-ph-pins {
> + pins = "PH20", "PH21";
> + function = "can";
> + };
> +
> + can_pa_pins: can-pa-pins {
> + pins = "PA16", "PA17";
> + function = "can";
> + };
> +
> clk_out_a_pin: clk-out-a-pin {
> pins = "PI12";
> function = "clk_out_a";
> @@ -601,6 +613,15 @@
> bias-pull-up;
> };
>
> + /omit-if-no-ref/
> + mmc3_pins: mmc3-pins {
> + pins = "PI4", "PI5", "PI6",
> + "PI7", "PI8", "PI9";
> + function = "mmc3";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> /omit-if-no-ref/
> spi0_pc_pins: spi0-pc-pins {
> pins = "PC0", "PC1", "PC2";
> @@ -631,20 +652,65 @@
> function = "spi1";
> };
>
> + /omit-if-no-ref/
> uart0_pb_pins: uart0-pb-pins {
> pins = "PB22", "PB23";
> function = "uart0";
> };
>
> + /omit-if-no-ref/
> + uart2_pi_pins: uart2-pi-pins {
> + pins = "PI18", "PI19";
> + function = "uart2";
> + };
> +
> + /omit-if-no-ref/
> + uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
> + pins = "PI16", "PI17";
> + function = "uart2";
> + };
> +
> + /omit-if-no-ref/
> uart3_pg_pins: uart3-pg-pins {
> pins = "PG6", "PG7";
> function = "uart3";
> };
>
> + /omit-if-no-ref/
> uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
> pins = "PG8", "PG9";
> function = "uart3";
> };
> +
> + /omit-if-no-ref/
> + uart4_pg_pins: uart4-pg-pins {
> + pins = "PG10", "PG11";
> + function = "uart4";
> + };
> +
> + /omit-if-no-ref/
> + uart5_ph_pins: uart5-ph-pins {
> + pins = "PH6", "PH7";
> + function = "uart5";
> + };
> +
> + /omit-if-no-ref/
> + uart7_pi_pins: uart7-pi-pins {
> + pins = "PI20", "PI21";
> + function = "uart7";
> + };
> + };
> +
> + timer@1c20c00 {
> + compatible = "allwinner,sun4i-a10-timer";
> + reg = <0x01c20c00 0x90>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> };
>
> wdt: watchdog@1c20c90 {
> @@ -680,6 +746,45 @@
> status = "disabled";
> };
>
> + i2s0: i2s@1c22000 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun8i-r40-i2s",
> + "allwinner,sun8i-h3-i2s";
> + reg = <0x01c22000 0x400>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S0>;
> + dmas = <&dma 3>, <&dma 3>;
> + dma-names = "rx", "tx";
> + };
> +
> + i2s1: i2s@1c22400 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun8i-r40-i2s",
> + "allwinner,sun8i-h3-i2s";
> + reg = <0x01c22400 0x400>;
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S1>;
> + dmas = <&dma 4>, <&dma 4>;
> + dma-names = "rx", "tx";
> + };
> +
> + i2s2: i2s@1c22800 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun8i-r40-i2s",
> + "allwinner,sun8i-h3-i2s";
> + reg = <0x01c22800 0x400>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
> + clock-names = "apb", "mod";
> + resets = <&ccu RST_BUS_I2S2>;
> + dmas = <&dma 6>, <&dma 6>;
> + dma-names = "rx", "tx";
> + };
> +
> ths: thermal-sensor@1c24c00 {
> compatible = "allwinner,sun8i-r40-ths";
> reg = <0x01c24c00 0x100>;
> @@ -831,6 +936,15 @@
> #size-cells = <0>;
> };
>
> + can0: can@1c2bc00 {
> + compatible = "allwinner,sun8i-r40-can";
> + reg = <0x01c2bc00 0x400>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CAN>;
> + resets = <&ccu RST_BUS_CAN>;
> + status = "disabled";
> + };
> +
> i2c4: i2c@1c2c000 {
> compatible = "allwinner,sun6i-a31-i2c";
> reg = <0x01c2c000 0x400>;
> @@ -1117,8 +1231,8 @@
> reg-io-width = <1>;
> interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
> - <&ccu CLK_HDMI>;
> - clock-names = "iahb", "isfr", "tmds";
> + <&ccu CLK_HDMI>, <&rtc 0>;
> + clock-names = "iahb", "isfr", "tmds", "cec";
> resets = <&ccu RST_BUS_HDMI1>;
> reset-names = "ctrl";
> phys = <&hdmi_phy>;
> diff --git a/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
> new file mode 100644
> index 0000000000..6931aaab23
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
> @@ -0,0 +1,226 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> + * Copyright (C) 2018 Hao Zhang <hao5781286@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-r40.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "t3-cqa3t-bv3";
> + compatible = "qihua,t3-cqa3t-bv3", "allwinner,sun8i-t3",
> + "allwinner,sun8i-r40";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + connector {
> + compatible = "hdmi-connector";
> + type = "a";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> + reg_vcc5v0: vcc5v0 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
> + enable-active-high;
> + };
> +};
> +
> +&ahci {
> + ahci-supply = <®_dldo4>;
> + phy-supply = <®_eldo3>;
> + status = "okay";
> +};
> +
> +&de {
> + status = "okay";
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci2 {
> + status = "okay";
> +};
> +
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + axp22x: pmic@34 {
> + compatible = "x-powers,axp221";
> + reg = <0x34>;
> + interrupt-parent = <&nmi_intc>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +#include "axp22x.dtsi"
> +
> +&mmc0 {
> + vmmc-supply = <®_dcdc1>;
> + bus-width = <4>;
> + cd-gpios = <&pio 7 15 GPIO_ACTIVE_LOW>; /* PH15 */
> + status = "okay";
> +};
> +
> +&mmc2 {
> + vmmc-supply = <®_dcdc1>;
> + vqmmc-supply = <®_dcdc1>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&ohci2 {
> + status = "okay";
> +};
> +
> +®_aldo2 {
> + regulator-always-on;
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + regulator-name = "vcc-pa";
> +};
> +
> +®_aldo3 {
> + regulator-always-on;
> + regulator-min-microvolt = <2700000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "avcc";
> +};
> +
> +®_dcdc1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-name = "vcc-3v0";
> +};
> +
> +®_dcdc2 {
> + regulator-always-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-name = "vdd-cpu";
> +};
> +
> +®_dcdc3 {
> + regulator-always-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-name = "vdd-sys";
> +};
> +
> +®_dcdc5 {
> + regulator-always-on;
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-name = "vcc-dram";
> +};
> +
> +®_dldo1 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-pg";
> +};
> +
> +®_dldo3 {
> + regulator-always-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-dldo3";
> +};
> +
> +®_eldo3 {
> + regulator-always-on;
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-name = "vcc-pe";
> +};
> +
> +&tcon_tv0 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pb_pins>;
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb1_vbus-supply = <®_vcc5v0>;
> + usb2_vbus-supply = <®_vcc5v0>;
> + status = "okay";
> +};
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/12] ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1
2022-04-27 20:31 ` [PATCH 08/12] ARM: dts: sunxi: H2+/H3/H5: " Samuel Holland
@ 2022-05-22 23:33 ` Andre Przywara
0 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-22 23:33 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:27 -0500
Samuel Holland <samuel@sholland.org> wrote:
> Copy the devicetree source for the H2+/H3/H5 SoCs and all existing
> boards from the Linux v5.18-rc1 tag.
>
> To maintain ABI compatibility with existing LTS kernels, one change
> moving some IP blocks to the r_intc interrupt controller is excluded.
> This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.
>
> This commit also adds the following new board devicetree:
> - sun8i-h3-nanopi-r1.dts
>
> This update should not impact any existing U-Boot functionality.
>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
Looks good, the files are the same as in the kernel tree, minus the
r_intc change.
There seems to be a compatible name change for the H5 for the
mbus device, but that should only affect the interlace device, and I
actually don't see a driver using the old compatible name in the tree
at all. So:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +-
> arch/arm/dts/sun50i-h5.dtsi | 6 +-
> .../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 28 ++-
> arch/arm/dts/sun8i-h3-beelink-x2.dts | 27 ++-
> arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 28 +++
> arch/arm/dts/sun8i-h3-nanopi-r1.dts | 169 ++++++++++++++++++
> arch/arm/dts/sun8i-h3-nanopi.dtsi | 1 +
> arch/arm/dts/sun8i-h3-orangepi-2.dts | 3 +-
> arch/arm/dts/sun8i-h3-orangepi-pc.dts | 3 +-
> arch/arm/dts/sun8i-h3.dtsi | 10 +-
> arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 18 +-
> arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 4 +-
> arch/arm/dts/sunxi-h3-h5.dtsi | 42 ++++-
> arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 13 ++
> arch/arm/dts/sunxi-libretech-all-h3-it.dtsi | 2 +-
> 17 files changed, 342 insertions(+), 24 deletions(-)
> create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 6433f63455..bbd69d3a67 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -655,6 +655,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
> sun8i-h3-nanopi-m1-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> sun8i-h3-nanopi-neo-air.dtb \
> + sun8i-h3-nanopi-r1.dtb \
> sun8i-h3-orangepi-2.dtb \
> sun8i-h3-orangepi-lite.dtb \
> sun8i-h3-orangepi-one.dtb \
> diff --git a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
> index b265720195..1afad8b437 100644
> --- a/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
> +++ b/arch/arm/dts/sun50i-h5-cpu-opp.dtsi
> @@ -2,7 +2,7 @@
> // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org>
>
> / {
> - cpu_opp_table: cpu-opp-table {
> + cpu_opp_table: opp-table-cpu {
> compatible = "operating-points-v2";
> opp-shared;
>
> diff --git a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
> index 55bcdf8d1a..55b369534a 100644
> --- a/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
> +++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
> @@ -142,9 +142,16 @@
> status = "okay";
>
> eeprom@51 {
> - compatible = "microchip,24c02";
> + compatible = "microchip,24c02", "atmel,24c02";
> reg = <0x51>;
> pagesize = <16>;
> + read-only;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + eth_mac1: mac-address@fa {
> + reg = <0xfa 0x06>;
> + };
> };
> };
>
> diff --git a/arch/arm/dts/sun50i-h5.dtsi b/arch/arm/dts/sun50i-h5.dtsi
> index ab860e20d0..9b3462b13c 100644
> --- a/arch/arm/dts/sun50i-h5.dtsi
> +++ b/arch/arm/dts/sun50i-h5.dtsi
> @@ -217,7 +217,7 @@
> };
> };
>
> - gpu_thermal {
> + gpu-thermal {
> polling-delay-passive = <0>;
> polling-delay = <0>;
> thermal-sensors = <&ths 1>;
> @@ -233,6 +233,10 @@
> compatible = "allwinner,sun50i-h5-de2-clk";
> };
>
> +&mbus {
> + compatible = "allwinner,sun50i-h5-mbus";
> +};
> +
> &mmc0 {
> compatible = "allwinner,sun50i-h5-mmc",
> "allwinner,sun50i-a64-mmc";
> diff --git a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> index f3f7a2c912..d5c7b7984d 100644
> --- a/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> +++ b/arch/arm/dts/sun8i-h2-plus-bananapi-m2-zero.dts
> @@ -26,6 +26,17 @@
> stdout-path = "serial0:115200n8";
> };
>
> + connector {
> + compatible = "hdmi-connector";
> + type = "c";
> +
> + port {
> + hdmi_con_in: endpoint {
> + remote-endpoint = <&hdmi_out_con>;
> + };
> + };
> + };
> +
> leds {
> compatible = "gpio-leds";
>
> @@ -41,8 +52,9 @@
>
> sw4 {
> label = "power";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
>
> @@ -103,10 +115,24 @@
> cpu-supply = <®_vdd_cpux>;
> };
>
> +&de {
> + status = "okay";
> +};
> +
> &ehci0 {
> status = "okay";
> };
>
> +&hdmi {
> + status = "okay";
> +};
> +
> +&hdmi_out {
> + hdmi_out_con: endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> +};
> +
> &mmc0 {
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> diff --git a/arch/arm/dts/sun8i-h3-beelink-x2.dts b/arch/arm/dts/sun8i-h3-beelink-x2.dts
> index 62b5280ec0..cd9f655e4f 100644
> --- a/arch/arm/dts/sun8i-h3-beelink-x2.dts
> +++ b/arch/arm/dts/sun8i-h3-beelink-x2.dts
> @@ -57,6 +57,12 @@
> ethernet1 = &sdiowifi;
> };
>
> + cec-gpio {
> + compatible = "cec-gpio";
> + cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */
> + hdmi-phandle = <&hdmi>;
> + };
> +
> chosen {
> stdout-path = "serial0:115200n8";
> };
> @@ -87,11 +93,15 @@
> };
> };
>
> - wifi_pwrseq: wifi_pwrseq {
> - compatible = "mmc-pwrseq-simple";
> - reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
> - clocks = <&rtc 1>;
> - clock-names = "ext_clock";
> + r-gpio-keys {
> + compatible = "gpio-keys";
> +
> + power {
> + label = "power";
> + linux,code = <KEY_POWER>;
> + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> + };
> };
>
> sound_spdif {
> @@ -111,6 +121,13 @@
> #sound-dai-cells = <0>;
> compatible = "linux,spdif-dit";
> };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
> + clocks = <&rtc 1>;
> + clock-names = "ext_clock";
> + };
> };
>
> &de {
> diff --git a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
> index be49eabbff..cd3df12b65 100644
> --- a/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
> +++ b/arch/arm/dts/sun8i-h3-nanopi-neo-air.dts
> @@ -103,12 +103,40 @@
> };
> };
>
> +&mmc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_8bit_pins>;
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc3v3>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pa_pins>;
> status = "okay";
> };
>
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + clocks = <&rtc 1>;
> + clock-names = "lpo";
> + vbat-supply = <®_vcc3v3>;
> + vddio-supply = <®_vcc3v3>;
> + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
> + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
> + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
> + };
> +};
> +
> &usbphy {
> /* USB VBUS is always on */
> status = "okay";
> diff --git a/arch/arm/dts/sun8i-h3-nanopi-r1.dts b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
> new file mode 100644
> index 0000000000..26e2e6172e
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
> + * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
> + * Copyright (C) 2020 Yu-Tung Chang <mtwget@gmail.com>
> +*/
> +
> +#include "sun8i-h3-nanopi.dtsi"
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> + model = "FriendlyARM NanoPi R1";
> + compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3";
> +
> + aliases {
> + serial1 = &uart1;
> + ethernet0 = &emac;
> + ethernet1 = &wifi;
> + };
> +
> + reg_gmac_3v3: gmac-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "gmac-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + startup-delay-us = <100000>;
> + enable-active-high;
> + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
> + };
> +
> + reg_vdd_cpux: gpio-regulator {
> + compatible = "regulator-gpio";
> + regulator-name = "vdd-cpux";
> + regulator-type = "voltage";
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-ramp-delay = <50>;
> + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
> + gpios-states = <0x1>;
> + states = <1100000 0x0>,
> + <1300000 0x1>;
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
> + clocks = <&rtc 1>;
> + clock-names = "ext_clock";
> + };
> +
> + leds {
> + led-2 {
> + function = LED_FUNCTION_WAN;
> + color = <LED_COLOR_ID_GREEN>;
> + gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
> + };
> +
> + led-3 {
> + function = LED_FUNCTION_LAN;
> + color = <LED_COLOR_ID_GREEN>;
> + gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; /* PA9 */
> + };
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <®_vdd_cpux>;
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci2 {
> + status = "okay";
> +};
> +
> +&emac {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emac_rgmii_pins>;
> + phy-supply = <®_gmac_3v3>;
> + phy-handle = <&ext_rgmii_phy>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +};
> +
> +&external_mdio {
> + ext_rgmii_phy: ethernet-phy@7 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <7>;
> + };
> +};
> +
> +&mmc1 {
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc3v3>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +
> + wifi: wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + interrupt-parent = <&pio>;
> + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
> + interrupt-names = "host-wake";
> + };
> +};
> +
> +&mmc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_8bit_pins>;
> + vmmc-supply = <®_vcc3v3>;
> + vqmmc-supply = <®_vcc3v3>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&ohci2 {
> + status = "okay";
> +};
> +
> +®_usb0_vbus {
> + gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "brcm,bcm43438-bt";
> + clocks = <&rtc 1>;
> + clock-names = "lpo";
> + vbat-supply = <®_vcc3v3>;
> + vddio-supply = <®_vcc3v3>;
> + device-wakeup-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */
> + host-wakeup-gpios = <&pio 0 7 GPIO_ACTIVE_HIGH>; /* PA7 */
> + shutdown-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
> + };
> +};
> +
> +&usb_otg {
> + status = "okay";
> + dr_mode = "otg";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
> + usb0_vbus-supply = <®_usb0_vbus>;
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/sun8i-h3-nanopi.dtsi b/arch/arm/dts/sun8i-h3-nanopi.dtsi
> index c7c3e7d8b3..fc45d5aaa6 100644
> --- a/arch/arm/dts/sun8i-h3-nanopi.dtsi
> +++ b/arch/arm/dts/sun8i-h3-nanopi.dtsi
> @@ -81,6 +81,7 @@
> label = "k1";
> linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
> };
> diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts
> index 597c425d08..9daffd90c1 100644
> --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts
> +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts
> @@ -99,8 +99,9 @@
>
> sw4 {
> label = "sw4";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
>
> diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
> index 5aff8ecc66..90f75fa85e 100644
> --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts
> +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts
> @@ -91,8 +91,9 @@
>
> sw4 {
> label = "sw4";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
> };
> diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
> index 4e89701df9..eac2349a23 100644
> --- a/arch/arm/dts/sun8i-h3.dtsi
> +++ b/arch/arm/dts/sun8i-h3.dtsi
> @@ -44,7 +44,7 @@
> #include <dt-bindings/thermal/thermal.h>
>
> / {
> - cpu0_opp_table: opp_table0 {
> + cpu0_opp_table: opp-table-cpu {
> compatible = "operating-points-v2";
> opp-shared;
>
> @@ -112,7 +112,7 @@
> };
> };
>
> - gpu_opp_table: gpu-opp-table {
> + gpu_opp_table: opp-table-gpu {
> compatible = "operating-points-v2";
>
> opp-120000000 {
> @@ -245,7 +245,7 @@
> cpu_thermal: cpu-thermal {
> polling-delay-passive = <0>;
> polling-delay = <0>;
> - thermal-sensors = <&ths 0>;
> + thermal-sensors = <&ths>;
>
> trips {
> cpu_hot_trip: cpu-hot {
> @@ -282,6 +282,10 @@
> compatible = "allwinner,sun8i-h3-de2-clk";
> };
>
> +&mbus {
> + compatible = "allwinner,sun8i-h3-mbus";
> +};
> +
> &mmc0 {
> compatible = "allwinner,sun7i-a20-mmc";
> clocks = <&ccu CLK_BUS_MMC0>,
> diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
> index 22466afd38..235994a4a2 100644
> --- a/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
> +++ b/arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi
> @@ -16,15 +16,27 @@
> regulator-type = "voltage";
> regulator-boot-on;
> regulator-always-on;
> - regulator-min-microvolt = <1100000>;
> - regulator-max-microvolt = <1300000>;
> + regulator-min-microvolt = <1108475>;
> + regulator-max-microvolt = <1308475>;
> regulator-ramp-delay = <50>; /* 4ms */
> gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
> gpios-states = <0x1>;
> - states = <1100000 0>, <1300000 1>;
> + states = <1108475 0>, <1308475 1>;
> };
> };
>
> &cpu0 {
> cpu-supply = <®_vdd_cpux>;
> };
> +
> +&cpu1 {
> + cpu-supply = <®_vdd_cpux>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <®_vdd_cpux>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <®_vdd_cpux>;
> +};
> diff --git a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
> index 8e5cb3b3fd..d03f5853ef 100644
> --- a/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
> +++ b/arch/arm/dts/sunxi-bananapi-m2-plus.dtsi
> @@ -82,8 +82,9 @@
>
> sw4 {
> label = "power";
> - linux,code = <BTN_0>;
> + linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + wakeup-source;
> };
> };
>
> @@ -219,6 +220,7 @@
>
> bluetooth {
> compatible = "brcm,bcm43438-bt";
> + max-speed = <1500000>;
> clocks = <&rtc 1>;
> clock-names = "lpo";
> vbat-supply = <®_vcc3v3>;
> diff --git a/arch/arm/dts/sunxi-h3-h5.dtsi b/arch/arm/dts/sunxi-h3-h5.dtsi
> index 9be13378d4..6cea57e07f 100644
> --- a/arch/arm/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/dts/sunxi-h3-h5.dtsi
> @@ -567,9 +567,14 @@
> };
>
> mbus: dram-controller@1c62000 {
> - compatible = "allwinner,sun8i-h3-mbus";
> - reg = <0x01c62000 0x1000>;
> - clocks = <&ccu CLK_MBUS>;
> + /* compatible is in per SoC .dtsi file */
> + reg = <0x01c62000 0x1000>,
> + <0x01c63000 0x1000>;
> + reg-names = "mbus", "dram";
> + clocks = <&ccu CLK_MBUS>,
> + <&ccu CLK_DRAM>,
> + <&ccu CLK_BUS_DRAM>;
> + clock-names = "mbus", "dram", "bus";
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x00000000 0x40000000 0xc0000000>;
> @@ -812,8 +817,8 @@
> reg-io-width = <1>;
> interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
> - <&ccu CLK_HDMI>;
> - clock-names = "iahb", "isfr", "tmds";
> + <&ccu CLK_HDMI>, <&rtc 0>;
> + clock-names = "iahb", "isfr", "tmds", "cec";
> resets = <&ccu RST_BUS_HDMI1>;
> reset-names = "ctrl";
> phys = <&hdmi_phy>;
> @@ -859,6 +864,15 @@
> #clock-cells = <1>;
> };
>
> + r_intc: interrupt-controller@1f00c00 {
> + compatible = "allwinner,sun8i-h3-r-intc",
> + "allwinner,sun6i-a31-r-intc";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x01f00c00 0x400>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> r_ccu: clock@1f01400 {
> compatible = "allwinner,sun8i-h3-r-ccu";
> reg = <0x01f01400 0x100>;
> @@ -897,6 +911,19 @@
> #size-cells = <0>;
> };
>
> + r_uart: serial@1f02800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x01f02800 0x400>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&r_ccu CLK_APB0_UART>;
> + resets = <&r_ccu RST_APB0_UART>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&r_uart_pins>;
> + status = "disabled";
> + };
> +
> r_pio: pinctrl@1f02c00 {
> compatible = "allwinner,sun8i-h3-r-pinctrl";
> reg = <0x01f02c00 0x400>;
> @@ -922,6 +949,11 @@
> pins = "PL10";
> function = "s_pwm";
> };
> +
> + r_uart_pins: r-uart-pins {
> + pins = "PL2", "PL3";
> + function = "s_uart";
> + };
> };
>
> r_pwm: pwm@1f03800 {
> diff --git a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
> index 19b3b23cfa..9e14fe5fdc 100644
> --- a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
> +++ b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
> @@ -49,6 +49,7 @@
> label = "power";
> linux,code = <KEY_POWER>;
> gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
> + wakeup-source;
> };
> };
>
> @@ -128,6 +129,18 @@
> cpu-supply = <®_vdd_cpux>;
> };
>
> +&cpu1 {
> + cpu-supply = <®_vdd_cpux>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <®_vdd_cpux>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <®_vdd_cpux>;
> +};
> +
> &de {
> status = "okay";
> };
> diff --git a/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
> index 204fba3614..50d328c2a8 100644
> --- a/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
> +++ b/arch/arm/dts/sunxi-libretech-all-h3-it.dtsi
> @@ -156,7 +156,7 @@
> &spi0 {
> status = "okay";
>
> - spiflash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <50000000>;
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
` (12 preceding siblings ...)
2022-04-29 14:51 ` [PATCH 00/12] sunxi: Devicetree sync " Andre Przywara
@ 2022-05-24 15:58 ` Andre Przywara
13 siblings, 0 replies; 41+ messages in thread
From: Andre Przywara @ 2022-05-24 15:58 UTC (permalink / raw)
To: Samuel Holland; +Cc: u-boot, Jagan Teki, Tom Rini
On Wed, 27 Apr 2022 15:31:19 -0500
Samuel Holland <samuel@sholland.org> wrote:
> This series brings all of our devicetrees up to date with Linux.
>
> Older SoCs (before A83T) have not been synchronized in over 3 years.
> And I don't have any of this hardware to test. But there are not major
> changes to those devicetrees either.
>
> The big motivation for including older SoCs in this update is converting
> the USB PHY driver to get its VBUS detection GPIO/regulator from the
> devicetree instead of from a pin name in Kconfig. Many older boards had
> those properties added or fixed since the last devicetree sync. This PHY
> driver change is necessary to complete the DM_GPIO migration.
>
> A couple of breaking changes were made to several SoCs' devicetrees in
> Linux relating to the "r_intc" interrupt controller. New kernels support
> old devicetrees, but not the other way around. So to be most compatible
> and avoid regressions, those changes are skipped here.
Applied the whole series to sunxi/master, including the Mele M5 fix.
Thanks!
Andre
>
>
> Samuel Holland (12):
> dt-bindings: sunxi: Update clock/reset binding headers
> ARM: dts: sunxi: Remove unused devicetree headers
> ARM: dts: sun4i: Sync from Linux v5.18-rc1
> ARM: dts: sun7i: Sync from Linux v5.18-rc1
> ARM: dts: sunxi: A13/A31/A23/A33: Sync from Linux v5.18-rc1
> ARM: dts: sun9i: Sync from Linux v5.18-rc1
> ARM: dts: sun8i: A83T: Sync from Linux v5.18-rc1
> ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1
> ARM: dts: sun8i: V3/V3s/S3: Sync from Linux v5.18-rc1
> ARM: dts: sun8i: R40/T3: Sync from Linux v5.18-rc1
> ARM: dts: sun50i: A64: Sync from Linux v5.18-rc1
> ARM: dts: sun50i: H6: Sync from Linux v5.18-rc1
>
> arch/arm/dts/Makefile | 25 +-
> arch/arm/dts/axp209.dtsi | 6 +-
> arch/arm/dts/axp22x.dtsi | 11 +-
> arch/arm/dts/axp803.dtsi | 10 +-
> arch/arm/dts/axp81x.dtsi | 15 +-
> arch/arm/dts/sun4i-a10-a1000.dts | 31 +-
> arch/arm/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
> arch/arm/dts/sun4i-a10-chuwi-v7-cw0825.dts | 20 +-
> arch/arm/dts/sun4i-a10-cubieboard.dts | 16 +-
> arch/arm/dts/sun4i-a10-dserve-dsrv9703c.dts | 21 +-
> arch/arm/dts/sun4i-a10-hackberry.dts | 2 +-
> arch/arm/dts/sun4i-a10-hyundai-a7hd.dts | 20 +-
> arch/arm/dts/sun4i-a10-inet1.dts | 21 +-
> arch/arm/dts/sun4i-a10-inet97fv2.dts | 22 +-
> arch/arm/dts/sun4i-a10-inet9f-rev03.dts | 74 ++--
> .../dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +-
> arch/arm/dts/sun4i-a10-jesurun-q5.dts | 4 +-
> arch/arm/dts/sun4i-a10-marsboard.dts | 22 +-
> arch/arm/dts/sun4i-a10-olinuxino-lime.dts | 33 +-
> arch/arm/dts/sun4i-a10-pcduino.dts | 20 +-
> arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts | 21 +-
> arch/arm/dts/sun4i-a10-topwise-a721.dts | 242 +++++++++++++
> arch/arm/dts/sun4i-a10.dtsi | 135 ++++++-
> arch/arm/dts/sun50i-a64-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-a64-orangepi-win.dts | 2 +-
> arch/arm/dts/sun50i-a64-pinebook.dts | 1 +
> arch/arm/dts/sun50i-a64-pinephone.dtsi | 27 ++
> arch/arm/dts/sun50i-a64-pinetab.dts | 29 +-
> arch/arm/dts/sun50i-a64-teres-i.dts | 4 +-
> arch/arm/dts/sun50i-a64.dtsi | 93 +++--
> arch/arm/dts/sun50i-h5-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 9 +-
> arch/arm/dts/sun50i-h5.dtsi | 6 +-
> arch/arm/dts/sun50i-h6-beelink-gs1.dts | 38 +-
> arch/arm/dts/sun50i-h6-cpu-opp.dtsi | 2 +-
> arch/arm/dts/sun50i-h6-orangepi-3.dts | 14 +-
> arch/arm/dts/sun50i-h6-orangepi.dtsi | 22 +-
> arch/arm/dts/sun50i-h6-pine-h64-model-b.dts | 51 +++
> arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts | 15 +
> arch/arm/dts/sun50i-h6-tanix-tx6.dts | 115 +-----
> arch/arm/dts/sun50i-h6-tanix.dtsi | 189 ++++++++++
> arch/arm/dts/sun50i-h6.dtsi | 26 +-
> arch/arm/dts/sun5i-a10s-auxtek-t003.dts | 16 +-
> arch/arm/dts/sun5i-a10s-auxtek-t004.dts | 35 +-
> arch/arm/dts/sun5i-a10s-mk802.dts | 31 +-
> arch/arm/dts/sun5i-a10s-olinuxino-micro.dts | 68 +---
> arch/arm/dts/sun5i-a10s-r7-tv-dongle.dts | 22 +-
> arch/arm/dts/sun5i-a10s-wobo-i5.dts | 34 +-
> arch/arm/dts/sun5i-a10s.dtsi | 30 +-
> arch/arm/dts/sun5i-a13-ampe-a76.dts | 2 +-
> .../dts/sun5i-a13-empire-electronix-d709.dts | 41 +--
> arch/arm/dts/sun5i-a13-hsg-h702.dts | 37 +-
> arch/arm/dts/sun5i-a13-inet-86vs.dts | 2 +-
> ...common.dtsi => sun5i-a13-licheepi-one.dts} | 146 +++++---
> arch/arm/dts/sun5i-a13-olinuxino-micro.dts | 50 +--
> arch/arm/dts/sun5i-a13-olinuxino.dts | 56 +--
> .../dts/sun5i-a13-pocketbook-touch-lux-3.dts | 258 ++++++++++++++
> arch/arm/dts/sun5i-a13-q8-tablet.dts | 18 +-
> arch/arm/dts/sun5i-a13-utoo-p66.dts | 26 +-
> arch/arm/dts/sun5i-a13.dtsi | 23 +-
> arch/arm/dts/sun5i-gr8-chip-pro.dts | 38 +-
> arch/arm/dts/sun5i-gr8-evb.dts | 333 ++++++++++++++++++
> arch/arm/dts/sun5i-gr8.dtsi | 12 +-
> arch/arm/dts/sun5i-r8-chip.dts | 52 +--
> .../dts/sun5i-reference-design-tablet.dtsi | 57 +--
> arch/arm/dts/sun5i.dtsi | 209 +++++++----
> arch/arm/dts/sun6i-a31-app4-evb1.dts | 10 +-
> arch/arm/dts/sun6i-a31-colombus.dts | 57 +--
> arch/arm/dts/sun6i-a31-hummingbird.dts | 75 +---
> arch/arm/dts/sun6i-a31-i7.dts | 47 +--
> arch/arm/dts/sun6i-a31-m9.dts | 46 +--
> arch/arm/dts/sun6i-a31-mele-a1000g-quad.dts | 46 +--
> arch/arm/dts/sun6i-a31-mixtile-loftq.dts | 6 +-
> arch/arm/dts/sun6i-a31.dtsi | 218 +++++++-----
> arch/arm/dts/sun6i-a31s-colorfly-e708-q1.dts | 2 +-
> arch/arm/dts/sun6i-a31s-cs908.dts | 17 +-
> arch/arm/dts/sun6i-a31s-inet-q972.dts | 8 +-
> arch/arm/dts/sun6i-a31s-primo81.dts | 32 +-
> arch/arm/dts/sun6i-a31s-sina31s-core.dtsi | 4 +-
> arch/arm/dts/sun6i-a31s-sina31s.dts | 39 +-
> arch/arm/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 144 +++++---
> .../sun6i-a31s-yones-toptech-bs1078-v2.dts | 22 +-
> .../dts/sun6i-reference-design-tablet.dtsi | 22 +-
> arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 16 +-
> arch/arm/dts/sun7i-a20-bananapi.dts | 41 +--
> arch/arm/dts/sun7i-a20-bananapro.dts | 16 +-
> arch/arm/dts/sun7i-a20-cubieboard2.dts | 28 +-
> arch/arm/dts/sun7i-a20-cubietruck.dts | 20 +-
> arch/arm/dts/sun7i-a20-haoyu-marsboard.dts | 182 ++++++++++
> arch/arm/dts/sun7i-a20-hummingbird.dts | 21 +-
> arch/arm/dts/sun7i-a20-i12-tvbox.dts | 16 +-
> arch/arm/dts/sun7i-a20-icnova-swac.dts | 15 +-
> arch/arm/dts/sun7i-a20-itead-ibox.dts | 8 +-
> arch/arm/dts/sun7i-a20-lamobo-r1.dts | 16 +-
> .../dts/sun7i-a20-linutronix-testbox-v2.dts | 47 +++
> arch/arm/dts/sun7i-a20-m3.dts | 14 +-
> arch/arm/dts/sun7i-a20-olimex-som-evb.dts | 14 +-
> arch/arm/dts/sun7i-a20-olimex-som204-evb.dts | 30 +-
> .../arm/dts/sun7i-a20-olinuxino-lime-emmc.dts | 32 ++
> arch/arm/dts/sun7i-a20-olinuxino-lime.dts | 32 +-
> arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 46 +--
> arch/arm/dts/sun7i-a20-olinuxino-micro.dts | 32 +-
> arch/arm/dts/sun7i-a20-orangepi-mini.dts | 28 +-
> arch/arm/dts/sun7i-a20-orangepi.dts | 26 +-
> arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 32 +-
> arch/arm/dts/sun7i-a20-pcduino3.dts | 28 +-
> arch/arm/dts/sun7i-a20-wexler-tab7200.dts | 13 +-
> arch/arm/dts/sun7i-a20-wits-pro-a20-dkt.dts | 24 +-
> arch/arm/dts/sun7i-a20.dtsi | 254 +++++++++++--
> arch/arm/dts/sun8i-a23-a33.dtsi | 308 ++++++++++++----
> arch/arm/dts/sun8i-a23-evb.dts | 20 +-
> arch/arm/dts/sun8i-a23-gt90h-v4.dts | 2 +-
> ...ommon.dtsi => sun8i-a23-ippo-q8h-v1.2.dts} | 54 ++-
> arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts | 73 ++++
> .../dts/sun8i-a23-polaroid-mid2407pxe03.dts | 15 +-
> .../dts/sun8i-a23-polaroid-mid2809pxe04.dts | 15 +-
> arch/arm/dts/sun8i-a23-q8-tablet.dts | 10 +
> arch/arm/dts/sun8i-a23.dtsi | 26 +-
> ...c-edition.dts => sun8i-a33-et-q8-v1.6.dts} | 32 +-
> arch/arm/dts/sun8i-a33-ga10h-v1.1.dts | 4 +-
> arch/arm/dts/sun8i-a33-inet-d978-rev2.dts | 14 +-
> arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts | 57 +++
> arch/arm/dts/sun8i-a33-olinuxino.dts | 12 +-
> arch/arm/dts/sun8i-a33-q8-tablet.dts | 7 +
> arch/arm/dts/sun8i-a33-sinlinx-sina33.dts | 34 +-
> arch/arm/dts/sun8i-a33.dtsi | 270 +++++---------
> .../dts/sun8i-a83t-allwinner-h8homlet-v2.dts | 12 +
> arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 55 ++-
> arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 77 +++-
> arch/arm/dts/sun8i-a83t-tbs-a711.dts | 101 +++++-
> arch/arm/dts/sun8i-a83t.dtsi | 311 ++++++++++++++--
> .../dts/sun8i-h2-plus-bananapi-m2-zero.dts | 28 +-
> arch/arm/dts/sun8i-h3-beelink-x2.dts | 27 +-
> arch/arm/dts/sun8i-h3-nanopi-neo-air.dts | 28 ++
> arch/arm/dts/sun8i-h3-nanopi-r1.dts | 169 +++++++++
> arch/arm/dts/sun8i-h3-nanopi.dtsi | 1 +
> arch/arm/dts/sun8i-h3-orangepi-2.dts | 3 +-
> arch/arm/dts/sun8i-h3-orangepi-pc.dts | 3 +-
> arch/arm/dts/sun8i-h3.dtsi | 10 +-
> arch/arm/dts/sun8i-q8-common.dtsi | 31 +-
> arch/arm/dts/sun8i-r16-bananapi-m2m.dts | 55 ++-
> .../dts/sun8i-r16-nintendo-nes-classic.dts | 54 +++
> .../sun8i-r16-nintendo-super-nes-classic.dts | 11 +
> arch/arm/dts/sun8i-r16-parrot.dts | 62 +---
> arch/arm/dts/sun8i-r40-feta40i.dtsi | 106 ++++++
> arch/arm/dts/sun8i-r40-oka40i-c.dts | 203 +++++++++++
> arch/arm/dts/sun8i-r40.dtsi | 118 ++++++-
> .../dts/sun8i-reference-design-tablet.dtsi | 33 +-
> arch/arm/dts/sun8i-s3-elimo-impetus.dtsi | 44 +++
> arch/arm/dts/sun8i-s3-elimo-initium.dts | 29 ++
> arch/arm/dts/sun8i-s3-pinecube.dts | 13 +-
> arch/arm/dts/sun8i-t3-cqa3t-bv3.dts | 226 ++++++++++++
> arch/arm/dts/sun8i-v3-sl631-imx179.dts | 12 +
> arch/arm/dts/sun8i-v3-sl631.dtsi | 138 ++++++++
> arch/arm/dts/sun8i-v3.dtsi | 36 ++
> arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 17 +-
> arch/arm/dts/sun8i-v3s.dtsi | 93 ++++-
> arch/arm/dts/sun9i-a80-cubieboard4.dts | 67 +++-
> arch/arm/dts/sun9i-a80-optimus.dts | 50 ++-
> arch/arm/dts/sun9i-a80.dtsi | 195 ++++++----
> arch/arm/dts/sunxi-bananapi-m2-plus-v1.2.dtsi | 18 +-
> arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 4 +-
> arch/arm/dts/sunxi-common-regulators.dtsi | 39 --
> arch/arm/dts/sunxi-h3-h5.dtsi | 42 ++-
> arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi | 13 +
> arch/arm/dts/sunxi-libretech-all-h3-it.dtsi | 2 +-
> .../dts/sunxi-reference-design-tablet.dtsi | 11 +-
> arch/arm/mach-sunxi/Kconfig | 2 +-
> .../Nintendo_NES_Classic_Edition_defconfig | 2 +-
> include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +-
> include/dt-bindings/clock/sun5i-ccu.h | 13 +-
> include/dt-bindings/clock/sun6i-a31-ccu.h | 2 +
> include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 2 +
> include/dt-bindings/clock/sun8i-h3-ccu.h | 2 +-
> include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
> include/dt-bindings/reset/sun5i-ccu.h | 11 +-
> include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
> 177 files changed, 5704 insertions(+), 2683 deletions(-)
> create mode 100644 arch/arm/dts/sun4i-a10-topwise-a721.dts
> create mode 100644 arch/arm/dts/sun50i-h6-pine-h64-model-b.dts
> create mode 100644 arch/arm/dts/sun50i-h6-tanix-tx6-mini.dts
> create mode 100644 arch/arm/dts/sun50i-h6-tanix.dtsi
> rename arch/arm/dts/{sun5i-q8-common.dtsi => sun5i-a13-licheepi-one.dts} (62%)
> create mode 100644 arch/arm/dts/sun5i-a13-pocketbook-touch-lux-3.dts
> create mode 100644 arch/arm/dts/sun5i-gr8-evb.dts
> create mode 100644 arch/arm/dts/sun7i-a20-haoyu-marsboard.dts
> create mode 100644 arch/arm/dts/sun7i-a20-linutronix-testbox-v2.dts
> create mode 100644 arch/arm/dts/sun7i-a20-olinuxino-lime-emmc.dts
> rename arch/arm/dts/{sunxi-q8-common.dtsi => sun8i-a23-ippo-q8h-v1.2.dts} (75%)
> create mode 100644 arch/arm/dts/sun8i-a23-ippo-q8h-v5.dts
> rename arch/arm/dts/{sun8i-r16-nintendo-nes-classic-edition.dts => sun8i-a33-et-q8-v1.6.dts} (81%)
> create mode 100644 arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts
> create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
> create mode 100644 arch/arm/dts/sun8i-r16-nintendo-nes-classic.dts
> create mode 100644 arch/arm/dts/sun8i-r16-nintendo-super-nes-classic.dts
> create mode 100644 arch/arm/dts/sun8i-r40-feta40i.dtsi
> create mode 100644 arch/arm/dts/sun8i-r40-oka40i-c.dts
> create mode 100644 arch/arm/dts/sun8i-s3-elimo-impetus.dtsi
> create mode 100644 arch/arm/dts/sun8i-s3-elimo-initium.dts
> create mode 100644 arch/arm/dts/sun8i-t3-cqa3t-bv3.dts
> create mode 100644 arch/arm/dts/sun8i-v3-sl631-imx179.dts
> create mode 100644 arch/arm/dts/sun8i-v3-sl631.dtsi
>
^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2022-05-24 16:18 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-27 20:31 [PATCH 00/12] sunxi: Devicetree sync from Linux v5.18-rc1 Samuel Holland
2022-04-27 20:31 ` [PATCH 01/12] dt-bindings: sunxi: Update clock/reset binding headers Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 02/12] ARM: dts: sunxi: Remove unused devicetree headers Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 03/12] ARM: dts: sun4i: Sync from Linux v5.18-rc1 Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 04/12] ARM: dts: sun7i: " Samuel Holland
2022-05-06 0:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 05/12] ARM: dts: sunxi: A13/A31/A23/A33: " Samuel Holland
2022-05-20 15:34 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 06/12] ARM: dts: sun9i: " Samuel Holland
2022-05-20 13:39 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 07/12] ARM: dts: sun8i: A83T: " Samuel Holland
2022-05-20 13:48 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 08/12] ARM: dts: sunxi: H2+/H3/H5: " Samuel Holland
2022-05-22 23:33 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 09/12] ARM: dts: sun8i: V3/V3s/S3: " Samuel Holland
2022-05-22 22:22 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 10/12] ARM: dts: sun8i: R40/T3: " Samuel Holland
2022-05-22 22:38 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 11/12] ARM: dts: sun50i: A64: " Samuel Holland
2022-05-20 14:01 ` Andre Przywara
2022-04-27 20:31 ` [PATCH 12/12] ARM: dts: sun50i: H6: " Samuel Holland
2022-05-20 14:14 ` Andre Przywara
2022-04-29 14:51 ` [PATCH 00/12] sunxi: Devicetree sync " Andre Przywara
2022-04-29 14:57 ` Tom Rini
2022-04-29 15:25 ` Andre Przywara
2022-04-29 15:31 ` Tom Rini
2022-04-29 15:57 ` Andre Przywara
2022-04-29 16:05 ` Mark Kettenis
2022-04-29 18:14 ` Tom Rini
2022-04-29 18:21 ` Mark Kettenis
2022-04-30 0:08 ` Andre Przywara
2022-04-30 2:38 ` Samuel Holland
2022-05-01 0:59 ` Andre Przywara
2022-05-01 11:01 ` Mark Kettenis
2022-05-03 1:57 ` Samuel Holland
2022-05-03 14:53 ` Andre Przywara
2022-05-01 16:25 ` Tom Rini
2022-05-24 15:58 ` Andre Przywara
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.