From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Jingoo Han <jingoohan1@gmail.com>,
Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Stanimir Varbanov <svarbanov@mm-sol.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, Johan Hovold <johan@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH v11 5/7] dt-bindings: PCI: qcom: Support additional MSI interrupts
Date: Fri, 20 May 2022 21:31:12 +0300 [thread overview]
Message-ID: <20220520183114.1356599-6-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220520183114.1356599-1-dmitry.baryshkov@linaro.org>
On Qualcomm platforms each group of 32 MSI vectors is routed to the
separate GIC interrupt. Document mapping of additional interrupts.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++++++++++++++++--
1 file changed, 50 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 0b69b12b849e..fe8f9a62a665 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -43,11 +43,12 @@ properties:
maxItems: 5
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 8
interrupt-names:
- items:
- - const: msi
+ minItems: 1
+ maxItems: 8
# Common definitions for clocks, clock-names and reset.
# Platform constraints are described later.
@@ -623,6 +624,52 @@ allOf:
- resets
- reset-names
+ # On newer chipsets support either 1 or 8 msi interrupts
+ # On older chipsets it's always 1 msi interrupt
+ - if:
+ properties:
+ compatibles:
+ contains:
+ enum:
+ - qcom,pcie-msm8996
+ - qcom,pcie-sc7280
+ - qcom,pcie-sc8180x
+ - qcom,pcie-sdm845
+ - qcom,pcie-sm8150
+ - qcom,pcie-sm8250
+ - qcom,pcie-sm8450-pcie0
+ - qcom,pcie-sm8450-pcie1
+ then:
+ oneOf:
+ - properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ maxItems: 1
+ items:
+ - const: msi
+ - properties:
+ interrupts:
+ minItems: 8
+ interrupt-names:
+ minItems: 8
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+ - const: msi4
+ - const: msi5
+ - const: msi6
+ - const: msi7
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: msi
+
unevaluatedProperties: false
examples:
--
2.35.1
next prev parent reply other threads:[~2022-05-20 18:32 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-20 18:31 [PATCH v11 0/7] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 1/7] PCI: dwc: Convert msi_irq to the array Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 2/7] PCI: dwc: split MSI IRQ parsing/allocation to a separate function Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 3/7] PCI: dwc: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-23 7:53 ` Johan Hovold
2022-05-23 13:39 ` Dmitry Baryshkov
2022-05-23 14:02 ` Johan Hovold
2022-05-23 15:17 ` Dmitry Baryshkov
2022-05-23 15:32 ` Johan Hovold
2022-05-23 15:36 ` Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 4/7] PCI: dwc: Implement special ISR handler for split MSI IRQ setup Dmitry Baryshkov
2022-05-20 18:31 ` Dmitry Baryshkov [this message]
2022-05-20 18:31 ` [PATCH v11 6/7] arm64: dts: qcom: sm8250: provide additional MSI interrupts Dmitry Baryshkov
2022-05-20 18:31 ` [PATCH v11 7/7] dt-bindings: mfd: qcom,qca639x: add binding for QCA639x defvice Dmitry Baryshkov
2022-05-23 7:42 ` [PATCH v11 0/7] PCI: qcom: Fix higher MSI vectors handling Johan Hovold
2022-05-23 13:03 ` Dmitry Baryshkov
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