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From: Andrei Lalaev <andrey.lalaev@gmail.com>
To: andre.przywara@arm.com
Cc: wens@csie.org, jernej.skrabec@gmail.com, samuel@sholland.org,
	krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
	devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev,
	Andrei Lalaev <andrey.lalaev@gmail.com>
Subject: arm: dts: sunxi: h3/h5: add gpio-ranges for pio and r_pio
Date: Mon, 23 May 2022 08:55:18 +0300	[thread overview]
Message-ID: <20220523055516.270056-1-andrey.lalaev@gmail.com> (raw)
In-Reply-To: <20220522222630.7faab948@slackpad.lan>

On Sun, 22 May 2022 22:26:30 +0100
Andre Przywara <andre.przywara@arm.com> wrote:

> But this is somewhat redundant information, because the pinctrl driver
> knows about those values, as they are derived from the big struct
> sunxi_desc_pin definition.
> So wouldn't it be smarter to put a call to
> gpiochip_add_pingroup_range() somewhere into the sunxi pinctrl driver,
> so that it would automatically work for all SoCs?

Sorry, I forgot about the other SoCs. I completely agree with you now.
I will try to fix it in another way.

Thank you, Andre!

Best regards,
Andrei Lalaev

  reply	other threads:[~2022-05-23  5:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-22 17:20 [PATCH] arm: dts: sunxi: h3/h5: add gpio-ranges for pio and r_pio Andrei Lalaev
2022-05-22 21:26 ` Andre Przywara
2022-05-23  5:55   ` Andrei Lalaev [this message]
2022-05-23 19:19   ` Andrei Lalaev
2022-07-05  4:28     ` Samuel Holland

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