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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 03/18] target/arm: Move and expand parameters to exception_target_el Date: Mon, 23 May 2022 13:47:27 -0700 Message-Id: <20220523204742.740932-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Move exception_target_el out of line. Add cur_el parameter, because 2 of 3 users already have that handy. Add psyn parameter in preparation for more code movement. Signed-off-by: Richard Henderson --- target/arm/internals.h | 15 +-------------- target/arm/op_helper.c | 17 ++++++++++++++++- target/arm/tlb_helper.c | 10 ++++++---- 3 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 03363b0f32..a71f795628 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1091,20 +1091,7 @@ typedef struct ARMVAParameters { ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -static inline int exception_target_el(CPUARMState *env) -{ - int target_el = MAX(1, arm_current_el(env)); - - /* - * No such thing as secure EL1 if EL3 is aarch32, - * so update the target EL to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { - target_el = 3; - } - - return target_el; -} +int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn); /* Determine if allocation tags are available. */ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 61e9c1d903..6858b8980d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,6 +28,21 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) +int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn) +{ + int target_el = MAX(1, cur_el); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t cur_or_target_el) { @@ -35,7 +50,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, int target_el = cur_or_target_el; if (cur_or_target_el == 0) { - target_el = exception_target_el(env); + target_el = exception_target_el(env, 0, &syndrome); } if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 6421e16202..573e18f830 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -85,11 +85,13 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env = &cpu->env; - int target_el; + int cur_el, target_el; bool same_el; uint32_t syn, exc, fsr, fsc; - target_el = exception_target_el(env); + cur_el = arm_current_el(env); + target_el = exception_target_el(env, cur_el, NULL); + if (fi->stage2) { target_el = 2; env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; @@ -97,7 +99,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |= HPFAR_NS; } } - same_el = (arm_current_el(env) == target_el); + same_el = cur_el == target_el; fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); @@ -139,7 +141,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; - int target_el = exception_target_el(env); + int target_el = exception_target_el(env, arm_current_el(env), NULL); int mmu_idx = cpu_mmu_index(env, true); uint32_t fsc; -- 2.34.1