From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D01CC433F5 for ; Mon, 23 May 2022 23:52:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231788AbiEWXw0 (ORCPT ); Mon, 23 May 2022 19:52:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231280AbiEWXvl (ORCPT ); Mon, 23 May 2022 19:51:41 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 157B253E30 for ; Mon, 23 May 2022 16:51:38 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id z7-20020a17090abd8700b001df78c7c209so615006pjr.1 for ; Mon, 23 May 2022 16:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QrWe5759iqT5XJ9qcHhhRz37JDXHYzjny//8lkVNxNY=; b=NwG6rmS9mXewedNF3JdT0ovZJIg3GZydhIjdJjKPnddDhiHp9+ziPMHdB8O3mpfZ3b SXJpf6ygX9OrQxCfxCug4FTuhx2dQkcdGt4Ji9M2ecgYnaQJ8LJN39hS12XRlQohxU6b pjIFssGpmR1oSR6dj3ylHSMUHMc+QlTqqYrwfaEW2LwtOsWbLg3tVlJNSJPZhYQeiN+j 622zL59wIn29XN8avVfv5jSWnGNKdq3MvewVPMHT3WfqH5U/83PDcrPdZAUDAdmuUynC ORTP2L7VpG1RrH9EWVR0KJF1lsOU2vDYw6fXDtkJH+EForuDJJEKiRHsvaDsebU5dfdH 5CYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QrWe5759iqT5XJ9qcHhhRz37JDXHYzjny//8lkVNxNY=; b=I0IvPXAsiK9akGc+I9ov8YBMjBav4dSO/S5Nmr6ks7MwENI4mPdbEtlmx2fIlsZpQc 0PAUH7FuX1zj0sl3J/rryEYzwB0KlnBQRPbPUWDmxG0tc1wV4ES/jd/Q/CJex21ZAF+F uwJTcEMmhaa2p9bvDO+6ArUF1NRlgKV8VSz5eEWd9ENCw2aeN3CymC7chEUATkkylpna fw37WFuj/hPFY2l+vaYTm5OgZkK0XB8tgt3ZyjQLQoHp0zzVOg/DifXAr/WOyLWn1qTY jtpwrR7HtykHr9DiGctJnFKWiDRjdvbZfV1qEBX1fSdmhjwp55d3M2g+r3xGdfXzzJFr uH7g== X-Gm-Message-State: AOAM530vR0+z4buTLG2KOde4omfbhcK6ItwH4Nrovrd9wyMMNvJF1vem iQdfyB6/YyIxh0aGAuLIHUssSSgM8wF3EQ== X-Google-Smtp-Source: ABdhPJxq09Jw6ETTxaWCSnFNNIjYqLB3731cctpYfHYAdtSMd7QIGGthQ61qCsA4uf9mrfm6QCsbLA== X-Received: by 2002:a17:90b:3ecd:b0:1dc:94f2:1bc0 with SMTP id rm13-20020a17090b3ecd00b001dc94f21bc0mr1566040pjb.32.1653349898147; Mon, 23 May 2022 16:51:38 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id pl15-20020a17090b268f00b001df4b919937sm257084pjb.16.2022.05.23.16.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 16:51:37 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Bin Meng , Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v9 09/12] target/riscv: Simplify counter predicate function Date: Mon, 23 May 2022 16:50:54 -0700 Message-Id: <20220523235057.123882-10-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220523235057.123882-1-atishp@rivosinc.com> References: <20220523235057.123882-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Reviewed-by: Bin Meng Acked-by: Alistair Francis Signed-off-by: Atish Patra --- target/riscv/csr.c | 111 ++++----------------------------------------- 1 file changed, 10 insertions(+), 101 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 723b52d836d3..e229f53c674d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -74,6 +74,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); int ctr_index; + target_ulong ctr_mask; int base_csrno = CSR_CYCLE; bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; @@ -82,122 +83,30 @@ static RISCVException ctr(CPURISCVState *env, int csrno) base_csrno += 0x80; } ctr_index = csrno - base_csrno; + ctr_mask = BIT(ctr_index); if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || (csrno >= CSR_CYCLEH && csrno <= CSR_INSTRETH)) { goto skip_ext_pmu_check; } - if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & BIT(ctr_index)))) { + if ((!cpu->cfg.pmu_num || !(cpu->pmu_avail_ctrs & ctr_mask))) { /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } skip_ext_pmu_check: - if (env->priv == PRV_S) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIME: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRET: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_TIMEH: - if (!get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_INSTRETH: - if (!get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_ILLEGAL_INST; - } - break; - } - } + if ((env->priv == PRV_S) && (!get_field(env->mcounteren, ctr_mask))) { + return RISCV_EXCP_ILLEGAL_INST; } if (riscv_cpu_virt_enabled(env)) { - switch (csrno) { - case CSR_CYCLE: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIME: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRET: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } - if (rv32) { - switch (csrno) { - case CSR_CYCLEH: - if (!get_field(env->hcounteren, COUNTEREN_CY) && - get_field(env->mcounteren, COUNTEREN_CY)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_TIMEH: - if (!get_field(env->hcounteren, COUNTEREN_TM) && - get_field(env->mcounteren, COUNTEREN_TM)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_INSTRETH: - if (!get_field(env->hcounteren, COUNTEREN_IR) && - get_field(env->mcounteren, COUNTEREN_IR)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H: - if (!get_field(env->hcounteren, 1 << ctr_index) && - get_field(env->mcounteren, 1 << ctr_index)) { - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; - } - break; - } + if (!get_field(env->mcounteren, ctr_mask)) { + /* The bit must be set in mcountern for HS mode access */ + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } else if (!get_field(env->hcounteren, ctr_mask)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } #endif -- 2.25.1