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From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>, Atish Patra <atishp@rivosinc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH v9 01/12] target/riscv: Fix PMU CSR predicate function
Date: Mon, 23 May 2022 16:50:46 -0700	[thread overview]
Message-ID: <20220523235057.123882-2-atishp@rivosinc.com> (raw)
In-Reply-To: <20220523235057.123882-1-atishp@rivosinc.com>

From: Atish Patra <atish.patra@wdc.com>

The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.

Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 target/riscv/csr.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3500e07f92e1..ee3a35afa256 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -72,6 +72,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
 #if !defined(CONFIG_USER_ONLY)
     CPUState *cs = env_cpu(env);
     RISCVCPU *cpu = RISCV_CPU(cs);
+    int ctr_index;
 
     if (!cpu->cfg.ext_counters) {
         /* The Counters extensions is not enabled */
@@ -99,8 +100,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
             }
             break;
         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
-            if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
-                get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+            ctr_index = csrno - CSR_CYCLE;
+            if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                 get_field(env->mcounteren, 1 << ctr_index)) {
                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
             }
             break;
@@ -126,8 +128,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
                 }
                 break;
             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
-                if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
-                    get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
+                ctr_index = csrno - CSR_CYCLEH;
+                if (!get_field(env->hcounteren, 1 << ctr_index) &&
+                     get_field(env->mcounteren, 1 << ctr_index)) {
                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
                 }
                 break;
-- 
2.25.1


  reply	other threads:[~2022-05-23 23:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-23 23:50 [PATCH v9 00/12] Improve PMU support Atish Patra
2022-05-23 23:50 ` Atish Patra [this message]
2022-05-23 23:50 ` [PATCH v9 02/12] target/riscv: Implement PMU CSR predicate function for S-mode Atish Patra
2022-05-23 23:50 ` [PATCH v9 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-05-23 23:50 ` [PATCH v9 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-05-23 23:50 ` [PATCH v9 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-05-23 23:50 ` [PATCH v9 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-05-23 23:50 ` [PATCH v9 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-05-23 23:50 ` [PATCH v9 08/12] target/riscv: Add sscofpmf extension support Atish Patra
2022-05-25 10:20   ` Frank Chang
2022-05-26  7:50     ` Atish Patra
2022-05-23 23:50 ` [PATCH v9 09/12] target/riscv: Simplify counter predicate function Atish Patra
2022-05-25 10:23   ` Frank Chang
2022-05-26  7:35     ` Atish Patra
2022-05-23 23:50 ` [PATCH v9 10/12] target/riscv: Add few cache related PMU events Atish Patra
2022-05-23 23:50 ` [PATCH v9 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-05-31  0:11   ` Alistair Francis
2022-05-23 23:50 ` [PATCH v9 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-05-31  0:12   ` Alistair Francis

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