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From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To: <chiawei_wang@aspeedtech.com>, <lukma@denx.de>,
	<seanga2@gmail.com>, <ryan_chen@aspeedtech.com>,
	<BMC-SW@aspeedtech.com>, <jagan@amarulasolutions.com>,
	<vigneshr@ti.com>, <clg@kaod.org>, <u-boot@lists.denx.de>,
	<p.yadav@ti.com>
Subject: [v4 09/12] spi: aspeed: SPI dirmap read support
Date: Tue, 24 May 2022 13:56:47 +0800	[thread overview]
Message-ID: <20220524055650.1115899-10-chin-ting_kuo@aspeedtech.com> (raw)
In-Reply-To: <20220524055650.1115899-1-chin-ting_kuo@aspeedtech.com>

From the HW point of view, the performance of
command read mode is greater than user mode slightly.
Thus, dirmap read framework is introduced to achieve
this goal.

In dirmap_create, a specific decoded address area with
flash size is assigned to each CS. CPU can thus access
the SPI flash as normal memory in dirmap_read function.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
---
 drivers/spi/spi-aspeed.c | 93 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
index 9574aff793..e5e348eb7b 100644
--- a/drivers/spi/spi-aspeed.c
+++ b/drivers/spi/spi-aspeed.c
@@ -85,6 +85,8 @@ struct aspeed_spi_info {
 
 static int aspeed_spi_trim_decoded_size(struct udevice *bus,
 					u32 decoded_sz_arr[]);
+static int aspeed_spi_decoded_range_config(struct udevice *bus,
+					   u32 decoded_sz_arr[]);
 
 static u32 aspeed_spi_get_io_mode(u32 bus_width)
 {
@@ -509,6 +511,95 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave,
 	return 0;
 }
 
+static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
+{
+	int ret = 0;
+	struct udevice *dev = desc->slave->dev;
+	struct udevice *bus = dev->parent;
+	struct aspeed_spi_plat *plat = dev_get_plat(bus);
+	struct aspeed_spi_priv *priv = dev_get_priv(bus);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+	const struct aspeed_spi_info *info = priv->info;
+	struct spi_mem_op op_tmpl = desc->info.op_tmpl;
+	u32 i;
+	u32 cs = slave_plat->cs;
+	u32 decoded_sz_arr[ASPEED_SPI_MAX_CS];
+	u32 reg_val;
+
+	if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
+		for (i = 0; i < priv->num_cs; i++) {
+			reg_val = readl(plat->ctrl_base +
+					REG_CE0_DECODED_ADDR_REG + i * 4);
+			decoded_sz_arr[i] =
+				info->segment_end(bus, reg_val) -
+				info->segment_start(bus, reg_val);
+		}
+
+		decoded_sz_arr[cs] = desc->info.length;
+
+		if (info->adjust_decoded_sz)
+			info->adjust_decoded_sz(bus, decoded_sz_arr);
+
+		for (i = 0; i < priv->num_cs; i++) {
+			dev_dbg(dev, "cs: %d, sz: 0x%x\n", i,
+				decoded_sz_arr[i]);
+		}
+
+		ret = aspeed_spi_decoded_range_config(bus, decoded_sz_arr);
+		if (ret)
+			return ret;
+
+		reg_val = readl(plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4) &
+			  (~info->cmd_io_ctrl_mask);
+		reg_val |= aspeed_spi_get_io_mode(op_tmpl.data.buswidth) |
+			   op_tmpl.cmd.opcode << 16 |
+			   ((op_tmpl.dummy.nbytes) & 0x3) << 6 |
+			   ((op_tmpl.dummy.nbytes) & 0x4) << 14 |
+			   CTRL_IO_MODE_CMD_READ;
+
+		writel(reg_val,
+		       plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4);
+		priv->flashes[cs].ce_ctrl_read = reg_val;
+
+		dev_dbg(dev, "read bus width: %d [0x%08x]\n",
+			op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read);
+	} else {
+		/*
+		 * dirmap_write is not supported currently due to a HW
+		 * limitation for command write mode: The written data
+		 * length should be multiple of 4-byte.
+		 */
+		return -EOPNOTSUPP;
+	}
+
+	return ret;
+}
+
+static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
+				      u64 offs, size_t len, void *buf)
+{
+	struct udevice *dev = desc->slave->dev;
+	struct aspeed_spi_priv *priv = dev_get_priv(dev->parent);
+	struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
+	u32 cs = slave_plat->cs;
+	int ret;
+
+	dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n",
+		desc->info.op_tmpl.cmd.opcode, offs, len);
+
+	if (priv->flashes[cs].ahb_win_sz < offs + len ||
+	    (offs + len) % 4 != 0) {
+		ret = aspeed_spi_exec_op_user_mode(desc->slave,
+						   &desc->info.op_tmpl);
+		if (ret != 0)
+			return 0;
+	} else {
+		memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len);
+	}
+
+	return len;
+}
+
 static struct aspeed_spi_flash *aspeed_spi_get_flash(struct udevice *dev)
 {
 	struct udevice *bus = dev->parent;
@@ -792,6 +883,8 @@ static int aspeed_spi_probe(struct udevice *bus)
 static const struct spi_controller_mem_ops aspeed_spi_mem_ops = {
 	.supports_op = aspeed_spi_supports_op,
 	.exec_op = aspeed_spi_exec_op_user_mode,
+	.dirmap_create = aspeed_spi_dirmap_create,
+	.dirmap_read = aspeed_spi_dirmap_read,
 };
 
 static const struct dm_spi_ops aspeed_spi_ops = {
-- 
2.25.1


  parent reply	other threads:[~2022-05-24  6:00 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-24  5:56 [v4 00/12] Add ASPEED SPI controller driver Chin-Ting Kuo
2022-05-24  5:56 ` [v4 01/12] clk: aspeed: Get HCLK frequency support Chin-Ting Kuo
2022-05-24  5:56 ` [v4 02/12] pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support Chin-Ting Kuo
2022-05-24  5:56 ` [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver Chin-Ting Kuo
2022-07-01  9:28   ` Cédric Le Goater
2022-07-03  8:47     ` Chin-Ting Kuo
2022-07-04 15:24       ` Cédric Le Goater
2022-07-06 11:06         ` Chin-Ting Kuo
2022-07-07  5:36   ` Joel Stanley
2022-07-08  5:42     ` Chin-Ting Kuo
2022-07-08  8:52       ` Cédric Le Goater
2022-07-11  6:51         ` Chin-Ting Kuo
2022-05-24  5:56 ` [v4 04/12] configs: aspeed: Enable SPI flash features Chin-Ting Kuo
2022-07-01  9:28   ` Cédric Le Goater
2022-07-01 11:50     ` Cédric Le Goater
2022-07-03  9:00       ` Chin-Ting Kuo
2022-07-04  8:01         ` Cédric Le Goater
2022-05-24  5:56 ` [v4 05/12] MAINTAINERS: Add ASPEED SPI driver file Chin-Ting Kuo
2022-07-01 11:52   ` Jagan Teki
2022-08-11  5:20     ` Chin-Ting Kuo
2022-05-24  5:56 ` [v4 06/12] arm: dts: aspeed: Update SPI flash node settings Chin-Ting Kuo
2022-07-01  9:42   ` Cédric Le Goater
2022-07-03  8:54     ` Chin-Ting Kuo
2022-05-24  5:56 ` [v4 07/12] spi-mem: Add dirmap API from Linux Chin-Ting Kuo
2022-07-01  9:36   ` Cédric Le Goater
2022-07-03  8:49     ` Chin-Ting Kuo
2022-07-01 12:04   ` Jagan Teki
2022-08-11  5:19     ` Chin-Ting Kuo
2022-05-24  5:56 ` [v4 08/12] mtd: spi-nor: Use spi-mem dirmap API Chin-Ting Kuo
2022-05-24  5:56 ` Chin-Ting Kuo [this message]
2022-05-24  5:56 ` [v4 10/12] configs: aspeed: Enable CONFIG_SPI_DIRMAP Chin-Ting Kuo
2022-05-24  5:56 ` [v4 11/12] mtd: spi-nor-ids: Add Winbond W25Q512JV ID Chin-Ting Kuo
2022-07-01  9:43   ` Cédric Le Goater
2022-05-24  5:56 ` [v4 12/12] spi: aspeed: Fix bug when SPI_NOR_4B_OPCODES flag is set Chin-Ting Kuo
2022-07-01  9:44   ` Cédric Le Goater
2022-07-03  8:56     ` Chin-Ting Kuo
2022-06-26  4:56 ` [v4 00/12] Add ASPEED SPI controller driver Chin-Ting Kuo
2022-06-26 16:15   ` Cédric Le Goater
2022-06-27  1:41     ` Chin-Ting Kuo
2022-07-01 11:57 ` Jagan Teki
2022-08-11  5:25   ` Chin-Ting Kuo

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