From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
mark.cave-ayland@ilande.co.uk, mst@redhat.com,
imammedo@redhat.com, ani@anisinha.ca
Subject: [PATCH v5 08/43] target/loongarch: Add fixed point atomic instruction translation
Date: Tue, 24 May 2022 16:17:29 +0800 [thread overview]
Message-ID: <20220524081804.3608101-9-yangxiaojuan@loongson.cn> (raw)
In-Reply-To: <20220524081804.3608101-1-yangxiaojuan@loongson.cn>
From: Song Gao <gaosong@loongson.cn>
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
.../loongarch/insn_trans/trans_atomic.c.inc | 113 ++++++++++++++++++
.../loongarch/insn_trans/trans_memory.c.inc | 2 +-
target/loongarch/insns.decode | 44 +++++++
target/loongarch/translate.c | 1 +
4 files changed, 159 insertions(+), 1 deletion(-)
create mode 100644 target/loongarch/insn_trans/trans_atomic.c.inc
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc
new file mode 100644
index 0000000000..6763c1c301
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_addi_tl(t0, src1, a->imm);
+ tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop);
+ tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));
+ tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
+ TCGv t0 = tcg_temp_new();
+ TCGv val = tcg_temp_new();
+
+ TCGLabel *l1 = gen_new_label();
+ TCGLabel *done = gen_new_label();
+
+ tcg_gen_addi_tl(t0, src1, a->imm);
+ tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);
+ tcg_gen_movi_tl(dest, 0);
+ tcg_gen_br(done);
+
+ gen_set_label(l1);
+ tcg_gen_mov_tl(val, src2);
+ /* generate cmpxchg */
+ tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval,
+ val, ctx->mem_idx, mop);
+ tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval);
+ gen_set_label(done);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+ tcg_temp_free(t0);
+ tcg_temp_free(val);
+
+ return true;
+}
+
+static bool gen_am(DisasContext *ctx, arg_rrr *a,
+ void (*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
+ MemOp mop)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv val = gpr_src(ctx, a->rk, EXT_NONE);
+
+ if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Warning: source register overlaps destination register"
+ "in atomic insn at pc=0x" TARGET_FMT_lx "\n",
+ ctx->base.pc_next - 4);
+ return false;
+ }
+
+ func(dest, addr, val, ctx->mem_idx, mop);
+ gen_set_gpr(a->rd, dest, EXT_NONE);
+
+ return true;
+}
+
+TRANS(ll_w, gen_ll, MO_TESL)
+TRANS(sc_w, gen_sc, MO_TESL)
+TRANS(ll_d, gen_ll, MO_TEUQ)
+TRANS(sc_d, gen_sc, MO_TEUQ)
+TRANS(amswap_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
+TRANS(amswap_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
+TRANS(amadd_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
+TRANS(amadd_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
+TRANS(amand_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
+TRANS(amand_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
+TRANS(amor_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
+TRANS(amor_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
+TRANS(amxor_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
+TRANS(amxor_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
+TRANS(ammax_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
+TRANS(ammax_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
+TRANS(ammin_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
+TRANS(ammin_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
+TRANS(ammax_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
+TRANS(ammax_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
+TRANS(ammin_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
+TRANS(ammin_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
+TRANS(amswap_db_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
+TRANS(amswap_db_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
+TRANS(amadd_db_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
+TRANS(amadd_db_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
+TRANS(amand_db_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
+TRANS(amand_db_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
+TRANS(amor_db_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
+TRANS(amor_db_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
+TRANS(amxor_db_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
+TRANS(amxor_db_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
+TRANS(ammax_db_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
+TRANS(ammax_db_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
+TRANS(ammin_db_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
+TRANS(ammin_db_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
+TRANS(ammax_db_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
+TRANS(ammax_db_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
+TRANS(ammin_db_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
+TRANS(ammin_db_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
index 10914acf52..d5eb31147c 100644
--- a/target/loongarch/insn_trans/trans_memory.c.inc
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
@@ -172,7 +172,7 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
if (a->imm) {
temp = tcg_temp_new();
- tcg_gen_addi_tl(temp, addr, a->im);
+ tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 1156e6965c..8d247aa68c 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -193,3 +193,47 @@ stle_b 0011 10000111 11100 ..... ..... ..... @rrr
stle_h 0011 10000111 11101 ..... ..... ..... @rrr
stle_w 0011 10000111 11110 ..... ..... ..... @rrr
stle_d 0011 10000111 11111 ..... ..... ..... @rrr
+
+#
+# Fixed point atomic instruction
+#
+ll_w 0010 0000 .............. ..... ..... @rr_i14s2
+sc_w 0010 0001 .............. ..... ..... @rr_i14s2
+ll_d 0010 0010 .............. ..... ..... @rr_i14s2
+sc_d 0010 0011 .............. ..... ..... @rr_i14s2
+amswap_w 0011 10000110 00000 ..... ..... ..... @rrr
+amswap_d 0011 10000110 00001 ..... ..... ..... @rrr
+amadd_w 0011 10000110 00010 ..... ..... ..... @rrr
+amadd_d 0011 10000110 00011 ..... ..... ..... @rrr
+amand_w 0011 10000110 00100 ..... ..... ..... @rrr
+amand_d 0011 10000110 00101 ..... ..... ..... @rrr
+amor_w 0011 10000110 00110 ..... ..... ..... @rrr
+amor_d 0011 10000110 00111 ..... ..... ..... @rrr
+amxor_w 0011 10000110 01000 ..... ..... ..... @rrr
+amxor_d 0011 10000110 01001 ..... ..... ..... @rrr
+ammax_w 0011 10000110 01010 ..... ..... ..... @rrr
+ammax_d 0011 10000110 01011 ..... ..... ..... @rrr
+ammin_w 0011 10000110 01100 ..... ..... ..... @rrr
+ammin_d 0011 10000110 01101 ..... ..... ..... @rrr
+ammax_wu 0011 10000110 01110 ..... ..... ..... @rrr
+ammax_du 0011 10000110 01111 ..... ..... ..... @rrr
+ammin_wu 0011 10000110 10000 ..... ..... ..... @rrr
+ammin_du 0011 10000110 10001 ..... ..... ..... @rrr
+amswap_db_w 0011 10000110 10010 ..... ..... ..... @rrr
+amswap_db_d 0011 10000110 10011 ..... ..... ..... @rrr
+amadd_db_w 0011 10000110 10100 ..... ..... ..... @rrr
+amadd_db_d 0011 10000110 10101 ..... ..... ..... @rrr
+amand_db_w 0011 10000110 10110 ..... ..... ..... @rrr
+amand_db_d 0011 10000110 10111 ..... ..... ..... @rrr
+amor_db_w 0011 10000110 11000 ..... ..... ..... @rrr
+amor_db_d 0011 10000110 11001 ..... ..... ..... @rrr
+amxor_db_w 0011 10000110 11010 ..... ..... ..... @rrr
+amxor_db_d 0011 10000110 11011 ..... ..... ..... @rrr
+ammax_db_w 0011 10000110 11100 ..... ..... ..... @rrr
+ammax_db_d 0011 10000110 11101 ..... ..... ..... @rrr
+ammin_db_w 0011 10000110 11110 ..... ..... ..... @rrr
+ammin_db_d 0011 10000110 11111 ..... ..... ..... @rrr
+ammax_db_wu 0011 10000111 00000 ..... ..... ..... @rrr
+ammax_db_du 0011 10000111 00001 ..... ..... ..... @rrr
+ammin_db_wu 0011 10000111 00010 ..... ..... ..... @rrr
+ammin_db_du 0011 10000111 00011 ..... ..... ..... @rrr
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 3b8ada08ed..7118e6c17d 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -154,6 +154,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_shift.c.inc"
#include "insn_trans/trans_bit.c.inc"
#include "insn_trans/trans_memory.c.inc"
+#include "insn_trans/trans_atomic.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
2.31.1
next prev parent reply other threads:[~2022-05-24 8:51 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 8:17 [PATCH v5 00/43] Add LoongArch softmmu support Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 01/43] target/loongarch: Add README Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 02/43] target/loongarch: Add core definition Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 03/43] target/loongarch: Add main translation routines Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 04/43] target/loongarch: Add fixed point arithmetic instruction translation Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 05/43] target/loongarch: Add fixed point shift " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 06/43] target/loongarch: Add fixed point bit " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 07/43] target/loongarch: Add fixed point load/store " Xiaojuan Yang
2022-05-24 8:17 ` Xiaojuan Yang [this message]
2022-05-24 8:17 ` [PATCH v5 09/43] target/loongarch: Add fixed point extra " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 10/43] target/loongarch: Add floating point arithmetic " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 11/43] target/loongarch: Add floating point comparison " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 12/43] target/loongarch: Add floating point conversion " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 13/43] target/loongarch: Add floating point move " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 14/43] target/loongarch: Add floating point load/store " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 15/43] target/loongarch: Add branch " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 16/43] target/loongarch: Add disassembler Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 17/43] target/loongarch: Add target build suport Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 18/43] target/loongarch: Add system emulation introduction Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 19/43] target/loongarch: Add CSRs definition Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 20/43] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 21/43] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 22/43] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 23/43] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 24/43] target/loongarch: Add constant timer support Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 25/43] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 26/43] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 27/43] target/loongarch: Add TLB instruction support Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 28/43] target/loongarch: Add other core instructions support Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 29/43] target/loongarch: Add timer related " Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 30/43] hw/loongarch: Add support loongson3 virt machine type Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 31/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 35/43] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 36/43] Enable common virtio pci support for LoongArch Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 37/43] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2022-05-24 8:17 ` [PATCH v5 38/43] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2022-05-24 8:18 ` [PATCH v5 39/43] hw/loongarch: Add LoongArch load elf function Xiaojuan Yang
2022-05-24 8:18 ` [PATCH v5 40/43] hw/loongarch: Add LoongArch ls7a acpi device support Xiaojuan Yang
2022-05-26 8:42 ` Igor Mammedov
2022-05-26 22:18 ` maobibo
2022-05-30 10:21 ` Igor Mammedov
2022-05-31 3:43 ` maobibo
2022-05-24 8:18 ` [PATCH v5 41/43] target/loongarch: Add gdb support Xiaojuan Yang
2022-05-24 8:18 ` [PATCH v5 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system Xiaojuan Yang
2022-05-24 8:18 ` [PATCH v5 43/43] target/loongarch: 'make check-tcg' support Xiaojuan Yang
2022-05-24 22:32 ` [PATCH v5 00/43] Add LoongArch softmmu support Richard Henderson
2022-05-24 22:41 ` Richard Henderson
2022-05-25 0:44 ` yangxiaojuan
2022-05-25 3:31 ` Richard Henderson
2022-05-25 0:27 ` yangxiaojuan
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