[RFC v2 14/96] cl8k: add chip.h

[viktor.barna@celeno.com]

From: Viktor Barna <viktor.barna@celeno.com>

(Part of the split. Please, take a look at the cover letter for more
details).

Signed-off-by: Viktor Barna <viktor.barna@celeno.com>
---
 drivers/net/wireless/celeno/cl8k/chip.h | 182 ++++++++++++++++++++++++
 1 file changed, 182 insertions(+)
 create mode 100644 drivers/net/wireless/celeno/cl8k/chip.h

diff --git a/drivers/net/wireless/celeno/cl8k/chip.h b/drivers/net/wireless/celeno/cl8k/chip.h
new file mode 100644
index 000000000000..29d02cb85fb4
--- /dev/null
+++ b/drivers/net/wireless/celeno/cl8k/chip.h
@@ -0,0 +1,182 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/* Copyright(c) 2019-2022, Celeno Communications Ltd. */
+
+#ifndef CL_CHIP_H
+#define CL_CHIP_H
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/pci.h>
+
+#include "pci.h"
+#include "calib.h"
+#include "sounding.h"
+#include "temperature.h"
+#include "platform.h"
+#include "phy.h"
+#include "ela.h"
+
+/**
+ * DOC: Chip basics
+ *
+ * Each physical device of ours is a separate chip, that is being described by
+ * %cl_chip structure. Each chip may be several (%TCV_MAX) transceivers (bands),
+ * which are operating simultaneously and are described via own %ieee80211_hw
+ * unit (it refers to the private driver via specific pointer, described by
+ * %cl_hw). Totally, 3 types of bands are supported - 2.4G/5.2G/6G. Driver
+ * supports multiple chips (up to %CHIP_MAX). Since the driver can control up
+ * to %TCV_TOTAL entities, it is important to pass it's pointer to each
+ * function, that operates somehow with specific band/transceiver.
+ *
+ * Chip instance is being created during bus probing procedure and is being
+ * destroyed during bus removal procedure.
+ *
+ * Physically, 80xx chips family may have different amount of antennas (4/6/8),
+ * each of which may not be hardly bounded to the specific band (both bands are
+ * sharing them and may change antenna combinations in specific circumstances).
+ *
+ * Each band (transceiver) has own FW, that is being loaded by
+ * request_firmware() call during chip structure initialization procedure. At
+ * lower layer each band is associated with own HW die by LMAC and SMAC names
+ * (e.g: 5.2G and 2.4G). Celeno is using XMAC naming when we are referring to any
+ * of LMAC/SMAC components.
+ */
+
+struct cl_ring_indices {
+	struct cl_ipc_ring_indices *params;
+	dma_addr_t dma_addr;
+	struct dma_pool *pool;
+};
+
+struct cl_chip {
+	u8 idx;
+	bool umac_active;
+	u8 max_antennas;
+	u8 rfic_version;
+	enum cl_bus_type bus_type;
+	struct pci_driver pci_drv;
+	struct pci_dev *pci_dev;
+	void __iomem *pci_bar0_virt_addr;
+	struct cl_irq_stats irq_stats;
+	struct cl_temperature temperature;
+	struct cl_chip_conf *conf;
+	struct device *dev;
+	struct cl_hw *cl_hw_lut[TCV_MAX];
+	struct cl_hw *cl_hw_tcv0;
+	struct cl_hw *cl_hw_tcv1;
+	u8 cdb_mode_maj;
+	spinlock_t isr_lock;
+	spinlock_t spi_lock;
+	struct mutex start_msg_lock;
+	bool first_start_sent;
+	rwlock_t cl_hw_lock;
+	void (*ipc_host2xmac_trigger_set)(struct cl_chip *chip, u32 value);
+	bool rf_reg_overwrite;
+	struct cl_fem_params fem;
+	struct eeprom *eeprom_cache;
+	size_t eeprom_bin_size;
+	int (*eeprom_read_block)(struct cl_chip *chip, u16 addr, u16 num_of_byte, u8 *data);
+	int (*eeprom_write_block)(struct cl_chip *chip, u16 addr, u16 num_of_byte, u8 *data);
+	struct cl_iq_dcoc_conf iq_dcoc_conf;
+	struct cl_afe_reg orig_afe_reg;
+	struct cl_calib_db calib_db;
+	struct cl_ela_db ela_db;
+	struct cl_ring_indices ring_indices;
+	u8 reg_dbg;
+	struct cl_xmem xmem_db;
+	bool is_calib_eeprom_loaded;
+	struct workqueue_struct *chip_workqueue;
+	struct mutex recovery_mutex;
+	struct mutex calib_runtime_mutex;
+	struct mutex set_idle_mutex;
+	struct cl_platform platform;
+};
+
+struct cl_controller_reg {
+	u32 breset;
+	u32 debug_enable;
+	u32 dreset;
+	u32 ocd_halt_on_reset;
+	u32 run_stall;
+};
+
+struct cl_chip *cl_chip_alloc(u8 idx);
+void cl_chip_dealloc(struct cl_chip *chip);
+int cl_chip_init(struct cl_chip *chip);
+void cl_chip_deinit(struct cl_chip *chip);
+bool cl_chip_is_enabled(struct cl_chip *chip);
+bool cl_chip_is_both_enabled(struct cl_chip *chip);
+bool cl_chip_is_tcv0_enabled(struct cl_chip *chip);
+bool cl_chip_is_tcv1_enabled(struct cl_chip *chip);
+bool cl_chip_is_only_tcv0_enabled(struct cl_chip *chip);
+bool cl_chip_is_only_tcv1_enabled(struct cl_chip *chip);
+void cl_chip_set_hw(struct cl_chip *chip, struct cl_hw *cl_hw);
+void cl_chip_unset_hw(struct cl_chip *chip, struct cl_hw *cl_hw);
+bool cl_chip_is_8ant(struct cl_chip *chip);
+bool cl_chip_is_6ant(struct cl_chip *chip);
+bool cl_chip_is_4ant(struct cl_chip *chip);
+bool cl_chip_is_3ant(struct cl_chip *chip);
+bool cl_chip_is_6g(struct cl_chip *chip);
+u16 cl_chip_get_device_id(struct cl_chip *chip);
+
+#define CC_MAX_LEN 3 /* 2 characters + null */
+#define RM_MAX_LEN 5 /* 4 characters + null */
+#define FW_MAX_NAME 32
+
+struct cl_chip_conf {
+	bool ce_tcv_enabled[TCV_MAX];
+	s8 ce_lmac[FW_MAX_NAME];
+	s8 ce_smac[FW_MAX_NAME];
+	s32 ce_irq_smp_affinity;
+	u8 ce_eeprom_mode;
+	bool ce_production_mode;
+	bool ci_pci_msi_enable;
+	u8 ci_dma_lli_max_chan[TCV_MAX];
+	s8 ci_country_code[CC_MAX_LEN];
+	s8 ci_regdom_mode[RM_MAX_LEN];
+	s8 ce_ela_mode[STR_LEN_64B];
+	u8 ci_phy_dev;
+	s8 ce_debug_level;
+	u8 ce_host_pci_gen_ver;
+	s32 ci_scale_down_fw;
+	bool ce_temp_comp_en;
+	u8 ce_temp_protect_en;
+	s8 ce_temp_protect_delta;
+	s16 ce_temp_protect_th_max;
+	s16 ce_temp_protect_th_min;
+	u16 ce_temp_protect_tx_period_ms;
+	s16 ce_temp_protect_radio_off_th;
+	bool ci_phy_load_bootdrv;
+	u8 ce_phys_mac_addr[ETH_ALEN];
+	bool ce_lam_enable;
+	u8 ce_first_mask_bit;
+	bool ci_no_capture_noise_sleep;
+	bool ci_afe_config_en;
+	u32 ci_afe_vc_ref;
+	u32 ci_afe_vc_avd;
+	u32 ci_afe_vc_cml;
+	u16 ci_afe_eoc_ctrl;
+	u8 ci_afe_ch_cml_sel;
+	u8 ci_afe_cml_sel;
+	bool ci_afe_loopback;
+	bool ci_afe_hw_mode;
+	u8 ci_dcoc_mv_thr[CHNL_BW_MAX];
+	bool ci_calib_check_errors;
+	s8 ci_lolc_db_thr;
+	s8 ci_iq_db_thr;
+	bool ci_rx_resched_tasklet;
+	u32 ci_rx_skb_max;
+	bool ci_tcv1_chains_sx0;
+	u16 ci_sim_device_id;
+	bool ce_calib_runtime_en;
+	bool ci_calib_eeprom_en;
+	bool ci_calib_runtime_force;
+	bool ci_la_mirror_en;
+
+	/* New NVRAM parameters must be added to cl_chip_config_print() */
+};
+
+int cl_chip_config_read(struct cl_chip *chip);
+void cl_chip_config_dealloc(struct cl_chip *chip);
+
+#endif /* CL_CHIP_H */
-- 
2.36.1