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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/eeprom.h | 283 ++++++++++++++++++++++ 1 file changed, 283 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/eeprom.h diff --git a/drivers/net/wireless/celeno/cl8k/eeprom.h b/drivers/net/wireless/celeno/cl8k/eeprom.h new file mode 100644 index 000000000000..2680af90484b --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/eeprom.h @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* Copyright(c) 2019-2022, Celeno Communications Ltd. */ + +#ifndef CL_EEPROM_H +#define CL_EEPROM_H + +#include + +#include "def.h" +#include "phy.h" +#include "calib.h" + +#define SERIAL_NUMBER_SIZE 32 +#define BIT_MAP_SIZE 20 +#define EXT_BIT_MAP_SIZE (BIT_MAP_SIZE * 2) +#define NUM_OF_PIVOTS 20 +#define NUM_PIVOT_PHYS (MAX_ANTENNAS * NUM_OF_PIVOTS) + +#ifdef CONFIG_CL8K_EEPROM_STM24256 +#define BIT_MAP_SIZE_20MHZ_TCV0 9 +#define BIT_MAP_SIZE_20MHZ_TCV1 6 +#define BIT_MAP_SIZE_40MHZ_TCV0 4 +#define BIT_MAP_SIZE_40MHZ_TCV1 4 +#define BIT_MAP_SIZE_80MHZ_TCV0 2 +#define BIT_MAP_SIZE_80MHZ_TCV1 2 +#define BIT_MAP_SIZE_160MHZ_TCV0 1 +#define BIT_MAP_SIZE_160MHZ_TCV1 3 + +#define EEPROM_CALIB_DATA_ELEM_NUM_20MHZ_TCV0 10 +#define EEPROM_CALIB_DATA_ELEM_NUM_20MHZ_TCV1 7 +#define EEPROM_CALIB_DATA_ELEM_NUM_40MHZ_TCV0 9 +#define EEPROM_CALIB_DATA_ELEM_NUM_40MHZ_TCV1 7 +#define EEPROM_CALIB_DATA_ELEM_NUM_80MHZ_TCV0 8 +#define EEPROM_CALIB_DATA_ELEM_NUM_80MHZ_TCV1 6 +#define EEPROM_CALIB_DATA_ELEM_NUM_160MHZ_TCV0 6 +#define EEPROM_CALIB_DATA_ELEM_NUM_160MHZ_TCV1 2 +#endif + +struct eeprom_hw { + u8 reserved[96]; +} __packed; + +struct eeprom_general { + u8 version; + u8 flavor; + u8 mac_address[6]; + u8 temp_diff; /* Default value TEMP_DIFF_INVALID = 0x7F */ + u8 serial_number[SERIAL_NUMBER_SIZE]; + u8 pwr_table_id[2]; + u8 reserved[53]; +} __packed; + +struct eeprom_fem { + u8 wiring_id; + u16 fem_lut[FEM_TYPE_MAX]; + u32 platform_id; + u8 reserved[19]; +} __packed; + +struct eeprom_phy_calib { + s8 pow; + s8 offset; + s8 tmp; +} __packed; + +struct point { + u8 chan; + u8 phy; + u8 idx; + u16 addr; + struct eeprom_phy_calib calib; +} __packed; + +#ifdef CONFIG_CL8K_EEPROM_STM24256 +struct iq { + __le32 coef0; + __le32 coef1; + __le32 coef2; + __le32 gain; +} __packed; + +struct score { + s8 iq_tx_score; + s8 iq_tx_worst_score; + s8 iq_rx_score; + s8 iq_rx_worst_score; + s16 dcoc_i_mv[DCOC_LNA_GAIN_NUM]; + s16 dcoc_q_mv[DCOC_LNA_GAIN_NUM]; + s32 lolc_score; +} __packed; + +struct eeprom_calib_data { + u8 valid; + u8 temperature; + u32 lolc[MAX_ANTENNAS]; + struct cl_dcoc_calib dcoc[MAX_ANTENNAS][DCOC_LNA_GAIN_NUM]; + struct iq iq_tx[MAX_ANTENNAS]; + struct iq iq_rx[MAX_ANTENNAS]; + struct score score[MAX_ANTENNAS]; +} __packed; +#endif + +struct eeprom_calib_power { + u16 freq_offset; + u8 chan_bmp[BIT_MAP_SIZE]; + struct eeprom_phy_calib phy_calib[NUM_PIVOT_PHYS]; +} __packed; + +#ifdef CONFIG_CL8K_EEPROM_STM24256 +struct eeprom_calib_iq_dcoc { + u8 calib_version; + u8 chan_20mhz_bmp_tcv0[BIT_MAP_SIZE_20MHZ_TCV0]; + u8 chan_20mhz_bmp_tcv1[BIT_MAP_SIZE_20MHZ_TCV1]; + u8 chan_40mhz_bmp_tcv0[BIT_MAP_SIZE_40MHZ_TCV0]; + u8 chan_40mhz_bmp_tcv1[BIT_MAP_SIZE_40MHZ_TCV1]; + u8 chan_80mhz_bmp_tcv0[BIT_MAP_SIZE_80MHZ_TCV0]; + u8 chan_80mhz_bmp_tcv1[BIT_MAP_SIZE_80MHZ_TCV1]; + u8 chan_160mhz_bmp_tcv0[BIT_MAP_SIZE_160MHZ_TCV0]; + u8 chan_160mhz_bmp_tcv1[BIT_MAP_SIZE_160MHZ_TCV1]; + struct eeprom_calib_data + calib_20_data_tcv0[EEPROM_CALIB_DATA_ELEM_NUM_20MHZ_TCV0]; + struct eeprom_calib_data + calib_20_data_tcv1[EEPROM_CALIB_DATA_ELEM_NUM_20MHZ_TCV1]; + struct eeprom_calib_data + calib_40_data_tcv0[EEPROM_CALIB_DATA_ELEM_NUM_40MHZ_TCV0]; + struct eeprom_calib_data + calib_40_data_tcv1[EEPROM_CALIB_DATA_ELEM_NUM_40MHZ_TCV1]; + struct eeprom_calib_data + calib_80_data_tcv0[EEPROM_CALIB_DATA_ELEM_NUM_80MHZ_TCV0]; + struct eeprom_calib_data + calib_80_data_tcv1[EEPROM_CALIB_DATA_ELEM_NUM_80MHZ_TCV1]; + struct eeprom_calib_data + calib_160_data_tcv0[EEPROM_CALIB_DATA_ELEM_NUM_160MHZ_TCV0]; + struct eeprom_calib_data + calib_160_data_tcv1[EEPROM_CALIB_DATA_ELEM_NUM_160MHZ_TCV1]; +} __packed; +#endif + +struct eeprom { + struct eeprom_hw hw; + struct eeprom_general general; + struct eeprom_fem fem; + struct eeprom_calib_power calib_power; +#ifdef CONFIG_CL8K_EEPROM_STM24256 + struct eeprom_calib_iq_dcoc calib_iq_dcoc; +#endif +} __packed; + +enum { + ADDR_HW = offsetof(struct eeprom, hw), + ADDR_HW_RESERVED = ADDR_HW + offsetof(struct eeprom_hw, reserved), + + ADDR_GEN = offsetof(struct eeprom, general), + ADDR_GEN_VERSION = ADDR_GEN + offsetof(struct eeprom_general, version), + ADDR_GEN_FLAVOR = ADDR_GEN + offsetof(struct eeprom_general, flavor), + ADDR_GEN_MAC_ADDR = ADDR_GEN + offsetof(struct eeprom_general, mac_address), + ADDR_GEN_TEMP_DIFF = ADDR_GEN + offsetof(struct eeprom_general, temp_diff), + ADDR_GEN_SERIAL_NUMBER = ADDR_GEN + offsetof(struct eeprom_general, serial_number), + ADDR_GEN_PWR_TABLE_ID = ADDR_GEN + offsetof(struct eeprom_general, pwr_table_id), + ADDR_GEN_RESERVED = ADDR_GEN + offsetof(struct eeprom_general, reserved), + + ADDR_FEM = offsetof(struct eeprom, fem), + ADDR_FEM_WIRING_ID = ADDR_FEM + offsetof(struct eeprom_fem, wiring_id), + ADDR_FEM_LUT = ADDR_FEM + offsetof(struct eeprom_fem, fem_lut), + ADDR_FEM_PLATFORM_ID = ADDR_FEM + offsetof(struct eeprom_fem, platform_id), + ADDR_FEM_RESERVED = ADDR_FEM + offsetof(struct eeprom_fem, reserved), + + ADDR_CALIB_POWER = offsetof(struct eeprom, calib_power), + ADDR_CALIB_POWER_FREQ_OFFSET = ADDR_CALIB_POWER + + offsetof(struct eeprom_calib_power, freq_offset), + ADDR_CALIB_POWER_CHAN_BMP = ADDR_CALIB_POWER + + offsetof(struct eeprom_calib_power, chan_bmp), + ADDR_CALIB_POWER_PHY = ADDR_CALIB_POWER + + offsetof(struct eeprom_calib_power, phy_calib), + +#ifdef CONFIG_CL8K_EEPROM_STM24256 + ADDR_CALIB_IQ_DCOC = offsetof(struct eeprom, calib_iq_dcoc), + ADDR_CALIB_IQ_DCOC_VERSION = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_version), + ADDR_CALIB_IQ_DCOC_CHANNEL_20MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_20mhz_bmp_tcv0), + ADDR_CALIB_IQ_DCOC_CHANNEL_20MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_20mhz_bmp_tcv1), + ADDR_CALIB_IQ_DCOC_CHANNEL_40MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_40mhz_bmp_tcv0), + ADDR_CALIB_IQ_DCOC_CHANNEL_40MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_40mhz_bmp_tcv1), + ADDR_CALIB_IQ_DCOC_CHANNEL_80MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_80mhz_bmp_tcv0), + ADDR_CALIB_IQ_DCOC_CHANNEL_80MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_80mhz_bmp_tcv1), + ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_160mhz_bmp_tcv0), + ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, chan_160mhz_bmp_tcv1), + ADDR_CALIB_IQ_DCOC_DATA_20MHZ_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_20_data_tcv0), + ADDR_CALIB_IQ_DCOC_DATA_20MHZ_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_20_data_tcv1), + ADDR_CALIB_IQ_DCOC_DATA_40MHZ_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_40_data_tcv0), + ADDR_CALIB_IQ_DCOC_DATA_40MHZ_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_40_data_tcv1), + ADDR_CALIB_IQ_DCOC_DATA_80MHZ_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_80_data_tcv0), + ADDR_CALIB_IQ_DCOC_DATA_80MHZ_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_80_data_tcv1), + ADDR_CALIB_IQ_DCOC_DATA_160MHZ_TCV0 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_160_data_tcv0), + ADDR_CALIB_IQ_DCOC_DATA_160MHZ_TCV1 = ADDR_CALIB_IQ_DCOC + + offsetof(struct eeprom_calib_iq_dcoc, calib_160_data_tcv1), +#endif + SIZE_HW = sizeof(struct eeprom_hw), + SIZE_HW_RESERVED = ADDR_GEN - ADDR_HW_RESERVED, + + SIZE_GEN = sizeof(struct eeprom_general), + SIZE_GEN_VERSION = ADDR_GEN_FLAVOR - ADDR_GEN_VERSION, + SIZE_GEN_FLAVOR = ADDR_GEN_MAC_ADDR - ADDR_GEN_FLAVOR, + SIZE_GEN_MAC_ADDR = ADDR_GEN_TEMP_DIFF - ADDR_GEN_MAC_ADDR, + SIZE_GEN_TEMP_DIFF = ADDR_GEN_SERIAL_NUMBER - ADDR_GEN_TEMP_DIFF, + SIZE_GEN_SERIAL_NUMBER = ADDR_GEN_PWR_TABLE_ID - ADDR_GEN_SERIAL_NUMBER, + SIZE_GEN_PWR_TABLE_ID = ADDR_GEN_RESERVED - ADDR_GEN_PWR_TABLE_ID, + SIZE_GEN_RESERVED = ADDR_FEM - ADDR_GEN_RESERVED, + + SIZE_FEM = sizeof(struct eeprom_fem), + SIZE_FEM_WIRING_ID = ADDR_FEM_LUT - ADDR_FEM_WIRING_ID, + SIZE_FEM_LUT = ADDR_FEM_PLATFORM_ID - ADDR_FEM_LUT, + SIZE_FEM_PLATFORM_ID = ADDR_FEM_RESERVED - ADDR_FEM_PLATFORM_ID, + + SIZE_CALIB_POWER = sizeof(struct eeprom_calib_power), + SIZE_CALIB_POWER_FREQ_OFFSET = ADDR_CALIB_POWER_CHAN_BMP - ADDR_CALIB_POWER_FREQ_OFFSET, + SIZE_CALIB_POWER_CHAN_BMP = ADDR_CALIB_POWER_PHY - ADDR_CALIB_POWER_CHAN_BMP, +#ifdef CONFIG_CL8K_EEPROM_STM24256 + SIZE_CALIB_POWER_PHY = ADDR_CALIB_IQ_DCOC_VERSION - ADDR_CALIB_POWER_PHY, +#else + SIZE_CALIB_POWER_PHY = sizeof(struct eeprom_phy_calib) * NUM_PIVOT_PHYS, +#endif + +#ifdef CONFIG_CL8K_EEPROM_STM24256 + SIZE_CALIB_IQ_DCOC_VERSION = ADDR_CALIB_IQ_DCOC_CHANNEL_20MHZ_BMP_TCV0 - + ADDR_CALIB_IQ_DCOC_VERSION, + SIZE_CALIB_IQ_DCOC_20MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC_CHANNEL_20MHZ_BMP_TCV1 - + ADDR_CALIB_IQ_DCOC_CHANNEL_20MHZ_BMP_TCV0, + SIZE_CALIB_IQ_DCOC_20MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC_CHANNEL_40MHZ_BMP_TCV0 - + ADDR_CALIB_IQ_DCOC_CHANNEL_20MHZ_BMP_TCV1, + SIZE_CALIB_IQ_DCOC_40MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC_CHANNEL_40MHZ_BMP_TCV1 - + ADDR_CALIB_IQ_DCOC_CHANNEL_40MHZ_BMP_TCV0, + SIZE_CALIB_IQ_DCOC_40MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC_CHANNEL_80MHZ_BMP_TCV0 - + ADDR_CALIB_IQ_DCOC_CHANNEL_40MHZ_BMP_TCV1, + SIZE_CALIB_IQ_DCOC_80MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC_CHANNEL_80MHZ_BMP_TCV1 - + ADDR_CALIB_IQ_DCOC_CHANNEL_80MHZ_BMP_TCV0, + SIZE_CALIB_IQ_DCOC_80MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV0 - + ADDR_CALIB_IQ_DCOC_CHANNEL_80MHZ_BMP_TCV1, + SIZE_CALIB_IQ_DCOC_160MHZ_BMP_TCV0 = ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV1 - + ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV0, + SIZE_CALIB_IQ_DCOC_160MHZ_BMP_TCV1 = ADDR_CALIB_IQ_DCOC_DATA_20MHZ_TCV0 - + ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV1, + SIZE_CALIB_IQ_DCOC_DATA_20MHZ_TCV0 = ADDR_CALIB_IQ_DCOC_DATA_20MHZ_TCV1 - + ADDR_CALIB_IQ_DCOC_DATA_20MHZ_TCV0, + SIZE_CALIB_IQ_DCOC_DATA_20MHZ_TCV1 = ADDR_CALIB_IQ_DCOC_DATA_40MHZ_TCV0 - + ADDR_CALIB_IQ_DCOC_DATA_20MHZ_TCV1, + SIZE_CALIB_IQ_DCOC_DATA_40MHZ_TCV0 = ADDR_CALIB_IQ_DCOC_DATA_40MHZ_TCV1 - + ADDR_CALIB_IQ_DCOC_DATA_40MHZ_TCV0, + SIZE_CALIB_IQ_DCOC_DATA_40MHZ_TCV1 = ADDR_CALIB_IQ_DCOC_DATA_80MHZ_TCV0 - + ADDR_CALIB_IQ_DCOC_DATA_40MHZ_TCV1, + SIZE_CALIB_IQ_DCOC_DATA_80MHZ_TCV0 = ADDR_CALIB_IQ_DCOC_DATA_80MHZ_TCV1 - + ADDR_CALIB_IQ_DCOC_DATA_80MHZ_TCV0, + SIZE_CALIB_IQ_DCOC_DATA_80MHZ_TCV1 = ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV0 - + ADDR_CALIB_IQ_DCOC_DATA_80MHZ_TCV1, + SIZE_CALIB_IQ_DCOC_DATA_160MHZ_TCV0 = ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV1 - + ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV0, + SIZE_CALIB_IQ_DCOC_DATA_160MHZ_TCV1 = sizeof(struct eeprom_calib_data) * + ADDR_CALIB_IQ_DCOC_CHANNEL_160MHZ_BMP_TCV1, + EEPROM_BASIC_NUM_BYTES = sizeof(struct eeprom) - sizeof(struct eeprom_calib_iq_dcoc), +#else + EEPROM_BASIC_NUM_BYTES = sizeof(struct eeprom), +#endif + EEPROM_NUM_BYTES = sizeof(struct eeprom), + + EEPROM_LAST_BYTE = EEPROM_NUM_BYTES - 1, +}; + +#endif /* CL_EEPROM_H */ -- 2.36.1