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Please, take a look at the cover letter for more details). Signed-off-by: Viktor Barna --- drivers/net/wireless/celeno/cl8k/platform.h | 196 ++++++++++++++++++++ 1 file changed, 196 insertions(+) create mode 100644 drivers/net/wireless/celeno/cl8k/platform.h diff --git a/drivers/net/wireless/celeno/cl8k/platform.h b/drivers/net/wireless/celeno/cl8k/platform.h new file mode 100644 index 000000000000..d0268eded0c3 --- /dev/null +++ b/drivers/net/wireless/celeno/cl8k/platform.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* Copyright(c) 2019-2022, Celeno Communications Ltd. */ + +#ifndef CL_PLATFORM_H +#define CL_PLATFORM_H + +#define PLATFORM_DESCRIPTION_LENGTH 100 +#define PLATFORM_CUSTOMER_MASK 0xffff0000 +#define PLATFORM_BOARD_MASK 0x0000ff00 +#define PLATFORM_CHIP_MASK 0x000000f0 + +#define PLATFORM_CUSTOMER(platform) \ + u32_get_bits(platform, PLATFORM_CUSTOMER_MASK) +#define PLATFORM_BOARD(platform) \ + u32_get_bits(platform, PLATFORM_BOARD_MASK) +#define PLATFORM_CHIP(platform) \ + u32_get_bits(platform, PLATFORM_CHIP_MASK) + +#define PLATFORM_PACK_VERSION_V1 1 +#define PLATFORM_PACK_MAGIC_V1 "CL8K-AGC-PPCK" +#define PLATFORM_PACK_FILENAME_V1 "agcppk.bin" +#define PLATFORM_PACK_MAGIC_LEN 16 + +struct cl_platform_table { + u32 platform_id; + u8 platform_description[PLATFORM_DESCRIPTION_LENGTH]; + struct cl_agc_profile_per_bw *agc_profile[TCV_MAX]; + struct cl_agc_profile_per_bw *agc_profile_elastic[TCV_MAX]; + struct cl_agc_profile_per_bw *agc_profile_sensing; + const u8 *power_conv_table_2; + const u8 *power_conv_table_5; + const u8 *power_conv_table_6; +}; + +enum cl_agc_pack_type { + CL_AGC_PACK_UNDEFINED, + CL_AGC_PACK_PLATFORM_BINDING, + CL_AGC_PACK_PROFILE, + CL_AGC_PACK_POWER_TABLE, + CL_AGC_PACK_EOF, + + CL_AGC_PACK_MAX +}; + +enum cl_agc_profile_type { + CL_AGC_PROFILE_UNDEFINED, + CL_AGC_PROFILE_FIRST, + CL_AGC_PROFILE_2_1_9 = CL_AGC_PROFILE_FIRST, + CL_AGC_PROFILE_5_1_9, + CL_AGC_PROFILE_6_1_3, + CL_AGC_PROFILE_50_0_1, + CL_AGC_PROFILE_60_1_3, + + CL_AGC_PROFILE_MAX +}; + +enum cl_power_table_type { + CL_POWER_TO_POWERWORD_CONV_TABLE_UNDEFINED, + CL_POWER_TO_POWERWORD_CONV_TABLE_FIRST, + CL_POWER_TO_POWERWORD_CONV_TABLE_COMMON_ID_0 = CL_POWER_TO_POWERWORD_CONV_TABLE_FIRST, + CL_POWER_TO_POWERWORD_CONV_TABLE_COMMON_ID_1, + CL_POWER_TO_POWERWORD_CONV_TABLE_COMMON_ID_2, + CL_POWER_TO_POWERWORD_CONV_TABLE_ATHOS_B_ID_0, + CL_POWER_TO_POWERWORD_CONV_TABLE_ATHOS_B_ID_1, + + CL_POWER_TO_POWERWORD_CONV_TABLE_MAX +}; + +struct cl_agc_platform_pack { + char magic[PLATFORM_PACK_MAGIC_LEN]; + __le32 version; + u8 reserved[249]; + u8 data[]; +} __packed; + +struct cl_agc_tilv { + u8 t; + u8 i; + u32 l; + u8 v[]; +} __packed; + +struct cl_platform_binding { + u32 platform_id; + u8 platform_description[PLATFORM_DESCRIPTION_LENGTH]; + u8 agc_profile[TCV_MAX]; + u8 agc_profile_elastic[TCV_MAX]; + u8 agc_profile_sensing; + u8 power_conv_table_2; + u8 power_conv_table_5; + u8 power_conv_table_6; +} __packed; + +struct cl_platform { + struct cl_agc_platform_pack *app; + ssize_t app_size; + struct cl_platform_table table; + u8 idx; +}; + +struct cl_platform_table *cl_platform_get_active_table(struct cl_chip *chip, + u8 idx); +int cl_platform_get_tables_cnt(struct cl_chip *chip); +int cl_platform_unpack_v1(struct cl_platform_table *table, + struct cl_agc_platform_pack *app, + ssize_t buf_len, u8 platform_idx); +int cl_platform_alloc(struct cl_chip *chip); +void cl_platform_dealloc(struct cl_chip *chip); + +/** + * AGC (=Automatic Gain Control) + */ + +struct cl_agc_reg { + u32 val; + u32 mask; +}; + +struct cl_agc_regs { + struct cl_agc_reg fsm_preset_p2; /* 0x244 */ + struct cl_agc_reg lna_thr_set0_ref2; /* 0x25C */ + struct cl_agc_reg lna_thr_set0_ref3; /* 0x260 */ + struct cl_agc_reg lna_thr_set1_ref2; /* 0x264 */ + struct cl_agc_reg lna_thr_set1_ref3; /* 0x268 */ + struct cl_agc_reg lna_thr_set2_ref2; /* 0x26C */ + struct cl_agc_reg lna_thr_set2_ref3; /* 0x270 */ + struct cl_agc_reg lna_gain_set0_ref2; /* 0x274 */ + struct cl_agc_reg lna_gain_set0_ref3; /* 0x278 */ + struct cl_agc_reg lna_nf_set0_ref2; /* 0x27C */ + struct cl_agc_reg lna_nf_set0_ref3; /* 0x280 */ + struct cl_agc_reg lna_icp1_set0_ref2; /* 0x284 */ + struct cl_agc_reg lna_icp1_set0_ref3; /* 0x288 */ + struct cl_agc_reg fsm_preset_p10; /* 0x2A8 */ + struct cl_agc_reg fsm_preset_p11; /* 0x2AC */ + struct cl_agc_reg fsm_preset_p12; /* 0x2B0 */ + struct cl_agc_reg ant_loss; /* 0x300 */ + struct cl_agc_reg gain_range; /* 0x304 */ + struct cl_agc_reg vga_ref0; /* 0x308 */ + struct cl_agc_reg lna_gain_set0_ref0; /* 0x30C */ + struct cl_agc_reg lna_gain_set0_ref1; /* 0x310 */ + struct cl_agc_reg lna_thr_set0_ref0; /* 0x314 */ + struct cl_agc_reg lna_thr_set0_ref1; /* 0x318 */ + struct cl_agc_reg lna_thr_set1_ref0; /* 0x31C */ + struct cl_agc_reg lna_thr_set1_ref1; /* 0x320 */ + struct cl_agc_reg lna_thr_set2_ref0; /* 0x324 */ + struct cl_agc_reg lna_thr_set2_ref1; /* 0x328 */ + struct cl_agc_reg lna_nf_set0_ref0; /* 0x32C */ + struct cl_agc_reg lna_nf_set0_ref1; /* 0x330 */ + struct cl_agc_reg lna_icp1_set0_ref0; /* 0x334 */ + struct cl_agc_reg lna_icp1_set0_ref1; /* 0x338 */ + struct cl_agc_reg saturation; /* 0x364 */ + struct cl_agc_reg ramp; /* 0x36C */ + struct cl_agc_reg dsp0; /* 0x394 */ + struct cl_agc_reg dsp1; /* 0x398 */ + struct cl_agc_reg dsp2; /* 0x39C */ + struct cl_agc_reg dsp3; /* 0x3A0 */ + struct cl_agc_reg lna_gain_set1_ref0; /* 0x590 */ + struct cl_agc_reg lna_gain_set1_ref1; /* 0x594 */ + struct cl_agc_reg lna_gain_set1_ref2; /* 0x598 */ + struct cl_agc_reg lna_gain_set1_ref3; /* 0x59c */ + struct cl_agc_reg lna_nf_set1_ref0; /* 0x5A0 */ + struct cl_agc_reg lna_nf_set1_ref1; /* 0x5A4 */ + struct cl_agc_reg lna_nf_set1_ref2; /* 0x5A8 */ + struct cl_agc_reg lna_nf_set1_ref3 ; /* 0x5AC */ + struct cl_agc_reg lna_icp1_set1_ref0; /* 0x5B0 */ + struct cl_agc_reg lna_icp1_set1_ref1; /* 0x5B4 */ + struct cl_agc_reg lna_icp1_set1_ref2; /* 0x5B8 */ + struct cl_agc_reg lna_icp1_set1_ref3 ;/* 0x5BC */ +}; + +struct cl_agc_profile_per_bw { + u32 id; + struct cl_agc_regs regs[CHNL_BW_MAX]; +}; + +struct cl_agc_profile { + u32 id; + struct cl_agc_regs regs; +}; + +struct cl_agc_params { + u8 num_profiles; + u8 ant_mask1; + u8 ant_mask2; + struct cl_agc_profile profile1; + struct cl_agc_profile profile2; +}; + +struct cl_chip; + +int cl_agc_params_read_platform_id(struct cl_chip *chip); +int cl_agc_params_fill(struct cl_hw *cl_hw, struct cl_agc_params *agc_params); +void cl_agc_params_dump_profile_id(char *buf, ssize_t buf_size, ssize_t *len, + u32 id, const char *str); + +#endif /* CL_PLATFORM_H */ -- 2.36.1