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From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Jamin Lin" <jamin_lin@aspeedtech.com>,
	"Cédric Le Goater" <clg@kaod.org>
Subject: [PULL 12/15] hw/gpio: Add ASPEED GPIO model for AST1030
Date: Wed, 25 May 2022 18:01:33 +0200	[thread overview]
Message-ID: <20220525160136.556277-13-clg@kaod.org> (raw)
In-Reply-To: <20220525160136.556277-1-clg@kaod.org>

From: Jamin Lin <jamin_lin@aspeedtech.com>

AST1030 integrates one set of Parallel GPIO Controller
with maximum 151 control pins, which are 21 groups
(A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4
S5 S6 S7 ) and the group T and U are input only.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/arm/aspeed_ast10x0.c | 11 +++++++++++
 hw/gpio/aspeed_gpio.c   | 27 +++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)

diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 938615d55f4a..d53454168403 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -136,6 +136,9 @@ static void aspeed_soc_ast1030_init(Object *obj)
         snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
         object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
     }
+
+    snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
+    object_initialize_child(obj, "gpio", &s->gpio, typename);
 }
 
 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
@@ -281,6 +284,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
                         sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
     }
+
+    /* GPIO */
+    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
+        return;
+    }
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
+                       aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
 }
 
 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 4620ea8e8b83..5138fe812b9e 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -819,6 +819,15 @@ static GPIOSetProperties ast2600_1_8v_set_props[ASPEED_GPIO_MAX_NR_SETS] = {
     [1] = {0x0000000f,  0x0000000f,  {"18E"} },
 };
 
+static GPIOSetProperties ast1030_set_props[ASPEED_GPIO_MAX_NR_SETS] = {
+    [0] = {0xffffffff,  0xffffffff,  {"A", "B", "C", "D"} },
+    [1] = {0xffffffff,  0xffffffff,  {"E", "F", "G", "H"} },
+    [2] = {0xffffffff,  0xffffffff,  {"I", "J", "K", "L"} },
+    [3] = {0xffffff3f,  0xffffff3f,  {"M", "N", "O", "P"} },
+    [4] = {0xff060c1f,  0x00060c1f,  {"Q", "R", "S", "T"} },
+    [5] = {0x000000ff,  0x00000000,  {"U"} },
+};
+
 static const MemoryRegionOps aspeed_gpio_ops = {
     .read       = aspeed_gpio_read,
     .write      = aspeed_gpio_write,
@@ -971,6 +980,16 @@ static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data)
     agc->reg_table = aspeed_1_8v_gpios;
 }
 
+static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data)
+{
+    AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass);
+
+    agc->props = ast1030_set_props;
+    agc->nr_gpio_pins = 151;
+    agc->nr_gpio_sets = 6;
+    agc->reg_table = aspeed_3_3v_gpios;
+}
+
 static const TypeInfo aspeed_gpio_info = {
     .name           = TYPE_ASPEED_GPIO,
     .parent         = TYPE_SYS_BUS_DEVICE,
@@ -1008,6 +1027,13 @@ static const TypeInfo aspeed_gpio_ast2600_1_8v_info = {
     .instance_init  = aspeed_gpio_init,
 };
 
+static const TypeInfo aspeed_gpio_ast1030_info = {
+    .name           = TYPE_ASPEED_GPIO "-ast1030",
+    .parent         = TYPE_ASPEED_GPIO,
+    .class_init     = aspeed_gpio_1030_class_init,
+    .instance_init  = aspeed_gpio_init,
+};
+
 static void aspeed_gpio_register_types(void)
 {
     type_register_static(&aspeed_gpio_info);
@@ -1015,6 +1041,7 @@ static void aspeed_gpio_register_types(void)
     type_register_static(&aspeed_gpio_ast2500_info);
     type_register_static(&aspeed_gpio_ast2600_3_3v_info);
     type_register_static(&aspeed_gpio_ast2600_1_8v_info);
+    type_register_static(&aspeed_gpio_ast1030_info);
 }
 
 type_init(aspeed_gpio_register_types);
-- 
2.35.3



  parent reply	other threads:[~2022-05-25 16:19 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-25 16:01 [PULL 00/15] aspeed queue Cédric Le Goater
2022-05-25 16:01 ` [PULL 01/15] docs: add minibmc section in aspeed document Cédric Le Goater
2022-05-25 16:01 ` [PULL 02/15] hw/arm/aspeed: Add fby35 machine type Cédric Le Goater
2022-05-25 16:01 ` [PULL 03/15] docs: aspeed: Add fby35 board Cédric Le Goater
2022-05-25 16:01 ` [PULL 04/15] hw: m25p80: allow write_enable latch get/set Cédric Le Goater
2022-05-25 16:01 ` [PULL 05/15] aspeed: Introduce a get_irq AspeedSoCClass method Cédric Le Goater
2022-05-25 16:01 ` [PULL 06/15] hw: aspeed: Add missing UART's Cédric Le Goater
2022-05-25 16:01 ` [PULL 07/15] hw: aspeed: Add uarts_num SoC attribute Cédric Le Goater
2022-05-25 16:01 ` [PULL 08/15] hw: aspeed: Ensure AST1030 respects uart-default Cédric Le Goater
2022-05-25 16:01 ` [PULL 09/15] hw: aspeed: Introduce common UART init function Cédric Le Goater
2022-05-25 16:01 ` [PULL 10/15] hw: aspeed: Init all UART's with serial devices Cédric Le Goater
2022-05-25 16:01 ` [PULL 11/15] hw/gpio Add GPIO read/write trace event Cédric Le Goater
2022-05-25 16:01 ` Cédric Le Goater [this message]
2022-05-25 16:01 ` [PULL 13/15] hw/gpio support GPIO index mode for write operation Cédric Le Goater
2022-05-25 16:01 ` [PULL 14/15] hw/gpio: replace HWADDR_PRIx with PRIx64 Cédric Le Goater
2022-05-25 16:01 ` [PULL 15/15] hw/arm/aspeed: Add i2c devices for AST2600 EVB Cédric Le Goater
2022-05-25 20:44 ` [PULL 00/15] aspeed queue Richard Henderson

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