From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com,
peter.maydell@linaro.org, richard.henderson@linaro.org,
"Víctor Colombo" <victor.colombo@eldorado.org.br>,
"Rashmica Gupta" <rashmica.g@gmail.com>
Subject: [PULL 09/34] target/ppc: Rename sfprf to sfifprf where it's also used as set fi flag
Date: Thu, 26 May 2022 18:37:50 -0300 [thread overview]
Message-ID: <20220526213815.92701-10-danielhb413@gmail.com> (raw)
In-Reply-To: <20220526213815.92701-1-danielhb413@gmail.com>
From: Víctor Colombo <victor.colombo@eldorado.org.br>
The bit FI fix used the sfprf flag as a flag for the set_fi parameter
in do_float_check_status where applicable. Now, this patch rename this
flag to sfifprf to state this dual usage.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com>
Message-Id: <20220517161522.36132-4-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/fpu_helper.c | 112 ++++++++++++++++++++--------------------
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 88f9e756a5..8592727792 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1693,9 +1693,9 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
* nels - number of elements (1, 2 or 4)
* tp - type (float32 or float64)
* fld - vsr_t field (VsrD(*) or VsrW(*))
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
+#define VSX_ADD_SUB(name, op, nels, tp, fld, sfifprf, r2sp) \
void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
@@ -1712,19 +1712,19 @@ void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
float_invalid_op_addsub(env, tstat.float_exception_flags, \
- sfprf, GETPC()); \
+ sfifprf, GETPC()); \
} \
\
if (r2sp) { \
t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
@@ -1769,9 +1769,9 @@ void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
* nels - number of elements (1, 2 or 4)
* tp - type (float32 or float64)
* fld - vsr_t field (VsrD(*) or VsrW(*))
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
+#define VSX_MUL(op, nels, tp, fld, sfifprf, r2sp) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
@@ -1788,20 +1788,20 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
float_invalid_op_mul(env, tstat.float_exception_flags, \
- sfprf, GETPC()); \
+ sfifprf, GETPC()); \
} \
\
if (r2sp) { \
t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
@@ -1840,9 +1840,9 @@ void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
* nels - number of elements (1, 2 or 4)
* tp - type (float32 or float64)
* fld - vsr_t field (VsrD(*) or VsrW(*))
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
+#define VSX_DIV(op, nels, tp, fld, sfifprf, r2sp) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
@@ -1859,7 +1859,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
float_invalid_op_div(env, tstat.float_exception_flags, \
- sfprf, GETPC()); \
+ sfifprf, GETPC()); \
} \
if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
float_zero_divide_excp(env, GETPC()); \
@@ -1869,13 +1869,13 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
@@ -1917,9 +1917,9 @@ void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
* nels - number of elements (1, 2 or 4)
* tp - type (float32 or float64)
* fld - vsr_t field (VsrD(*) or VsrW(*))
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
+#define VSX_RE(op, nels, tp, fld, sfifprf, r2sp) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -1937,13 +1937,13 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
@@ -1957,9 +1957,9 @@ VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
* nels - number of elements (1, 2 or 4)
* tp - type (float32 or float64)
* fld - vsr_t field (VsrD(*) or VsrW(*))
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
+#define VSX_SQRT(op, nels, tp, fld, sfifprf, r2sp) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -1975,20 +1975,20 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
float_invalid_op_sqrt(env, tstat.float_exception_flags, \
- sfprf, GETPC()); \
+ sfifprf, GETPC()); \
} \
\
if (r2sp) { \
t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
@@ -2002,9 +2002,9 @@ VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
* nels - number of elements (1, 2 or 4)
* tp - type (float32 or float64)
* fld - vsr_t field (VsrD(*) or VsrW(*))
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
+#define VSX_RSQRTE(op, nels, tp, fld, sfifprf, r2sp) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -2020,19 +2020,19 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
float_invalid_op_sqrt(env, tstat.float_exception_flags, \
- sfprf, GETPC()); \
+ sfifprf, GETPC()); \
} \
if (r2sp) { \
t.fld = do_frsp(env, t.fld, GETPC()); \
} \
\
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
@@ -2158,9 +2158,9 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
* fld - vsr_t field (VsrD(*) or VsrW(*))
* maddflgs - flags for the float*muladd routine that control the
* various forms (madd, msub, nmadd, nmsub)
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf) \
+#define VSX_MADD(op, nels, tp, fld, maddflgs, sfifprf) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
ppc_vsr_t *s1, ppc_vsr_t *s2, ppc_vsr_t *s3) \
{ \
@@ -2177,15 +2177,15 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
\
if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
float_invalid_op_madd(env, tstat.float_exception_flags, \
- sfprf, GETPC()); \
+ sfifprf, GETPC()); \
} \
\
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, 1)
@@ -2670,9 +2670,9 @@ VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
* ttp - target type (float32 or float64)
* sfld - source vsr_t field
* tfld - target vsr_t field (f32 or f64)
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
+#define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfifprf) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -2685,19 +2685,19 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
float_invalid_op_vxsnan(env, GETPC()); \
t.tfld = ttp##_snan_to_qnan(t.tfld); \
} \
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_##ttp(env, t.tfld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
-#define VSX_CVT_FP_TO_FP2(op, nels, stp, ttp, sfprf) \
+#define VSX_CVT_FP_TO_FP2(op, nels, stp, ttp, sfifprf) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -2710,14 +2710,14 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
float_invalid_op_vxsnan(env, GETPC()); \
t.VsrW(2 * i) = ttp##_snan_to_qnan(t.VsrW(2 * i)); \
} \
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_##ttp(env, t.VsrW(2 * i)); \
} \
t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_CVT_FP_TO_FP2(xvcvdpsp, 2, float64, float32, 0)
@@ -2733,9 +2733,9 @@ VSX_CVT_FP_TO_FP2(xscvdpsp, 1, float64, float32, 1)
* tfld - target vsr_t field (f32 or f64)
* sfprf - set FPRF
*/
-#define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
-void helper_##op(CPUPPCState *env, uint32_t opcode, \
- ppc_vsr_t *xt, ppc_vsr_t *xb) \
+#define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode, \
+ ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = *xt; \
int i; \
@@ -2767,9 +2767,9 @@ VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
* ttp - target type
* sfld - source vsr_t field
* tfld - target vsr_t field
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
+#define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfifprf) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -2782,13 +2782,13 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
float_invalid_op_vxsnan(env, GETPC()); \
t.tfld = ttp##_snan_to_qnan(t.tfld); \
} \
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_##ttp(env, t.tfld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
@@ -3035,9 +3035,9 @@ VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
* sfld - source vsr_t field
* tfld - target vsr_t field
* jdef - definition of the j index (i or 2*i)
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
+#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfifprf, r2sp)\
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -3048,13 +3048,13 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
if (r2sp) { \
t.tfld = do_frsp(env, t.tfld, GETPC()); \
} \
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.tfld); \
} \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
@@ -3136,9 +3136,9 @@ VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
* tp - type (float32 or float64)
* fld - vsr_t field (VsrD(*) or VsrW(*))
* rmode - rounding mode
- * sfprf - set FPRF
+ * sfifprf - set FI and FPRF
*/
-#define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
+#define VSX_ROUND(op, nels, tp, fld, rmode, sfifprf) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
@@ -3158,7 +3158,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
} else { \
t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
} \
- if (sfprf) { \
+ if (sfifprf) { \
helper_compute_fprf_float64(env, t.fld); \
} \
} \
@@ -3174,7 +3174,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
} \
\
*xt = t; \
- do_float_check_status(env, sfprf, GETPC()); \
+ do_float_check_status(env, sfifprf, GETPC()); \
}
VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
--
2.36.1
next prev parent reply other threads:[~2022-05-26 21:45 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-26 21:37 [PULL 00/34] ppc queue Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 01/34] pseries: allow setting stdout-path even on machines with a VGA Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 02/34] hw/ppc/e500: Remove unused BINARY_DEVICE_TREE_FILE Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 03/34] spapr: Use address from elf parser for kernel address Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 04/34] spapr/docs: Add a few words about x-vof Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 05/34] mos6522: fix linking error when CONFIG_MOS6522 is not set Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 06/34] target/ppc: Fix tlbie Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 07/34] target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 08/34] target/ppc: Fix FPSCR.FI changing in float_overflow_excp() Daniel Henrique Barboza
2022-05-26 21:37 ` Daniel Henrique Barboza [this message]
2022-05-26 21:37 ` [PULL 10/34] pnv/xive2: Don't overwrite PC registers when writing TCTXT registers Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 11/34] target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWG Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 12/34] target/ppc: use TCG_CALL_NO_RWG in vector helpers without env Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 13/34] target/ppc: use TCG_CALL_NO_RWG in BCD helpers Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 14/34] target/ppc: use TCG_CALL_NO_RWG in VSX helpers without env Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 15/34] target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 16/34] target/ppc: declare xscvspdpn helper with call flags Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 17/34] target/ppc: declare xvxsigsp " Daniel Henrique Barboza
2022-05-26 21:37 ` [PULL 18/34] target/ppc: declare xxextractuw and xxinsertw helpers " Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 19/34] target/ppc: introduce do_va_helper Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 20/34] target/ppc: declare vmsum[um]bm helpers with call flags Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 21/34] target/ppc: declare vmsumuh[ms] helper " Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 22/34] target/ppc: declare vmsumsh[ms] " Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 23/34] target/ppc: Fix eieio memory ordering semantics Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 24/34] tcg/ppc: ST_ST memory ordering is not provided with eieio Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 25/34] tcg/ppc: Optimize memory ordering generation with lwsync Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 26/34] target/ppc: Implement lwsync with weaker memory ordering Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 27/34] target/ppc: Implement xxm[tf]acc and xxsetaccz Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 28/34] target/ppc: Implemented xvi*ger* instructions Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 29/34] target/ppc: Implemented pmxvi*ger* instructions Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 30/34] target/ppc: Implemented xvf*ger* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 31/34] target/ppc: Implemented xvf16ger* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 32/34] target/ppc: Implemented pmxvf*ger* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 33/34] target/ppc: Implemented [pm]xvbf16ger2* Daniel Henrique Barboza
2022-05-26 21:38 ` [PULL 34/34] linux-user: Add PowerPC ISA 3.1 and MMA to hwcap Daniel Henrique Barboza
2022-05-27 15:19 ` [PULL 00/34] ppc queue Richard Henderson
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