From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 81927C433F5 for ; Mon, 30 May 2022 15:06:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 893DD10EE1C; Mon, 30 May 2022 15:06:12 +0000 (UTC) Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4268710EE02 for ; Mon, 30 May 2022 15:06:11 +0000 (UTC) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nvgy4-0005Kn-Bi; Mon, 30 May 2022 17:06:04 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nvgy4-005THz-2i; Mon, 30 May 2022 17:06:02 +0200 Received: from mfe by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nvgy1-005Bdw-Cg; Mon, 30 May 2022 17:06:01 +0200 From: Marco Felsch To: robert.foss@linaro.org, laurent.pinchart@ideasonboard.com, jernej.skrabec@gmail.com, jonas@kwiboo.se, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sam@ravnborg.org, maxime@cerno.tech Subject: [PATCH 1/6] drm/bridge: ti-sn65dsi83: make lvds lane register setup more readable Date: Mon, 30 May 2022 17:05:44 +0200 Message-Id: <20220530150548.1236307-2-m.felsch@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220530150548.1236307-1-m.felsch@pengutronix.de> References: <20220530150548.1236307-1-m.felsch@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, kernel@pengutronix.de, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" No functional change. Just reuse the already existing val variable to setup the register. This is in preparation for adding the new feature to reverse the CHA/CHB lane orders. Without this change this call gets very unreadable. Signed-off-by: Marco Felsch --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index 2831f0813c3a..112fea004c8e 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -437,11 +437,12 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, regmap_write(ctx->regmap, REG_LVDS_FMT, val); regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); - regmap_write(ctx->regmap, REG_LVDS_LANE, - (ctx->lvds_dual_link_even_odd_swap ? - REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | - REG_LVDS_LANE_CHA_LVDS_TERM | - REG_LVDS_LANE_CHB_LVDS_TERM); + + val = REG_LVDS_LANE_CHA_LVDS_TERM | REG_LVDS_LANE_CHB_LVDS_TERM; + if (ctx->lvds_dual_link_even_odd_swap) + val |= REG_LVDS_LANE_EVEN_ODD_SWAP; + + regmap_write(ctx->regmap, REG_LVDS_LANE, val); regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); le16val = cpu_to_le16(mode->hdisplay); -- 2.30.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72B7DC4332F for ; Mon, 30 May 2022 15:49:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240019AbiE3PtN (ORCPT ); Mon, 30 May 2022 11:49:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238400AbiE3Psu (ORCPT ); Mon, 30 May 2022 11:48:50 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5C78CE5ED for ; Mon, 30 May 2022 08:06:12 -0700 (PDT) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nvgy4-0005Kn-Bi; Mon, 30 May 2022 17:06:04 +0200 Received: from [2a0a:edc0:0:1101:1d::28] (helo=dude02.red.stw.pengutronix.de) by drehscheibe.grey.stw.pengutronix.de with esmtp (Exim 4.94.2) (envelope-from ) id 1nvgy4-005THz-2i; Mon, 30 May 2022 17:06:02 +0200 Received: from mfe by dude02.red.stw.pengutronix.de with local (Exim 4.94.2) (envelope-from ) id 1nvgy1-005Bdw-Cg; Mon, 30 May 2022 17:06:01 +0200 From: Marco Felsch To: robert.foss@linaro.org, laurent.pinchart@ideasonboard.com, jernej.skrabec@gmail.com, jonas@kwiboo.se, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, sam@ravnborg.org, maxime@cerno.tech Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, kernel@pengutronix.de Subject: [PATCH 1/6] drm/bridge: ti-sn65dsi83: make lvds lane register setup more readable Date: Mon, 30 May 2022 17:05:44 +0200 Message-Id: <20220530150548.1236307-2-m.felsch@pengutronix.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220530150548.1236307-1-m.felsch@pengutronix.de> References: <20220530150548.1236307-1-m.felsch@pengutronix.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: mfe@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: devicetree@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Just reuse the already existing val variable to setup the register. This is in preparation for adding the new feature to reverse the CHA/CHB lane orders. Without this change this call gets very unreadable. Signed-off-by: Marco Felsch --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c index 2831f0813c3a..112fea004c8e 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -437,11 +437,12 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, regmap_write(ctx->regmap, REG_LVDS_FMT, val); regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05); - regmap_write(ctx->regmap, REG_LVDS_LANE, - (ctx->lvds_dual_link_even_odd_swap ? - REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | - REG_LVDS_LANE_CHA_LVDS_TERM | - REG_LVDS_LANE_CHB_LVDS_TERM); + + val = REG_LVDS_LANE_CHA_LVDS_TERM | REG_LVDS_LANE_CHB_LVDS_TERM; + if (ctx->lvds_dual_link_even_odd_swap) + val |= REG_LVDS_LANE_EVEN_ODD_SWAP; + + regmap_write(ctx->regmap, REG_LVDS_LANE, val); regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); le16val = cpu_to_le16(mode->hdisplay); -- 2.30.2