From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B670C433F5 for ; Tue, 31 May 2022 10:59:23 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8971983DD4; Tue, 31 May 2022 12:59:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="cdMg02ek"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 98D3683E3C; Tue, 31 May 2022 12:59:20 +0200 (CEST) Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CB23083B15 for ; Tue, 31 May 2022 12:59:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=p.yadav@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 24VAxAdH131000; Tue, 31 May 2022 05:59:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1653994750; bh=4LtqnD1b2hSP82AEX6u59+4z3Say7dIU8uSJX2SqQJY=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=cdMg02ekPz/ekZ6GiLlnUHPLnGumo9FHRjonolIGUuA5uDpaCTiwdoiDRg/sykOEY gaNo30M8J0OwIzvOhkUXL9iiQZzPkrhKSpTdnGl2q8ZXGS5DCcEtChr1Z6otMgVk0I BjW9poH7K9zIUSymt1Gg9Pb+s00/SSNTHkLmsF7s= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 24VAxAkJ010767 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 31 May 2022 05:59:10 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Tue, 31 May 2022 05:59:09 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Tue, 31 May 2022 05:59:10 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 24VAx9tq020778; Tue, 31 May 2022 05:59:09 -0500 Date: Tue, 31 May 2022 16:29:08 +0530 From: Pratyush Yadav To: Vaishnav Achath CC: , , , , , , , , , , , , , , Subject: Re: [PATCH v2 2/2] arm: k3: j721e: add dynamic sf bus override support for j721e Message-ID: <20220531105908.x3ltmcb6ipcppwhq@ti.com> References: <20220511060352.28140-1-vaishnav.a@ti.com> <20220511060352.28140-3-vaishnav.a@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20220511060352.28140-3-vaishnav.a@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi Vaishnav, On 11/05/22 11:33AM, Vaishnav Achath wrote: > implement overrides for spl_spi_boot_bus() and spl_spi_boot_cs() > lookup functions according to bootmode selection, so as to support > both QSPI and OSPI boot using the same build. > > Signed-off-by: Vaishnav Achath > --- > arch/arm/mach-k3/j721e_init.c | 17 +++++++++++++++++ > arch/arm/mach-k3/sysfw-loader.c | 4 ++-- > 2 files changed, 19 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c > index f503f15f19..82391b5cf8 100644 > --- a/arch/arm/mach-k3/j721e_init.c > +++ b/arch/arm/mach-k3/j721e_init.c > @@ -355,6 +355,23 @@ static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) > return bootmode; > } > > +u32 spl_spi_boot_bus(void) > +{ > + u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); > + u32 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); > + u32 bootmode = ((wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> > + WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT) | > + ((main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << BOOT_MODE_B_SHIFT); > + > + return (bootmode == BOOT_DEVICE_QSPI) ? 1 : 0; > +} > + > +/* both OSPI and QSPI flash are in CS0 */ > +u32 spl_spi_boot_cs(void) > +{ > + return 0; > +} > + I don't think we need to hard-code the chip select here. Let that come from the config. Other than this, Reviewed-by: Pratyush Yadav > u32 spl_boot_device(void) > { > u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); > diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c > index 5e48c36ccd..8ff36759c1 100644 > --- a/arch/arm/mach-k3/sysfw-loader.c > +++ b/arch/arm/mach-k3/sysfw-loader.c > @@ -324,9 +324,9 @@ static void *k3_sysfw_get_spi_addr(void) > struct udevice *dev; > fdt_addr_t addr; > int ret; > + unsigned int sf_bus = spl_spi_boot_bus(); > > - ret = uclass_find_device_by_seq(UCLASS_SPI, CONFIG_SF_DEFAULT_BUS, > - &dev); > + ret = uclass_find_device_by_seq(UCLASS_SPI, sf_bus, &dev); > if (ret) > return NULL; > > -- > 2.17.1 > -- Regards, Pratyush Yadav Texas Instruments Inc.