From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Atish Patra <atishp@rivosinc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org
Subject: [PATCH v5 0/3] Implement Sstc extension
Date: Tue, 31 May 2022 11:03:18 -0700 [thread overview]
Message-ID: <20220531180321.34942-1-atishp@rivosinc.com> (raw)
This series implements Sstc extension[1] which was ratified recently.
The first patch is a prepartory patches while PATCH 2 adds stimecmp
support while PATCH 3 adds vstimecmp support. This series is based on
on top of upstream commit (faee5441a038).
The series can also be found at
https://github.com/atishp04/qemu/tree/sstc_v5
It is tested on RV32 & RV64 with latest OpenSBI & Linux kernel[2]
patches. It does require the mcountinhibit support patch from PMU series[3]
or dummy one from Anup's series [4]. Otherwise, OpenSBI doesn't detect v1.12
priv version.
Changes from v4->v5:
1. Removed any ordering related flags and emulate the hardware more
closely.
Changes from v3->v4:
1. Added [v]stimecmp_wr_done to the corresponding vmstate strucuture.
Changes from v2->v3:
1. Dropped generic migration code improvement patches.
2. Removed the order constraints while updating stimecmp/vstimecmp.
Changes from v1->v2:
1. Rebased on the latest upstream commit.
2. Replaced PATCH 1 with another patch where mtimer/timecmp is
moved from CPU to ACLINT.
3. Added ACLINT migration support.
[1] https://drive.google.com/file/d/1m84Re2yK8m_vbW7TspvevCDR82MOBaSX/view
[2] https://github.com/atishp04/linux/tree/sstc_v4
[3] https://github.com/atishp04/qemu/tree/riscv_pmu_v7
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg885157.html
Atish Patra (3):
hw/intc: Move mtimer/mtimecmp to aclint
target/riscv: Add stimecmp support
target/riscv: Add vstimecmp support
hw/intc/riscv_aclint.c | 41 +++++---
hw/timer/ibex_timer.c | 18 ++--
include/hw/intc/riscv_aclint.h | 2 +
include/hw/timer/ibex_timer.h | 2 +
target/riscv/cpu.c | 8 ++
target/riscv/cpu.h | 11 +-
target/riscv/cpu_bits.h | 8 ++
target/riscv/cpu_helper.c | 11 +-
target/riscv/csr.c | 177 +++++++++++++++++++++++++++++++++
target/riscv/machine.c | 7 +-
target/riscv/meson.build | 3 +-
target/riscv/time_helper.c | 114 +++++++++++++++++++++
target/riscv/time_helper.h | 30 ++++++
13 files changed, 400 insertions(+), 32 deletions(-)
create mode 100644 target/riscv/time_helper.c
create mode 100644 target/riscv/time_helper.h
--
2.25.1
next reply other threads:[~2022-05-31 18:16 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-31 18:03 Atish Patra [this message]
2022-05-31 18:03 ` [PATCH v5 1/3] hw/intc: Move mtimer/mtimecmp to aclint Atish Patra
2022-05-31 18:03 ` [PATCH v5 2/3] target/riscv: Add stimecmp support Atish Patra
2022-06-02 6:57 ` Alistair Francis
2022-06-05 16:23 ` Atish Patra
2022-06-08 7:18 ` Alistair Francis
2022-06-15 18:21 ` Atish Kumar Patra
2022-06-16 2:37 ` Alistair Francis
2022-06-16 3:25 ` Anup Patel
2022-07-20 19:31 ` Atish Patra
2022-07-21 0:04 ` Alistair Francis
2022-05-31 18:03 ` [PATCH v5 3/3] target/riscv: Add vstimecmp support Atish Patra
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