From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 17040C433F5 for ; Tue, 31 May 2022 18:17:21 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C54FE842DC; Tue, 31 May 2022 20:15:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PyotaMQ9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id F15FF8421F; Tue, 31 May 2022 20:15:28 +0200 (CEST) Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4112984280 for ; Tue, 31 May 2022 20:15:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ovpanait@gmail.com Received: by mail-wr1-x435.google.com with SMTP id t13so19760427wrg.9 for ; Tue, 31 May 2022 11:15:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U9HvhDQrDqXcWa7YTPGl10Eafd/uW+ZMPgHFsdjtx/w=; b=PyotaMQ9H3x4cwb7e6sb+P91RRLS7egyuQueWpL0piTX8ycGb76CnYSpGVSHp9d3M5 DQgZrVviIpLC5+l96i8PZL0mW004OcYEwFnPs8tYINTppzzx7Pl4wRZXz+KQeYPnXzai MdMZ2bOjoXiutmgBK/9UP4kCgjvq+U0eFGr+5MZh940lMxweUW2uJeCrXE4GH2X+IWKd 1j+rpmpwJZ0EScY5X+2huyrAdFlSpAEE/zFBaU1IU7MN4o8mUv5HvTRZEU5PfEWSAu60 vNGo4tuNqEwEGBazEuABKAdLw9bUIhy1yfbj6taaUFJbbt8ob0e9PlR7AVl+VSMFRJ8k UkqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U9HvhDQrDqXcWa7YTPGl10Eafd/uW+ZMPgHFsdjtx/w=; b=4Yl4RnAbR14DIUatXXp/UZFB1jiXP2rLoZD/B1fm+mhQeTcl84+WfB5lqy8COa8a+X h5Vn8DL/Q0ZcYXX9MHxn7k5IVduipfYfLUN1PYynRr3ry1pb8tjQQTAKV0pRoXk1P3qD ET4XUpW6siJeCbhx+MAnmMkotUQzA9/XjraIe1fPyzhp4FqnChTEkqVoGHaV1QzEkO9j xoMsepjjLIlTJUfirepvT1aU6zNhQ7KrSdSFtG7e4mIsquUqviMy7SVG0pe3M86NaYrq 8bIHsVtszN/pl17mycQiX0q8C8OquoGv8iQdDxnWjvFvooRemrxfIZZ2o7Rwv7fFwygm wczg== X-Gm-Message-State: AOAM530cG2PC9+9Pqh5DC94/l30xyvYsDi/CioiBQlgaU9dukg7STVl3 Xq0x3YEVhsCofHSypmYy4hUeqZz0J7g= X-Google-Smtp-Source: ABdhPJwMQbMkd/QSFh24EWeAPH2IX6jwftbyPy1X6KMjNkZYbvGoZuHg8MUg0L8Q3fsTUKgIaiERPw== X-Received: by 2002:a05:6000:228:b0:210:3433:64d1 with SMTP id l8-20020a056000022800b00210343364d1mr9452765wrz.103.1654020899802; Tue, 31 May 2022 11:14:59 -0700 (PDT) Received: from localhost.localdomain ([2a02:2f0e:c003:7c00:45d1:29c0:7802:f752]) by smtp.gmail.com with ESMTPSA id l3-20020a1c7903000000b003974027722csm2682980wme.47.2022.05.31.11.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 11:14:59 -0700 (PDT) From: Ovidiu Panait To: u-boot@lists.denx.de Cc: monstr@monstr.eu, Ovidiu Panait , Michal Simek Subject: [PATCH v2 10/14] microblaze: cache: introduce cpuinfo structure Date: Tue, 31 May 2022 21:14:31 +0300 Message-Id: <20220531181435.3473549-10-ovpanait@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220531181435.3473549-1-ovpanait@gmail.com> References: <20220531181435.3473549-1-ovpanait@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Introduce a minimal cpuinfo structure to hold cache related info. The instruction/data cache size and cache line size are initialized early in the boot to default Kconfig values. They will be overwritten with data from PVR/dtb if the microblaze UCLASS_CPU driver is enabled. The cpuinfo struct was placed in global_data to allow the microblaze UCLASS_CPU driver to also run before relocation (initialized global data should be read-only before relocation). gd_cpuinfo() helper macro was added to avoid volatile "-Wdiscarded-qualifiers" warnings when using the pointer directly. Signed-off-by: Ovidiu Panait --- Changes in v2: - New patch. arch/microblaze/cpu/Makefile | 2 +- arch/microblaze/cpu/cache.c | 14 ++++++--- arch/microblaze/cpu/cpuinfo.c | 20 +++++++++++++ arch/microblaze/cpu/start.S | 7 +++++ arch/microblaze/include/asm/cpuinfo.h | 35 +++++++++++++++++++++++ arch/microblaze/include/asm/global_data.h | 5 ++++ 6 files changed, 78 insertions(+), 5 deletions(-) create mode 100644 arch/microblaze/cpu/cpuinfo.c create mode 100644 arch/microblaze/include/asm/cpuinfo.h diff --git a/arch/microblaze/cpu/Makefile b/arch/microblaze/cpu/Makefile index f7a83d07b6..5388a21550 100644 --- a/arch/microblaze/cpu/Makefile +++ b/arch/microblaze/cpu/Makefile @@ -5,5 +5,5 @@ extra-y = start.o obj-y = irq.o -obj-y += interrupts.o cache.o exception.o timer.o +obj-y += interrupts.o cache.o exception.o timer.o cpuinfo.o obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index b99b8c1706..cd8507901d 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -9,11 +9,16 @@ #include #include #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; static void __invalidate_icache(ulong addr, ulong size) { if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WIC)) { - for (int i = 0; i < size; i += 4) { + for (int i = 0; i < size; + i += gd_cpuinfo()->icache_line_length) { asm volatile ( "wic %0, r0;" "nop;" @@ -26,13 +31,14 @@ static void __invalidate_icache(ulong addr, ulong size) void invalidate_icache_all(void) { - __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE); + __invalidate_icache(0, gd_cpuinfo()->icache_size); } static void __flush_dcache(ulong addr, ulong size) { if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { - for (int i = 0; i < size; i += 4) { + for (int i = 0; i < size; + i += gd_cpuinfo()->dcache_line_length) { asm volatile ( "wdc.flush %0, r0;" "nop;" @@ -45,7 +51,7 @@ static void __flush_dcache(ulong addr, ulong size) void flush_dcache_all(void) { - __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); + __flush_dcache(0, gd_cpuinfo()->dcache_size); } int dcache_status(void) diff --git a/arch/microblaze/cpu/cpuinfo.c b/arch/microblaze/cpu/cpuinfo.c new file mode 100644 index 0000000000..3f0b1d2c04 --- /dev/null +++ b/arch/microblaze/cpu/cpuinfo.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022, Ovidiu Panait + */ +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void microblaze_early_cpuinfo_init(void) +{ + struct microblaze_cpuinfo *ci = gd_cpuinfo(); + + ci->icache_size = CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE; + ci->icache_line_length = 4; + + ci->dcache_size = CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE; + ci->dcache_line_length = 4; +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 7f7b5f5cb5..ad400a4be5 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -51,6 +51,13 @@ _start: nop #endif + /* + * Initialize global data cpuinfo with default values (cache + * size, cache line size, etc). + */ + bralid r15, microblaze_early_cpuinfo_init + nop + /* Flush cache before enable cache */ bralid r15, flush_cache_all nop diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h new file mode 100644 index 0000000000..c27dd40af7 --- /dev/null +++ b/arch/microblaze/include/asm/cpuinfo.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2022, Ovidiu Panait + */ + +#ifndef __ASM_MICROBLAZE_CPUINFO_H +#define __ASM_MICROBLAZE_CPUINFO_H + +/** + * struct microblaze_cpuinfo - CPU info for microblaze processor core. + * + * @icache_size: Size of instruction cache memory in bytes. + * @icache_line_length: Instruction cache line length in bytes. + * @dcache_size: Size of data cache memory in bytes. + * @dcache_line_length: Data cache line length in bytes. + */ +struct microblaze_cpuinfo { + u32 icache_size; + u32 icache_line_length; + + u32 dcache_size; + u32 dcache_line_length; +}; + +/** + * microblaze_early_cpuinfo_init() - Initialize cpuinfo with default values. + * + * Initializes the global data cpuinfo structure with default values (cache + * size, cache line size, etc.). It is called very early in the boot process + * (start.S codepath right before the first cache flush call) to ensure that + * cache related operations are properly handled. + */ +void microblaze_early_cpuinfo_init(void); + +#endif /* __ASM_MICROBLAZE_CPUINFO_H */ diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index 05868ac4f5..93506dec89 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -8,12 +8,17 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include + /* Architecture-specific global data */ struct arch_global_data { + struct microblaze_cpuinfo cpuinfo; }; #include #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") +#define gd_cpuinfo() ((struct microblaze_cpuinfo *)&gd->arch.cpuinfo) + #endif /* __ASM_GBL_DATA_H */ -- 2.25.1