From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6115FC433F5 for ; Tue, 31 May 2022 18:17:09 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C89AE842FD; Tue, 31 May 2022 20:15:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Ztx418lJ"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 5B18783EF9; Tue, 31 May 2022 20:15:28 +0200 (CEST) Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 423D28427E for ; Tue, 31 May 2022 20:14:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=ovpanait@gmail.com Received: by mail-wr1-x433.google.com with SMTP id e25so9136436wra.11 for ; Tue, 31 May 2022 11:14:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OQHzuj02xnAf+SNWOU/9L+UfrnwB0/gk3gW2OAQi9gU=; b=Ztx418lJk92pLD65KwKXR/OxBAus4iciCvJ7s1YQdAatC0bQVNV5ADt+hDdeWotCqB qtJHUqg5NfuHcZRejiWJFCs2uVXyISIq0yEHoEaIWgLEuNANzikr+A/VIwEuqBeJatY+ 6gbuhQ1Zw/Sbgic6Zyd1CydSkdqo49VKEcdOnuf2UhOtpKiw5Haca5Hx4Uib2qjRDnyC nWll8Qyu+pT6+3SrvF8ol4VrJO+DRW1wkaamfMR619fNM2nJpJeG61TXDX7MfVKUh7We SV+JJOxqBeOA4vCxct5Xha4YesN9rWZiwZg6OYOzDSkDLZB2TKH8u2cVnc74rr3AjsVi e7cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OQHzuj02xnAf+SNWOU/9L+UfrnwB0/gk3gW2OAQi9gU=; b=Qmd4ql28HUiNRtQ6wnCEbNFePaGvs49TxGkF10meIjzG8NtHqfE7JlS/jHwUybp4I9 VApO8V9BKVUi7ES4/vdcllNMoiGH337JeiXxWtqFteQ4KaWcLphpUOVzisHJVVpcktIW 3g0auukOFelwfb7vD89u6RDDIOxTLEIBrPOcoyeoibIGhjWePCyprcOw8qf2uRhqlbOY yrYS6+xwOT4G4tRIO54Ld6FudtkF1jHU7+GAshuXbdkZMjZaSeu+kLB9NNl+znrcxiC2 fzrhRABCNiOn/riXJS2WeRYIKJe4ZeWHfgp0Mk4wkl4KXUlBYx2o7gkkyHj2+CvIjihS bt+Q== X-Gm-Message-State: AOAM532/T3mw1f/sfEvBBrYoQ9qlhKnTYSwEMRXLueOpuQtxThc9QY2z NHzDG+qWJmmhCRjCPJ5v6R0qw0qHN5I= X-Google-Smtp-Source: ABdhPJybYhxO0GTC6S6fUYMpLans9LsXmqj4vDKbpHqdL6JBk9CC5GXHovS5z0uyzTvM5XsVePwJKw== X-Received: by 2002:a05:6000:1847:b0:20f:c628:5884 with SMTP id c7-20020a056000184700b0020fc6285884mr41348500wri.526.1654020898744; Tue, 31 May 2022 11:14:58 -0700 (PDT) Received: from localhost.localdomain ([2a02:2f0e:c003:7c00:45d1:29c0:7802:f752]) by smtp.gmail.com with ESMTPSA id l3-20020a1c7903000000b003974027722csm2682980wme.47.2022.05.31.11.14.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 May 2022 11:14:58 -0700 (PDT) From: Ovidiu Panait To: u-boot@lists.denx.de Cc: monstr@monstr.eu, Ovidiu Panait , Alexandru Gagniuc , Marek Vasut , Michal Simek , Simon Glass Subject: [PATCH v2 09/14] microblaze: cache: introduce flush_cache_all() Date: Tue, 31 May 2022 21:14:30 +0300 Message-Id: <20220531181435.3473549-9-ovpanait@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220531181435.3473549-1-ovpanait@gmail.com> References: <20220531181435.3473549-1-ovpanait@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean All flush_cache() calls in microblaze code are supposed to flush the entire instruction and data caches, so introduce flush_cache_all() helper to handle this. Also, provide implementations for flush_dcache_all() and invalidate_icache_all() so that icache and dcache u-boot commands can work. Signed-off-by: Ovidiu Panait --- Changes in v2: - adjusted for newly added CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE and CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE Kconfig symbols arch/microblaze/cpu/cache.c | 20 ++++++++++++++++++-- arch/microblaze/cpu/start.S | 8 ++------ arch/microblaze/include/asm/cache.h | 5 +++++ arch/microblaze/lib/bootm.c | 2 +- 4 files changed, 26 insertions(+), 9 deletions(-) diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index d5c0afd935..b99b8c1706 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -24,6 +24,11 @@ static void __invalidate_icache(ulong addr, ulong size) } } +void invalidate_icache_all(void) +{ + __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE); +} + static void __flush_dcache(ulong addr, ulong size) { if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { @@ -38,6 +43,11 @@ static void __flush_dcache(ulong addr, ulong size) } } +void flush_dcache_all(void) +{ + __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); +} + int dcache_status(void) { int i = 0; @@ -65,7 +75,7 @@ void icache_enable(void) void icache_disable(void) { - __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE); + invalidate_icache_all(); MSRCLR(0x20); } @@ -77,7 +87,7 @@ void dcache_enable(void) void dcache_disable(void) { - __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); + flush_dcache_all(); MSRCLR(0x80); } @@ -87,3 +97,9 @@ void flush_cache(ulong addr, ulong size) __invalidate_icache(addr, size); __flush_dcache(addr, size); } + +void flush_cache_all(void) +{ + invalidate_icache_all(); + flush_dcache_all(); +} diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 356ca05392..7f7b5f5cb5 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -52,9 +52,7 @@ _start: #endif /* Flush cache before enable cache */ - addik r5, r0, 0 - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE - bralid r15, flush_cache + bralid r15, flush_cache_all nop /* enable instruction and data cache */ @@ -283,9 +281,7 @@ relocate_code: addk r20, r20, r23 /* Flush caches to ensure consistency */ - addik r5, r0, 0 - addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE - bralid r15, flush_cache + bralid r15, flush_cache_all nop 2: addi r5, r31, 0 /* gd is initialized in board_r.c */ diff --git a/arch/microblaze/include/asm/cache.h b/arch/microblaze/include/asm/cache.h index baee01a0e2..c39b66dd7d 100644 --- a/arch/microblaze/include/asm/cache.h +++ b/arch/microblaze/include/asm/cache.h @@ -18,4 +18,9 @@ #define ARCH_DMA_MINALIGN 16 #endif +/** + * flush_cache_all - flush the entire instruction/data caches + */ +void flush_cache_all(void); + #endif /* __MICROBLAZE_CACHE_H__ */ diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 48e05333a6..af946b8642 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); - flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); + flush_cache_all(); if (!fake) { /* -- 2.25.1