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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id e13-20020a170906248d00b006fee7b5dff2sm845870ejb.143.2022.06.01.08.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 08:27:51 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 1/7] ARM: dts: s3c2410: use local header for pinctrl register values Date: Wed, 1 Jun 2022 17:27:14 +0200 Message-Id: <20220601152720.232383-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220601152720.232383-1-krzysztof.kozlowski@linaro.org> References: <20220601152720.232383-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The DTS uses hardware register values directly in pin controller pin configuration. These are not some IDs or other abstraction layer but raw numbers used in the registers. These numbers were previously put in the bindings header to avoid code duplication and to provide some context meaning (name), but they do not fit the purpose of bindings. It is also quite confusing to use constants prefixed with Exynos for other SoC, because there is actually nothing here in common, except the actual value. Store the constants in a header next to DTS and use them instead of bindings. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s3c2410-pinctrl.h | 19 +++++++++++++ arch/arm/boot/dts/s3c2416-pinctrl.dtsi | 38 +++++++++++++------------- 2 files changed, 38 insertions(+), 19 deletions(-) create mode 100644 arch/arm/boot/dts/s3c2410-pinctrl.h diff --git a/arch/arm/boot/dts/s3c2410-pinctrl.h b/arch/arm/boot/dts/s3c2410-pinctrl.h new file mode 100644 index 000000000000..76b6171ae149 --- /dev/null +++ b/arch/arm/boot/dts/s3c2410-pinctrl.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S3C2410 DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski + */ + +#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ + +#define S3C2410_PIN_FUNC_INPUT 0 +#define S3C2410_PIN_FUNC_OUTPUT 1 +#define S3C2410_PIN_FUNC_2 2 +#define S3C2410_PIN_FUNC_3 3 + +#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi index 20a7d72827c2..3268366bd8bc 100644 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Heiko Stuebner */ -#include +#include "s3c2410-pinctrl.h" &pinctrl_0 { /* @@ -82,91 +82,91 @@ gpm: gpm-gpio-bank { uart0_data: uart0-data-pins { samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart0_fctl: uart0-fctl-pins { samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart1_data: uart1-data-pins { samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart1_fctl: uart1-fctl-pins { samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart2_data: uart2-data-pins { samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart2_fctl: uart2-fctl-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart3_data: uart3-data-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; + samsung,pin-function = ; }; extuart_clk: extuart-clk-pins { samsung,pins = "gph-12"; - samsung,pin-function = ; + samsung,pin-function = ; }; i2c0_bus: i2c0-bus-pins { samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = ; + samsung,pin-function = ; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_clk: sd0-clk-pins { samsung,pins = "gpe-5"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_cmd: sd0-cmd-pins { samsung,pins = "gpe-6"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_bus1: sd0-bus1-pins { samsung,pins = "gpe-7"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_bus4: sd0-bus4-pins { samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_cmd: sd1-cmd-pins { samsung,pins = "gpl-8"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_clk: sd1-clk-pins { samsung,pins = "gpl-9"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_bus1: sd1-bus1-pins { samsung,pins = "gpl-0"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_bus4: sd1-bus4-pins { samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = ; + samsung,pin-function = ; }; }; -- 2.34.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84DF1C433EF for ; Wed, 1 Jun 2022 15:29:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=fgWQeT6Eexp3W1qIDqDEK7DVvXvLLlLc4sgyruGj8zY=; b=UmM0PN39xwOqqJ 6MZdUjLOIM5+XUIkk5y+ON3dE3GE/IkSmUXvYXcr6xfCEjeAWgCHVZNsCFsiP7MlKLzLn+qToGT/O z0oFGfeeYIuTh0t1W2mNJ9tzklwnxxhojVofXoisnikqLN7Ykrvk06EGdzdQ57Or7xXuIlFwDz4pC jL758c+tosU9bDQV8arctK+cgURv8AcE/lg9ZNnbcFlT5jsLU5yI/BOkEuotMYKl+PBDAefMB4szE 1XKpRG7SUZAPyCzrbmjcJ2Mti+rc5jXv9+FLLcrGkjYfxmsiImtHMzMcLWsC0+8O8AThwEpm67DQ8 lhRnvCHQQvZgUpX8iOiQ==; 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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id e13-20020a170906248d00b006fee7b5dff2sm845870ejb.143.2022.06.01.08.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 08:27:51 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Alim Akhtar , Tomasz Figa , Sylwester Nawrocki , Linus Walleij , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 1/7] ARM: dts: s3c2410: use local header for pinctrl register values Date: Wed, 1 Jun 2022 17:27:14 +0200 Message-Id: <20220601152720.232383-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220601152720.232383-1-krzysztof.kozlowski@linaro.org> References: <20220601152720.232383-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220601_082753_566913_1996F430 X-CRM114-Status: GOOD ( 18.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The DTS uses hardware register values directly in pin controller pin configuration. These are not some IDs or other abstraction layer but raw numbers used in the registers. These numbers were previously put in the bindings header to avoid code duplication and to provide some context meaning (name), but they do not fit the purpose of bindings. It is also quite confusing to use constants prefixed with Exynos for other SoC, because there is actually nothing here in common, except the actual value. Store the constants in a header next to DTS and use them instead of bindings. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s3c2410-pinctrl.h | 19 +++++++++++++ arch/arm/boot/dts/s3c2416-pinctrl.dtsi | 38 +++++++++++++------------- 2 files changed, 38 insertions(+), 19 deletions(-) create mode 100644 arch/arm/boot/dts/s3c2410-pinctrl.h diff --git a/arch/arm/boot/dts/s3c2410-pinctrl.h b/arch/arm/boot/dts/s3c2410-pinctrl.h new file mode 100644 index 000000000000..76b6171ae149 --- /dev/null +++ b/arch/arm/boot/dts/s3c2410-pinctrl.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung S3C2410 DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski + */ + +#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ +#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ + +#define S3C2410_PIN_FUNC_INPUT 0 +#define S3C2410_PIN_FUNC_OUTPUT 1 +#define S3C2410_PIN_FUNC_2 2 +#define S3C2410_PIN_FUNC_3 3 + +#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi index 20a7d72827c2..3268366bd8bc 100644 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -5,7 +5,7 @@ * Copyright (c) 2013 Heiko Stuebner */ -#include +#include "s3c2410-pinctrl.h" &pinctrl_0 { /* @@ -82,91 +82,91 @@ gpm: gpm-gpio-bank { uart0_data: uart0-data-pins { samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart0_fctl: uart0-fctl-pins { samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart1_data: uart1-data-pins { samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart1_fctl: uart1-fctl-pins { samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart2_data: uart2-data-pins { samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart2_fctl: uart2-fctl-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; + samsung,pin-function = ; }; uart3_data: uart3-data-pins { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; + samsung,pin-function = ; }; extuart_clk: extuart-clk-pins { samsung,pins = "gph-12"; - samsung,pin-function = ; + samsung,pin-function = ; }; i2c0_bus: i2c0-bus-pins { samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = ; + samsung,pin-function = ; }; spi0_bus: spi0-bus-pins { samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_clk: sd0-clk-pins { samsung,pins = "gpe-5"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_cmd: sd0-cmd-pins { samsung,pins = "gpe-6"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_bus1: sd0-bus1-pins { samsung,pins = "gpe-7"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd0_bus4: sd0-bus4-pins { samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_cmd: sd1-cmd-pins { samsung,pins = "gpl-8"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_clk: sd1-clk-pins { samsung,pins = "gpl-9"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_bus1: sd1-bus1-pins { samsung,pins = "gpl-0"; - samsung,pin-function = ; + samsung,pin-function = ; }; sd1_bus4: sd1-bus4-pins { samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = ; + samsung,pin-function = ; }; }; -- 2.34.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel