From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A1B9C433EF for ; Thu, 2 Jun 2022 15:14:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231998AbiFBPOO (ORCPT ); Thu, 2 Jun 2022 11:14:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54296 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230114AbiFBPON (ORCPT ); Thu, 2 Jun 2022 11:14:13 -0400 Received: from mail-oa1-f41.google.com (mail-oa1-f41.google.com [209.85.160.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D3DD9D4CC; Thu, 2 Jun 2022 08:14:11 -0700 (PDT) Received: by mail-oa1-f41.google.com with SMTP id 586e51a60fabf-f2cbceefb8so7074172fac.11; Thu, 02 Jun 2022 08:14:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=8ZadL1zw6i8KMO5fh9Q5arKi4oyBgssFPCtUsRXeJWQ=; b=74Xls42noV6dGVcgYIu8X9xYwxmbYLGOqzzFjW9r0irpBqOHNa/4RElXKXQAy5wYbf Zfe/fBOzyIoY937OyWBClGQ8YhWC/p7HrTMbb+/Qe4AP/QynfSLCFCnxoKtfHycaTYHu TM77sT0teh7gxtm0OGhUtT+kBVytCf1Q5SXvkP/XAhDvNu0W8Er345aNCY1FRyNmtEu4 k97498Jprrg+nRZ0uirCv1TP+SIYmSJtogB1APlmksqLujK+M60inKWf/XwfLgOmdMcV 1zp61AQRKEVTM7L2mwXTHQBtj86av5sdaM8v9MYyd/ENsHaTjv2pzNntQeex7ULKxu7s vSVw== X-Gm-Message-State: AOAM532eVkIK+oLoT8wjheFl8+ZPWTJVScRXjhnwYHd6ltdChk1IP3wt pm64ZIfGUJsnAyHDvVkP0HsI0d71tNB6 X-Google-Smtp-Source: ABdhPJzAwCQkxG7V7ktiZLgQzY3iiWykAD/DDTVfLswQC6nHYlfO/vO82ui1Cc1rqBIYY5AbTW/+Kw== X-Received: by 2002:a05:6870:348c:b0:e2:6df1:b1db with SMTP id n12-20020a056870348c00b000e26df1b1dbmr20482904oah.33.1654182850598; Thu, 02 Jun 2022 08:14:10 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id b36-20020a056870392400b000f349108868sm2179826oap.44.2022.06.02.08.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 08:14:10 -0700 (PDT) Received: (nullmailer pid 2339298 invoked by uid 1000); Thu, 02 Jun 2022 15:14:09 -0000 Date: Thu, 2 Jun 2022 10:14:09 -0500 From: Rob Herring To: Tanmay Shah Cc: openamp-system-reference@lists.openampproject.org, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, krzk+dt@kernel.org, michal.simek@xilinx.com, ben.levinsky@xilinx.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v6 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Message-ID: <20220602151409.GA2333778-robh@kernel.org> References: <20220531234308.3317795-1-tanmay.shah@xilinx.com> <20220531234308.3317795-2-tanmay.shah@xilinx.com> <20220601184240.GA188558-robh@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org On Wed, Jun 01, 2022 at 12:05:09PM -0700, Tanmay Shah wrote: > Hi Rob, > > Thanks for reviews. Please find my comments below: > > On 6/1/22 11:42 AM, Rob Herring wrote: > > On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote: > > > Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing > > > Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem > > > (cluster). > > > > > > Signed-off-by: Tanmay Shah > > > --- > > > > > > Changes in v6: > > > - Add maxItems to sram and memory-region property > > > > > > Changes in v5: > > > - Add constraints of the possible values of xlnx,cluster-mode property > > > - fix description of power-domains property for r5 core > > > - Remove reg, address-cells and size-cells properties as it is not required > > > - Fix description of mboxes property > > > - Add description of each memory-region and remove old .txt binding link > > > reference in the description > > > > > > Changes in v4: > > > - Add memory-region, mboxes and mbox-names properties in example > > > > > > Changes in v3: > > > - None > > > > > > > > > .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ > > > include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + > > > 2 files changed, 135 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > new file mode 100644 > > > index 000000000000..cbff1c201a89 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > @@ -0,0 +1,129 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Xilinx R5F processor subsystem > > > + > > > +maintainers: > > > + - Ben Levinsky > > > + - Tanmay Shah > > > + > > > +description: | > > > + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for > > > + real-time processing based on the Cortex-R5F processor core from ARM. > > > + The Cortex-R5F processor implements the Arm v7-R architecture and includes a > > > + floating-point unit that implements the Arm VFPv3 instruction set. > > > + > > > +properties: > > > + compatible: > > > + const: xlnx,zynqmp-r5fss > > > + > > > + xlnx,cluster-mode: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + enum: [0, 1, 2] > > > + description: | > > > + The RPU MPCore can operate in split mode(Dual-processor performance), Safety > > > + lock-step mode(Both RPU cores execute the same code in lock-step, > > > + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while > > > + core 1 runs normally). The processor does not support dynamic configuration. > > > + Switching between modes is only permitted immediately after a processor reset. > > > + If set to 1 then lockstep mode and if 0 then split mode. > > > + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. > > > + > > > +patternProperties: > > > + "^r5f-[a-f0-9]+$": > > > + type: object > > > + description: | > > > + The RPU is located in the Low Power Domain of the Processor Subsystem. > > > + Each processor includes separate L1 instruction and data caches and > > > + tightly coupled memories (TCM). System memory is cacheable, but the TCM > > > + memory space is non-cacheable. > > > + > > > + Each RPU contains one 64KB memory and two 32KB memories that > > > + are accessed via the TCM A and B port interfaces, for a total of 128KB > > > + per processor. In lock-step mode, the processor has access to 256KB of > > > + TCM memory. > > > + > > > + properties: > > > + compatible: > > > + const: xlnx,zynqmp-r5f > > > + > > > + power-domains: > > > + description: RPU core PM domain specifier > > > + maxItems: 1 > > > + > > > + mboxes: > > > + minItems: 1 > > > + items: > > > + - description: mailbox channel to send data to RPU > > > + - description: mailbox channel to receive data from RPU > > > + > > > + mbox-names: > > > + minItems: 1 > > > + items: > > > + - const: tx > > > + - const: rx > > > + > > > + sram: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + maxItems: 8 > > minItems: 1 > > maxItems: 8 > > items: > > maxItems: 1 > > I have posted v7 which adds "minItems: 1". > > However, I didn't get items: part. Is it required to have items: now? Yes. > > Can I add items: part once TCM bindings are posted? No. > I understand that minItems and maxItems under sram property decides how many > phandles sram can have. > > However, maxItems: 1 under items: field what it describes? 'phandle-array' is really a matrix type because we can have phandles plus argument cells. So you have to define each of the 1-8 entries is a single phandle cell (and no arg cells). Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBD92C43334 for ; Thu, 2 Jun 2022 15:15:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=sh+8vV2wnkgtTN7TzSA8lngrc+sRcE07IIRlHaRDDI8=; b=Wz8wtoyRodHU+s Hf/qsFx6Jhj2nFg3gL3vnheNqHOoHXf/gyU4y7a1LVk69j1kKqxst7YRUHrNxOHwYeokhYVPu64j8 sUcek1ZZxayPCUO2KjIm0XOGuBmhOLjKKzaGk8iuJGTW9vpMrNN6kabh+5Xeu34Yn/AgxuHyqI0Ng 3buY+gXnr76inotxuGGLQQzN01OPP3uHCER2dJtAcxOrt1Z2Hww0mLhtv6GYbk6BZBKhJbQ8Pnz44 Kg+TdCVyM6/+ZehOJI+wxE9LXiKW5QYJx3rHViuVBlYq2WU03y4vNo3oQFkL+CAfLYrgKuOJeYjKv FAfzLE6YVcydbtYatXFg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwmWd-003fTV-5d; Thu, 02 Jun 2022 15:14:15 +0000 Received: from mail-oa1-f42.google.com ([209.85.160.42]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nwmWZ-003fST-EU for linux-arm-kernel@lists.infradead.org; Thu, 02 Jun 2022 15:14:13 +0000 Received: by mail-oa1-f42.google.com with SMTP id 586e51a60fabf-f2bb84f9edso7081411fac.10 for ; Thu, 02 Jun 2022 08:14:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=8ZadL1zw6i8KMO5fh9Q5arKi4oyBgssFPCtUsRXeJWQ=; b=1hPa6hvqiYUz0tZfMelIHP9iNQ0y8hhPEsYLDTdyEFdGGDv0PWvzBCdsgXX6PcssgM iZPEBctQpSConSW1Z6WBoBaSWEHf37oHSz4iz1SaUi95fjJ3SDaKYQVF4vTY+0LT7KAw aIC0wkjIF/QwXvvCMSv4BQAWSCNeK47mKBSES4xzmkE55/yggc6jSNvrAGBTyUu1s4M8 eNZ6xatzFBTumMsze3KByPWeveUE/H/Z8x6Fw6irw1Ey5q3yfWGF1UJmyRIe3e7E4IFc 1NFHE7FBLP8XbzOBJYmBEr1Jc0K+0w0tca9z7TLP2+wtyTOso9GlYsa/kueYqvjZaCqu Vxbg== X-Gm-Message-State: AOAM530ng3Uqkxm5LmIi+JQKJ0YTDaxpSm8KvjW3MpnFSgaadS1yFe4K ylgqA3u080cXXOj4SrE8nw== X-Google-Smtp-Source: ABdhPJzAwCQkxG7V7ktiZLgQzY3iiWykAD/DDTVfLswQC6nHYlfO/vO82ui1Cc1rqBIYY5AbTW/+Kw== X-Received: by 2002:a05:6870:348c:b0:e2:6df1:b1db with SMTP id n12-20020a056870348c00b000e26df1b1dbmr20482904oah.33.1654182850598; Thu, 02 Jun 2022 08:14:10 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id b36-20020a056870392400b000f349108868sm2179826oap.44.2022.06.02.08.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 08:14:10 -0700 (PDT) Received: (nullmailer pid 2339298 invoked by uid 1000); Thu, 02 Jun 2022 15:14:09 -0000 Date: Thu, 2 Jun 2022 10:14:09 -0500 From: Rob Herring To: Tanmay Shah Cc: openamp-system-reference@lists.openampproject.org, bjorn.andersson@linaro.org, mathieu.poirier@linaro.org, krzk+dt@kernel.org, michal.simek@xilinx.com, ben.levinsky@xilinx.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v6 1/6] dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Message-ID: <20220602151409.GA2333778-robh@kernel.org> References: <20220531234308.3317795-1-tanmay.shah@xilinx.com> <20220531234308.3317795-2-tanmay.shah@xilinx.com> <20220601184240.GA188558-robh@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220602_081411_546261_673E2510 X-CRM114-Status: GOOD ( 34.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 01, 2022 at 12:05:09PM -0700, Tanmay Shah wrote: > Hi Rob, > > Thanks for reviews. Please find my comments below: > > On 6/1/22 11:42 AM, Rob Herring wrote: > > On Tue, May 31, 2022 at 04:43:05PM -0700, Tanmay Shah wrote: > > > Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing > > > Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem > > > (cluster). > > > > > > Signed-off-by: Tanmay Shah > > > --- > > > > > > Changes in v6: > > > - Add maxItems to sram and memory-region property > > > > > > Changes in v5: > > > - Add constraints of the possible values of xlnx,cluster-mode property > > > - fix description of power-domains property for r5 core > > > - Remove reg, address-cells and size-cells properties as it is not required > > > - Fix description of mboxes property > > > - Add description of each memory-region and remove old .txt binding link > > > reference in the description > > > > > > Changes in v4: > > > - Add memory-region, mboxes and mbox-names properties in example > > > > > > Changes in v3: > > > - None > > > > > > > > > .../bindings/remoteproc/xlnx,r5f-rproc.yaml | 129 ++++++++++++++++++ > > > include/dt-bindings/power/xlnx-zynqmp-power.h | 6 + > > > 2 files changed, 135 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > > > > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > new file mode 100644 > > > index 000000000000..cbff1c201a89 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,r5f-rproc.yaml > > > @@ -0,0 +1,129 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/remoteproc/xlnx,r5f-rproc.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Xilinx R5F processor subsystem > > > + > > > +maintainers: > > > + - Ben Levinsky > > > + - Tanmay Shah > > > + > > > +description: | > > > + The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for > > > + real-time processing based on the Cortex-R5F processor core from ARM. > > > + The Cortex-R5F processor implements the Arm v7-R architecture and includes a > > > + floating-point unit that implements the Arm VFPv3 instruction set. > > > + > > > +properties: > > > + compatible: > > > + const: xlnx,zynqmp-r5fss > > > + > > > + xlnx,cluster-mode: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + enum: [0, 1, 2] > > > + description: | > > > + The RPU MPCore can operate in split mode(Dual-processor performance), Safety > > > + lock-step mode(Both RPU cores execute the same code in lock-step, > > > + clock-for-clock) or Single CPU mode (RPU core 0 can be held in reset while > > > + core 1 runs normally). The processor does not support dynamic configuration. > > > + Switching between modes is only permitted immediately after a processor reset. > > > + If set to 1 then lockstep mode and if 0 then split mode. > > > + If set to 2 then single CPU mode. When not defined, default will be lockstep mode. > > > + > > > +patternProperties: > > > + "^r5f-[a-f0-9]+$": > > > + type: object > > > + description: | > > > + The RPU is located in the Low Power Domain of the Processor Subsystem. > > > + Each processor includes separate L1 instruction and data caches and > > > + tightly coupled memories (TCM). System memory is cacheable, but the TCM > > > + memory space is non-cacheable. > > > + > > > + Each RPU contains one 64KB memory and two 32KB memories that > > > + are accessed via the TCM A and B port interfaces, for a total of 128KB > > > + per processor. In lock-step mode, the processor has access to 256KB of > > > + TCM memory. > > > + > > > + properties: > > > + compatible: > > > + const: xlnx,zynqmp-r5f > > > + > > > + power-domains: > > > + description: RPU core PM domain specifier > > > + maxItems: 1 > > > + > > > + mboxes: > > > + minItems: 1 > > > + items: > > > + - description: mailbox channel to send data to RPU > > > + - description: mailbox channel to receive data from RPU > > > + > > > + mbox-names: > > > + minItems: 1 > > > + items: > > > + - const: tx > > > + - const: rx > > > + > > > + sram: > > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > > + maxItems: 8 > > minItems: 1 > > maxItems: 8 > > items: > > maxItems: 1 > > I have posted v7 which adds "minItems: 1". > > However, I didn't get items: part. Is it required to have items: now? Yes. > > Can I add items: part once TCM bindings are posted? No. > I understand that minItems and maxItems under sram property decides how many > phandles sram can have. > > However, maxItems: 1 under items: field what it describes? 'phandle-array' is really a matrix type because we can have phandles plus argument cells. So you have to define each of the 1-8 entries is a single phandle cell (and no arg cells). Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel