* [Intel-gfx] [PATCH v3 i-g-t 0/2] Update DRM UAPI and add test for new hw info query
@ 2022-06-03 0:54 John.C.Harrison
2022-06-03 0:54 ` [igt-dev] " John.C.Harrison
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: John.C.Harrison @ 2022-06-03 0:54 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Various UMDs require hardware configuration information about the
current platform. A new interface has been added to the KMD to return
this information. So, add a test for the new interface.
Also, update to the latest DRM UAPI header file that contains the new
query enums.
v2: Rebased to newer baseline.
v3: Update UAPI header file.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
John Harrison (1):
include/drm-uapi: Update to latest i915_drm.h
Rodrigo Vivi (1):
tests/i915/query: Query, parse and validate the hwconfig table
include/drm-uapi/i915_drm.h | 410 ++++++++++++++++++++++++++++--------
lib/intel_hwconfig_types.h | 118 +++++++++++
tests/i915/i915_query.c | 179 ++++++++++++++++
3 files changed, 615 insertions(+), 92 deletions(-)
create mode 100644 lib/intel_hwconfig_types.h
--
2.36.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v3 i-g-t 1/2] include/drm-uapi: Update to latest i915_drm.h
2022-06-03 0:54 [Intel-gfx] [PATCH v3 i-g-t 0/2] Update DRM UAPI and add test for new hw info query John.C.Harrison
@ 2022-06-03 0:54 ` John.C.Harrison
2022-06-03 0:54 ` [Intel-gfx] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: John.C.Harrison @ 2022-06-03 0:54 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Update to the latest master version of the DRM UAPI header file.
NB: Had to remove '__user' keywords as they do not appear to be
supported outside of kernel builds.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
include/drm-uapi/i915_drm.h | 410 ++++++++++++++++++++++++++++--------
1 file changed, 318 insertions(+), 92 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 9c9e1afa61ba..5d4166eb80a3 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -24,8 +24,8 @@
*
*/
-#ifndef _I915_DRM_H_
-#define _I915_DRM_H_
+#ifndef _UAPI_I915_DRM_H_
+#define _UAPI_I915_DRM_H_
#include "drm.h"
@@ -75,7 +75,7 @@ extern "C" {
* redefine the interface more easily than an ever growing struct of
* increasing complexity, and for large parts of that interface to be
* entirely optional. The downside is more pointer chasing; chasing across
- * the boundary with pointers encapsulated inside u64.
+ * the __user boundary with pointers encapsulated inside u64.
*
* Example chaining:
*
@@ -154,25 +154,77 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
};
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
* Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role. This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
*/
enum drm_i915_gem_engine_class {
+ /**
+ * @I915_ENGINE_CLASS_RENDER:
+ *
+ * Render engines support instructions used for 3D, Compute (GPGPU),
+ * and programmable media workloads. These instructions fetch data and
+ * dispatch individual work items to threads that operate in parallel.
+ * The threads run small programs (called "kernels" or "shaders") on
+ * the GPU's execution units (EUs).
+ */
I915_ENGINE_CLASS_RENDER = 0,
+
+ /**
+ * @I915_ENGINE_CLASS_COPY:
+ *
+ * Copy engines (also referred to as "blitters") support instructions
+ * that move blocks of data from one location in memory to another,
+ * or that fill a specified location of memory with fixed data.
+ * Copy engines can perform pre-defined logical or bitwise operations
+ * on the source, destination, or pattern data.
+ */
I915_ENGINE_CLASS_COPY = 1,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO:
+ *
+ * Video engines (also referred to as "bit stream decode" (BSD) or
+ * "vdbox") support instructions that perform fixed-function media
+ * decode and encode.
+ */
I915_ENGINE_CLASS_VIDEO = 2,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ *
+ * Video enhancement engines (also referred to as "vebox") support
+ * instructions related to image enhancement.
+ */
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
+ /**
+ * @I915_ENGINE_CLASS_COMPUTE:
+ *
+ * Compute engines support a subset of the instructions available
+ * on render engines: compute engines support Compute (GPGPU) and
+ * programmable media workloads, but do not support the 3D pipeline.
+ */
+ I915_ENGINE_CLASS_COMPUTE = 4,
+
+ /* Values in this enum should be kept compact. */
+ /**
+ * @I915_ENGINE_CLASS_INVALID:
+ *
+ * Placeholder value to represent an invalid engine class assignment.
+ */
I915_ENGINE_CLASS_INVALID = -1
};
-/*
+/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
* There may be more than one engine fulfilling any role within the system.
* Each engine of a class is given a unique instance number and therefore
* any engine can be specified by its class:instance tuplet. APIs that allow
@@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
* for this identification.
*/
struct i915_engine_class_instance {
- __u16 engine_class; /* see enum drm_i915_gem_engine_class */
- __u16 engine_instance;
+ /**
+ * @engine_class:
+ *
+ * Engine class from enum drm_i915_gem_engine_class
+ */
+ __u16 engine_class;
#define I915_ENGINE_CLASS_INVALID_NONE -1
#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+ /**
+ * @engine_instance:
+ *
+ * Engine instance.
+ */
+ __u16 engine_instance;
};
/**
@@ -1118,10 +1181,16 @@ struct drm_i915_gem_exec_object2 {
/**
* When the EXEC_OBJECT_PINNED flag is specified this is populated by
* the user with the GTT offset at which this object will be pinned.
+ *
* When the I915_EXEC_NO_RELOC flag is specified this must contain the
* presumed_offset of the object.
+ *
* During execbuffer2 the kernel populates it with the value of the
* current GTT offset of the object, for future presumed_offset writes.
+ *
+ * See struct drm_i915_gem_create_ext for the rules when dealing with
+ * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
+ * minimum page sizes, like DG2.
*/
__u64 offset;
@@ -2221,7 +2290,7 @@ struct i915_context_engines_parallel_submit {
*/
struct i915_engine_class_instance engines[0];
-} __attribute__((packed));
+} __packed;
#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
struct i915_user_extension base; \
@@ -2594,7 +2663,7 @@ struct drm_i915_perf_open_param {
* Change metrics_set captured by a stream.
*
* If the stream is bound to a specific context, the configuration change
- * will performed __inline__ with that context such that it takes effect before
+ * will performed inline with that context such that it takes effect before
* the next execbuf submission.
*
* Returns the previously bound metrics set id, or a negative error code.
@@ -2651,24 +2720,65 @@ enum drm_i915_perf_record_type {
DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
-/*
+/**
+ * struct drm_i915_perf_oa_config
+ *
* Structure to upload perf dynamic configuration into the kernel.
*/
struct drm_i915_perf_oa_config {
- /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
+ /**
+ * @uuid:
+ *
+ * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
+ */
char uuid[36];
+ /**
+ * @n_mux_regs:
+ *
+ * Number of mux regs in &mux_regs_ptr.
+ */
__u32 n_mux_regs;
+
+ /**
+ * @n_boolean_regs:
+ *
+ * Number of boolean regs in &boolean_regs_ptr.
+ */
__u32 n_boolean_regs;
+
+ /**
+ * @n_flex_regs:
+ *
+ * Number of flex regs in &flex_regs_ptr.
+ */
__u32 n_flex_regs;
- /*
- * These fields are pointers to tuples of u32 values (register address,
- * value). For example the expected length of the buffer pointed by
- * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+ /**
+ * @mux_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_mux_regs).
*/
__u64 mux_regs_ptr;
+
+ /**
+ * @boolean_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_boolean_regs).
+ */
__u64 boolean_regs_ptr;
+
+ /**
+ * @flex_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_flex_regs).
+ */
__u64 flex_regs_ptr;
};
@@ -2679,12 +2789,24 @@ struct drm_i915_perf_oa_config {
* @data_ptr is also depends on the specific @query_id.
*/
struct drm_i915_query_item {
- /** @query_id: The id for this query */
+ /**
+ * @query_id:
+ *
+ * The id for this query. Currently accepted query IDs are:
+ * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
+ * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
+ * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
+ * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
+ * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
+ * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
+ */
__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO 1
-#define DRM_I915_QUERY_ENGINE_INFO 2
-#define DRM_I915_QUERY_PERF_CONFIG 3
-#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_TOPOLOGY_INFO 1
+#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_PERF_CONFIG 3
+#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_BLOB 5
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
/* Must be kept compact -- no holes and well documented */
/**
@@ -2700,14 +2822,17 @@ struct drm_i915_query_item {
/**
* @flags:
*
- * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+ * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+ * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
* following:
*
- * - DRM_I915_QUERY_PERF_CONFIG_LIST
- * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
- * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+ * - %DRM_I915_QUERY_PERF_CONFIG_LIST
+ * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+ * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+ *
+ * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
+ * a struct i915_engine_class_instance that references a render engine.
*/
__u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
@@ -2765,66 +2890,112 @@ struct drm_i915_query {
__u64 items_ptr;
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
- *
- * data: contains the 3 pieces of information :
- *
- * - the slice mask with one bit per slice telling whether a slice is
- * available. The availability of slice X can be queried with the following
- * formula :
- *
- * (data[X / 8] >> (X % 8)) & 1
- *
- * - the subslice mask for each slice with one bit per subslice telling
- * whether a subslice is available. Gen12 has dual-subslices, which are
- * similar to two gen11 subslices. For gen12, this array represents dual-
- * subslices. The availability of subslice Y in slice X can be queried
- * with the following formula :
- *
- * (data[subslice_offset +
- * X * subslice_stride +
- * Y / 8] >> (Y % 8)) & 1
- *
- * - the EU mask for each subslice in each slice with one bit per EU telling
- * whether an EU is available. The availability of EU Z in subslice Y in
- * slice X can be queried with the following formula :
+/**
+ * struct drm_i915_query_topology_info
*
- * (data[eu_offset +
- * (X * max_subslices + Y) * eu_stride +
- * Z / 8] >> (Z % 8)) & 1
+ * Describes slice/subslice/EU information queried by
+ * %DRM_I915_QUERY_TOPOLOGY_INFO
*/
struct drm_i915_query_topology_info {
- /*
+ /**
+ * @flags:
+ *
* Unused for now. Must be cleared to zero.
*/
__u16 flags;
+ /**
+ * @max_slices:
+ *
+ * The number of bits used to express the slice mask.
+ */
__u16 max_slices;
+
+ /**
+ * @max_subslices:
+ *
+ * The number of bits used to express the subslice mask.
+ */
__u16 max_subslices;
+
+ /**
+ * @max_eus_per_subslice:
+ *
+ * The number of bits in the EU mask that correspond to a single
+ * subslice's EUs.
+ */
__u16 max_eus_per_subslice;
- /*
+ /**
+ * @subslice_offset:
+ *
* Offset in data[] at which the subslice masks are stored.
*/
__u16 subslice_offset;
- /*
+ /**
+ * @subslice_stride:
+ *
* Stride at which each of the subslice masks for each slice are
* stored.
*/
__u16 subslice_stride;
- /*
+ /**
+ * @eu_offset:
+ *
* Offset in data[] at which the EU masks are stored.
*/
__u16 eu_offset;
- /*
+ /**
+ * @eu_stride:
+ *
* Stride at which each of the EU masks for each subslice are stored.
*/
__u16 eu_stride;
+ /**
+ * @data:
+ *
+ * Contains 3 pieces of information :
+ *
+ * - The slice mask with one bit per slice telling whether a slice is
+ * available. The availability of slice X can be queried with the
+ * following formula :
+ *
+ * .. code:: c
+ *
+ * (data[X / 8] >> (X % 8)) & 1
+ *
+ * Starting with Xe_HP platforms, Intel hardware no longer has
+ * traditional slices so i915 will always report a single slice
+ * (hardcoded slicemask = 0x1) which contains all of the platform's
+ * subslices. I.e., the mask here does not reflect any of the newer
+ * hardware concepts such as "gslices" or "cslices" since userspace
+ * is capable of inferring those from the subslice mask.
+ *
+ * - The subslice mask for each slice with one bit per subslice telling
+ * whether a subslice is available. Starting with Gen12 we use the
+ * term "subslice" to refer to what the hardware documentation
+ * describes as a "dual-subslices." The availability of subslice Y
+ * in slice X can be queried with the following formula :
+ *
+ * .. code:: c
+ *
+ * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
+ *
+ * - The EU mask for each subslice in each slice, with one bit per EU
+ * telling whether an EU is available. The availability of EU Z in
+ * subslice Y in slice X can be queried with the following formula :
+ *
+ * .. code:: c
+ *
+ * (data[eu_offset +
+ * (X * max_subslices + Y) * eu_stride +
+ * Z / 8
+ * ] >> (Z % 8)) & 1
+ */
__u8 data[];
};
@@ -2945,52 +3116,68 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+/**
+ * struct drm_i915_query_perf_config
+ *
+ * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
+ * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
*/
struct drm_i915_query_perf_config {
union {
- /*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
- * this fields to the number of configurations available.
+ /**
+ * @n_configs:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
+ * the number of configurations available.
*/
__u64 n_configs;
- /*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
- * i915 will use the value in this field as configuration
- * identifier to decide what data to write into config_ptr.
+ /**
+ * @config:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
+ * value in this field as configuration identifier to decide
+ * what data to write into config_ptr.
*/
__u64 config;
- /*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
- * i915 will use the value in this field as configuration
- * identifier to decide what data to write into config_ptr.
+ /**
+ * @uuid:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
+ * value in this field as configuration identifier to decide
+ * what data to write into config_ptr.
*
* String formatted like "%08x-%04x-%04x-%04x-%012x"
*/
char uuid[36];
};
- /*
+ /**
+ * @flags:
+ *
* Unused for now. Must be cleared to zero.
*/
__u32 flags;
- /*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
- * write an array of __u64 of configuration identifiers.
+ /**
+ * @data:
*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
- * write a struct drm_i915_perf_oa_config. If the following fields of
- * drm_i915_perf_oa_config are set not set to 0, i915 will write into
- * the associated pointers the values of submitted when the
+ * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
+ * i915 will write an array of __u64 of configuration identifiers.
+ *
+ * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
+ * i915 will write a struct drm_i915_perf_oa_config. If the following
+ * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
+ * write into the associated pointers the values of submitted when the
* configuration was created :
*
- * - n_mux_regs
- * - n_boolean_regs
- * - n_flex_regs
+ * - &drm_i915_perf_oa_config.n_mux_regs
+ * - &drm_i915_perf_oa_config.n_boolean_regs
+ * - &drm_i915_perf_oa_config.n_flex_regs
*/
__u8 data[];
};
@@ -3128,6 +3315,16 @@ struct drm_i915_query_memory_regions {
struct drm_i915_memory_region_info regions[];
};
+/**
+ * DOC: GuC HWCONFIG blob uAPI
+ *
+ * The GuC produces a blob with information about the current device.
+ * i915 reads this blob from GuC and makes it available via this uAPI.
+ *
+ * The format and meaning of the blob content are documented in the
+ * Programmer's Reference Manual.
+ */
+
/**
* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
* extension support using struct i915_user_extension.
@@ -3144,11 +3341,40 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
- * Note that for some devices we have might have further minimum
- * page-size restrictions(larger than 4K), like for device local-memory.
- * However in general the final size here should always reflect any
- * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
- * extension to place the object in device local-memory.
+ *
+ * DG2 64K min page size implications:
+ *
+ * On discrete platforms, starting from DG2, we have to contend with GTT
+ * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
+ * objects. Specifically the hardware only supports 64K or larger GTT
+ * page sizes for such memory. The kernel will already ensure that all
+ * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
+ * sizes underneath.
+ *
+ * Note that the returned size here will always reflect any required
+ * rounding up done by the kernel, i.e 4K will now become 64K on devices
+ * such as DG2.
+ *
+ * Special DG2 GTT address alignment requirement:
+ *
+ * The GTT alignment will also need to be at least 2M for such objects.
+ *
+ * Note that due to how the hardware implements 64K GTT page support, we
+ * have some further complications:
+ *
+ * 1) The entire PDE (which covers a 2MB virtual address range), must
+ * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
+ * PDE is forbidden by the hardware.
+ *
+ * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
+ * objects.
+ *
+ * To keep things simple for userland, we mandate that any GTT mappings
+ * must be aligned to and rounded up to 2MB. The kernel will internally
+ * pad them out to the next 2MB boundary. As this only wastes virtual
+ * address space and avoids userland having to copy any needlessly
+ * complicated PDE sharing scheme (coloring) and only affects DG2, this
+ * is deemed to be a good compromise.
*/
__u64 size;
/**
@@ -3282,4 +3508,4 @@ struct drm_i915_gem_create_ext_protected_content {
}
#endif
-#endif /* _I915_DRM_H_ */
+#endif /* _UAPI_I915_DRM_H_ */
--
2.36.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [igt-dev] [PATCH v3 i-g-t 1/2] include/drm-uapi: Update to latest i915_drm.h
@ 2022-06-03 0:54 ` John.C.Harrison
0 siblings, 0 replies; 10+ messages in thread
From: John.C.Harrison @ 2022-06-03 0:54 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX
From: John Harrison <John.C.Harrison@Intel.com>
Update to the latest master version of the DRM UAPI header file.
NB: Had to remove '__user' keywords as they do not appear to be
supported outside of kernel builds.
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
include/drm-uapi/i915_drm.h | 410 ++++++++++++++++++++++++++++--------
1 file changed, 318 insertions(+), 92 deletions(-)
diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index 9c9e1afa61ba..5d4166eb80a3 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -24,8 +24,8 @@
*
*/
-#ifndef _I915_DRM_H_
-#define _I915_DRM_H_
+#ifndef _UAPI_I915_DRM_H_
+#define _UAPI_I915_DRM_H_
#include "drm.h"
@@ -75,7 +75,7 @@ extern "C" {
* redefine the interface more easily than an ever growing struct of
* increasing complexity, and for large parts of that interface to be
* entirely optional. The downside is more pointer chasing; chasing across
- * the boundary with pointers encapsulated inside u64.
+ * the __user boundary with pointers encapsulated inside u64.
*
* Example chaining:
*
@@ -154,25 +154,77 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
};
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
* Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role. This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
*/
enum drm_i915_gem_engine_class {
+ /**
+ * @I915_ENGINE_CLASS_RENDER:
+ *
+ * Render engines support instructions used for 3D, Compute (GPGPU),
+ * and programmable media workloads. These instructions fetch data and
+ * dispatch individual work items to threads that operate in parallel.
+ * The threads run small programs (called "kernels" or "shaders") on
+ * the GPU's execution units (EUs).
+ */
I915_ENGINE_CLASS_RENDER = 0,
+
+ /**
+ * @I915_ENGINE_CLASS_COPY:
+ *
+ * Copy engines (also referred to as "blitters") support instructions
+ * that move blocks of data from one location in memory to another,
+ * or that fill a specified location of memory with fixed data.
+ * Copy engines can perform pre-defined logical or bitwise operations
+ * on the source, destination, or pattern data.
+ */
I915_ENGINE_CLASS_COPY = 1,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO:
+ *
+ * Video engines (also referred to as "bit stream decode" (BSD) or
+ * "vdbox") support instructions that perform fixed-function media
+ * decode and encode.
+ */
I915_ENGINE_CLASS_VIDEO = 2,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ *
+ * Video enhancement engines (also referred to as "vebox") support
+ * instructions related to image enhancement.
+ */
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
+ /**
+ * @I915_ENGINE_CLASS_COMPUTE:
+ *
+ * Compute engines support a subset of the instructions available
+ * on render engines: compute engines support Compute (GPGPU) and
+ * programmable media workloads, but do not support the 3D pipeline.
+ */
+ I915_ENGINE_CLASS_COMPUTE = 4,
+
+ /* Values in this enum should be kept compact. */
+ /**
+ * @I915_ENGINE_CLASS_INVALID:
+ *
+ * Placeholder value to represent an invalid engine class assignment.
+ */
I915_ENGINE_CLASS_INVALID = -1
};
-/*
+/**
+ * struct i915_engine_class_instance - Engine class/instance identifier
+ *
* There may be more than one engine fulfilling any role within the system.
* Each engine of a class is given a unique instance number and therefore
* any engine can be specified by its class:instance tuplet. APIs that allow
@@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
* for this identification.
*/
struct i915_engine_class_instance {
- __u16 engine_class; /* see enum drm_i915_gem_engine_class */
- __u16 engine_instance;
+ /**
+ * @engine_class:
+ *
+ * Engine class from enum drm_i915_gem_engine_class
+ */
+ __u16 engine_class;
#define I915_ENGINE_CLASS_INVALID_NONE -1
#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
+
+ /**
+ * @engine_instance:
+ *
+ * Engine instance.
+ */
+ __u16 engine_instance;
};
/**
@@ -1118,10 +1181,16 @@ struct drm_i915_gem_exec_object2 {
/**
* When the EXEC_OBJECT_PINNED flag is specified this is populated by
* the user with the GTT offset at which this object will be pinned.
+ *
* When the I915_EXEC_NO_RELOC flag is specified this must contain the
* presumed_offset of the object.
+ *
* During execbuffer2 the kernel populates it with the value of the
* current GTT offset of the object, for future presumed_offset writes.
+ *
+ * See struct drm_i915_gem_create_ext for the rules when dealing with
+ * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
+ * minimum page sizes, like DG2.
*/
__u64 offset;
@@ -2221,7 +2290,7 @@ struct i915_context_engines_parallel_submit {
*/
struct i915_engine_class_instance engines[0];
-} __attribute__((packed));
+} __packed;
#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
struct i915_user_extension base; \
@@ -2594,7 +2663,7 @@ struct drm_i915_perf_open_param {
* Change metrics_set captured by a stream.
*
* If the stream is bound to a specific context, the configuration change
- * will performed __inline__ with that context such that it takes effect before
+ * will performed inline with that context such that it takes effect before
* the next execbuf submission.
*
* Returns the previously bound metrics set id, or a negative error code.
@@ -2651,24 +2720,65 @@ enum drm_i915_perf_record_type {
DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
-/*
+/**
+ * struct drm_i915_perf_oa_config
+ *
* Structure to upload perf dynamic configuration into the kernel.
*/
struct drm_i915_perf_oa_config {
- /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
+ /**
+ * @uuid:
+ *
+ * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
+ */
char uuid[36];
+ /**
+ * @n_mux_regs:
+ *
+ * Number of mux regs in &mux_regs_ptr.
+ */
__u32 n_mux_regs;
+
+ /**
+ * @n_boolean_regs:
+ *
+ * Number of boolean regs in &boolean_regs_ptr.
+ */
__u32 n_boolean_regs;
+
+ /**
+ * @n_flex_regs:
+ *
+ * Number of flex regs in &flex_regs_ptr.
+ */
__u32 n_flex_regs;
- /*
- * These fields are pointers to tuples of u32 values (register address,
- * value). For example the expected length of the buffer pointed by
- * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
+ /**
+ * @mux_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_mux_regs).
*/
__u64 mux_regs_ptr;
+
+ /**
+ * @boolean_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_boolean_regs).
+ */
__u64 boolean_regs_ptr;
+
+ /**
+ * @flex_regs_ptr:
+ *
+ * Pointer to tuples of u32 values (register address, value) for mux
+ * registers. Expected length of buffer is (2 * sizeof(u32) *
+ * &n_flex_regs).
+ */
__u64 flex_regs_ptr;
};
@@ -2679,12 +2789,24 @@ struct drm_i915_perf_oa_config {
* @data_ptr is also depends on the specific @query_id.
*/
struct drm_i915_query_item {
- /** @query_id: The id for this query */
+ /**
+ * @query_id:
+ *
+ * The id for this query. Currently accepted query IDs are:
+ * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
+ * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
+ * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
+ * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
+ * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
+ * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
+ */
__u64 query_id;
-#define DRM_I915_QUERY_TOPOLOGY_INFO 1
-#define DRM_I915_QUERY_ENGINE_INFO 2
-#define DRM_I915_QUERY_PERF_CONFIG 3
-#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_TOPOLOGY_INFO 1
+#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_PERF_CONFIG 3
+#define DRM_I915_QUERY_MEMORY_REGIONS 4
+#define DRM_I915_QUERY_HWCONFIG_BLOB 5
+#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
/* Must be kept compact -- no holes and well documented */
/**
@@ -2700,14 +2822,17 @@ struct drm_i915_query_item {
/**
* @flags:
*
- * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+ * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+ * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
* following:
*
- * - DRM_I915_QUERY_PERF_CONFIG_LIST
- * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
- * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+ * - %DRM_I915_QUERY_PERF_CONFIG_LIST
+ * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+ * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
+ *
+ * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
+ * a struct i915_engine_class_instance that references a render engine.
*/
__u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
@@ -2765,66 +2890,112 @@ struct drm_i915_query {
__u64 items_ptr;
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
- *
- * data: contains the 3 pieces of information :
- *
- * - the slice mask with one bit per slice telling whether a slice is
- * available. The availability of slice X can be queried with the following
- * formula :
- *
- * (data[X / 8] >> (X % 8)) & 1
- *
- * - the subslice mask for each slice with one bit per subslice telling
- * whether a subslice is available. Gen12 has dual-subslices, which are
- * similar to two gen11 subslices. For gen12, this array represents dual-
- * subslices. The availability of subslice Y in slice X can be queried
- * with the following formula :
- *
- * (data[subslice_offset +
- * X * subslice_stride +
- * Y / 8] >> (Y % 8)) & 1
- *
- * - the EU mask for each subslice in each slice with one bit per EU telling
- * whether an EU is available. The availability of EU Z in subslice Y in
- * slice X can be queried with the following formula :
+/**
+ * struct drm_i915_query_topology_info
*
- * (data[eu_offset +
- * (X * max_subslices + Y) * eu_stride +
- * Z / 8] >> (Z % 8)) & 1
+ * Describes slice/subslice/EU information queried by
+ * %DRM_I915_QUERY_TOPOLOGY_INFO
*/
struct drm_i915_query_topology_info {
- /*
+ /**
+ * @flags:
+ *
* Unused for now. Must be cleared to zero.
*/
__u16 flags;
+ /**
+ * @max_slices:
+ *
+ * The number of bits used to express the slice mask.
+ */
__u16 max_slices;
+
+ /**
+ * @max_subslices:
+ *
+ * The number of bits used to express the subslice mask.
+ */
__u16 max_subslices;
+
+ /**
+ * @max_eus_per_subslice:
+ *
+ * The number of bits in the EU mask that correspond to a single
+ * subslice's EUs.
+ */
__u16 max_eus_per_subslice;
- /*
+ /**
+ * @subslice_offset:
+ *
* Offset in data[] at which the subslice masks are stored.
*/
__u16 subslice_offset;
- /*
+ /**
+ * @subslice_stride:
+ *
* Stride at which each of the subslice masks for each slice are
* stored.
*/
__u16 subslice_stride;
- /*
+ /**
+ * @eu_offset:
+ *
* Offset in data[] at which the EU masks are stored.
*/
__u16 eu_offset;
- /*
+ /**
+ * @eu_stride:
+ *
* Stride at which each of the EU masks for each subslice are stored.
*/
__u16 eu_stride;
+ /**
+ * @data:
+ *
+ * Contains 3 pieces of information :
+ *
+ * - The slice mask with one bit per slice telling whether a slice is
+ * available. The availability of slice X can be queried with the
+ * following formula :
+ *
+ * .. code:: c
+ *
+ * (data[X / 8] >> (X % 8)) & 1
+ *
+ * Starting with Xe_HP platforms, Intel hardware no longer has
+ * traditional slices so i915 will always report a single slice
+ * (hardcoded slicemask = 0x1) which contains all of the platform's
+ * subslices. I.e., the mask here does not reflect any of the newer
+ * hardware concepts such as "gslices" or "cslices" since userspace
+ * is capable of inferring those from the subslice mask.
+ *
+ * - The subslice mask for each slice with one bit per subslice telling
+ * whether a subslice is available. Starting with Gen12 we use the
+ * term "subslice" to refer to what the hardware documentation
+ * describes as a "dual-subslices." The availability of subslice Y
+ * in slice X can be queried with the following formula :
+ *
+ * .. code:: c
+ *
+ * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
+ *
+ * - The EU mask for each subslice in each slice, with one bit per EU
+ * telling whether an EU is available. The availability of EU Z in
+ * subslice Y in slice X can be queried with the following formula :
+ *
+ * .. code:: c
+ *
+ * (data[eu_offset +
+ * (X * max_subslices + Y) * eu_stride +
+ * Z / 8
+ * ] >> (Z % 8)) & 1
+ */
__u8 data[];
};
@@ -2945,52 +3116,68 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
-/*
- * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+/**
+ * struct drm_i915_query_perf_config
+ *
+ * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
+ * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
*/
struct drm_i915_query_perf_config {
union {
- /*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
- * this fields to the number of configurations available.
+ /**
+ * @n_configs:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
+ * the number of configurations available.
*/
__u64 n_configs;
- /*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
- * i915 will use the value in this field as configuration
- * identifier to decide what data to write into config_ptr.
+ /**
+ * @config:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
+ * value in this field as configuration identifier to decide
+ * what data to write into config_ptr.
*/
__u64 config;
- /*
- * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
- * i915 will use the value in this field as configuration
- * identifier to decide what data to write into config_ptr.
+ /**
+ * @uuid:
+ *
+ * When &drm_i915_query_item.flags ==
+ * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
+ * value in this field as configuration identifier to decide
+ * what data to write into config_ptr.
*
* String formatted like "%08x-%04x-%04x-%04x-%012x"
*/
char uuid[36];
};
- /*
+ /**
+ * @flags:
+ *
* Unused for now. Must be cleared to zero.
*/
__u32 flags;
- /*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
- * write an array of __u64 of configuration identifiers.
+ /**
+ * @data:
*
- * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
- * write a struct drm_i915_perf_oa_config. If the following fields of
- * drm_i915_perf_oa_config are set not set to 0, i915 will write into
- * the associated pointers the values of submitted when the
+ * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
+ * i915 will write an array of __u64 of configuration identifiers.
+ *
+ * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
+ * i915 will write a struct drm_i915_perf_oa_config. If the following
+ * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
+ * write into the associated pointers the values of submitted when the
* configuration was created :
*
- * - n_mux_regs
- * - n_boolean_regs
- * - n_flex_regs
+ * - &drm_i915_perf_oa_config.n_mux_regs
+ * - &drm_i915_perf_oa_config.n_boolean_regs
+ * - &drm_i915_perf_oa_config.n_flex_regs
*/
__u8 data[];
};
@@ -3128,6 +3315,16 @@ struct drm_i915_query_memory_regions {
struct drm_i915_memory_region_info regions[];
};
+/**
+ * DOC: GuC HWCONFIG blob uAPI
+ *
+ * The GuC produces a blob with information about the current device.
+ * i915 reads this blob from GuC and makes it available via this uAPI.
+ *
+ * The format and meaning of the blob content are documented in the
+ * Programmer's Reference Manual.
+ */
+
/**
* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
* extension support using struct i915_user_extension.
@@ -3144,11 +3341,40 @@ struct drm_i915_gem_create_ext {
*
* The (page-aligned) allocated size for the object will be returned.
*
- * Note that for some devices we have might have further minimum
- * page-size restrictions(larger than 4K), like for device local-memory.
- * However in general the final size here should always reflect any
- * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
- * extension to place the object in device local-memory.
+ *
+ * DG2 64K min page size implications:
+ *
+ * On discrete platforms, starting from DG2, we have to contend with GTT
+ * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
+ * objects. Specifically the hardware only supports 64K or larger GTT
+ * page sizes for such memory. The kernel will already ensure that all
+ * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
+ * sizes underneath.
+ *
+ * Note that the returned size here will always reflect any required
+ * rounding up done by the kernel, i.e 4K will now become 64K on devices
+ * such as DG2.
+ *
+ * Special DG2 GTT address alignment requirement:
+ *
+ * The GTT alignment will also need to be at least 2M for such objects.
+ *
+ * Note that due to how the hardware implements 64K GTT page support, we
+ * have some further complications:
+ *
+ * 1) The entire PDE (which covers a 2MB virtual address range), must
+ * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
+ * PDE is forbidden by the hardware.
+ *
+ * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
+ * objects.
+ *
+ * To keep things simple for userland, we mandate that any GTT mappings
+ * must be aligned to and rounded up to 2MB. The kernel will internally
+ * pad them out to the next 2MB boundary. As this only wastes virtual
+ * address space and avoids userland having to copy any needlessly
+ * complicated PDE sharing scheme (coloring) and only affects DG2, this
+ * is deemed to be a good compromise.
*/
__u64 size;
/**
@@ -3282,4 +3508,4 @@ struct drm_i915_gem_create_ext_protected_content {
}
#endif
-#endif /* _I915_DRM_H_ */
+#endif /* _UAPI_I915_DRM_H_ */
--
2.36.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table
2022-06-03 0:54 [Intel-gfx] [PATCH v3 i-g-t 0/2] Update DRM UAPI and add test for new hw info query John.C.Harrison
2022-06-03 0:54 ` [igt-dev] " John.C.Harrison
@ 2022-06-03 0:54 ` John.C.Harrison
2022-06-03 15:50 ` Kamil Konieczny
2022-06-03 3:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Update DRM UAPI and add test for new hw info query Patchwork
2022-06-03 7:44 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 1 reply; 10+ messages in thread
From: John.C.Harrison @ 2022-06-03 0:54 UTC (permalink / raw)
To: IGT-Dev; +Cc: Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Newer platforms have an embedded table giving details about that
platform's hardware configuration. This table can be retrieved from
the KMD via the existing query API. So add a test for it as both an
example of how to fetch the table and to validate the contents as much
as is possible.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
lib/intel_hwconfig_types.h | 118 ++++++++++++++++++++++++
tests/i915/i915_query.c | 179 +++++++++++++++++++++++++++++++++++++
2 files changed, 297 insertions(+)
create mode 100644 lib/intel_hwconfig_types.h
diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
new file mode 100644
index 000000000000..d5db217afba2
--- /dev/null
+++ b/lib/intel_hwconfig_types.h
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _INTEL_HWCONFIG_TYPES_H_
+#define _INTEL_HWCONFIG_TYPES_H_
+
+#include "intel_chipset.h"
+
+/**
+ * enum intel_hwconfig - Global definition of hwconfig table attributes
+ *
+ * Intel devices provide a KLV (Key/Length/Value) table containing
+ * the static hardware configuration for that platform.
+ * This enum defines the current attribute keys for this KLV.
+ */
+enum intel_hwconfig {
+ INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
+ INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
+ INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
+ INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
+ INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
+ INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
+ INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
+ INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
+ INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
+ INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
+ INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
+ INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
+ INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
+ INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
+ INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
+ INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
+ INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
+ INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
+ INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
+ INTEL_HWCONFIG_MAX_RCS, /* 23 */
+ INTEL_HWCONFIG_MAX_CCS, /* 24 */
+ INTEL_HWCONFIG_MAX_VCS, /* 25 */
+ INTEL_HWCONFIG_MAX_VECS, /* 26 */
+ INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
+ INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
+ INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
+ INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
+ INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
+ INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
+ INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
+ INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
+ INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
+ INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
+ INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
+ INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
+ INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
+ INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
+ INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
+ INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
+ INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
+ INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
+ INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
+ INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
+ INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
+ INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
+ INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
+ INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
+ INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
+ INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
+ INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
+ INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
+ INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
+ INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
+ INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
+ INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
+ INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
+ INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
+ INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
+ INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
+ INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
+ INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE, /* 74 */
+ INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK, /* 75 */
+ INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES, /* 76 */
+ INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES, /* 77 */
+ INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES, /* 78 */
+ INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES, /* 79 */
+ INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES, /* 80 */
+ __INTEL_HWCONFIG_KEY_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
+ INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
+ INTEL_HWCONFIG_MEMORY_TYPE_HBM2,
+ INTEL_HWCONFIG_MEMORY_TYPE_HBM2e,
+ INTEL_HWCONFIG_MEMORY_TYPE_GDDR6,
+ __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT
+};
+
+enum {
+ INTEL_HWCONFIG_CACHE_TYPE_L3 = 0,
+ INTEL_HWCONFIG_CACHE_TYPE_LLC,
+ INTEL_HWCONFIG_CACHE_TYPE_EDRAM,
+ __INTEL_HWCONFIG_CACHE_TYPE_LIMIT
+};
+
+#endif /* _INTEL_HWCONFIG_TYPES_H_ */
diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
index 246a979af72a..c47a74117d8d 100644
--- a/tests/i915/i915_query.c
+++ b/tests/i915/i915_query.c
@@ -22,6 +22,7 @@
*/
#include "igt.h"
+#include "intel_hwconfig_types.h"
#include <limits.h>
@@ -912,6 +913,181 @@ static void test_query_geometry_subslices(int fd)
}
}
+static const char * const hwconfig_keys[] = {
+ [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
+ [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
+ [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
+ [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
+ [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
+ [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
+ [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
+ [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
+ [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
+ [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
+ [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
+ [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
+ [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
+ [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
+ [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
+ [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
+ [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
+ [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
+ [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
+ [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
+ [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
+ [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
+ [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
+ [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
+ [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
+ [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
+ [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
+ [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
+ [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
+ [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
+ [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
+ [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
+ [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
+ [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
+ [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
+ [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
+ [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
+ [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
+ [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
+ [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
+ [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
+ [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
+ [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
+ [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
+ [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
+ [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
+ [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
+ [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
+ [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
+ [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
+ [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
+ [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
+ [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
+ [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
+ [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
+ [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
+ [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
+ [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
+ [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
+ [INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE] = "Num HBM Stacks Per Tile",
+ [INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK] = "Num Channels Per HBM Stack",
+ [INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES] = "HBM Channel Width (in bytes)",
+ [INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES] = "Min Task URB Entries",
+ [INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES] = "Max Task URB Entries",
+ [INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES] = "Min Mesh URB Entries",
+ [INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES] = "Max Mesh URB Entries",
+};
+
+static const char * const hwconfig_memtypes[] = {
+ [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4] = "LPDDR4",
+ [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5] = "LPDDR5",
+ [INTEL_HWCONFIG_MEMORY_TYPE_HBM2] = "HBM2",
+ [INTEL_HWCONFIG_MEMORY_TYPE_HBM2e] = "HBM2e",
+ [INTEL_HWCONFIG_MEMORY_TYPE_GDDR6] = "GDDR6",
+};
+
+static const char * const hwconfig_cachetypes[] = {
+ [INTEL_HWCONFIG_CACHE_TYPE_L3] = "L3",
+ [INTEL_HWCONFIG_CACHE_TYPE_LLC] = "LLC",
+ [INTEL_HWCONFIG_CACHE_TYPE_EDRAM] = "EDRAM",
+};
+
+static void query_parse_and_validate_hwconfig_table(int i915)
+{
+ struct drm_i915_query_item item = {
+ .query_id = DRM_I915_QUERY_HWCONFIG_BLOB,
+ };
+ uint32_t *data, value;
+ int i = 0;
+ int len, j, max_words, table_size;
+
+ igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_KEY_LIMIT);
+ igt_assert(ARRAY_SIZE(hwconfig_memtypes) == __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
+ igt_assert(ARRAY_SIZE(hwconfig_cachetypes) == __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
+
+ i915_query_items(i915, &item, 1);
+ table_size = item.length;
+ igt_require(table_size > 0);
+
+ data = malloc(table_size);
+ igt_assert(data);
+ memset(data, 0, table_size);
+ item.data_ptr = to_user_pointer(data);
+
+ i915_query_items(i915, &item, 1);
+ igt_assert(item.length == table_size);
+ igt_info("Table size = %d bytes\n", table_size);
+ igt_assert(table_size > 0);
+
+ /* HWConfig table is a list of KLV sets */
+ max_words = table_size / sizeof(uint32_t);
+ igt_assert(max_words * sizeof(uint32_t) == table_size);
+ while (i < max_words) {
+ /* Attribute ID zero is invalid */
+ igt_assert(data[i] > 0);
+ igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT);
+
+ len = data[i + 1];
+ igt_assert(len > 0);
+ igt_assert((i + 2 + len) <= max_words);
+
+ igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
+
+ value = data[i + 2];
+ switch (data[i]) {
+ case INTEL_HWCONFIG_MEMORY_TYPE:
+ igt_assert(len == 1);
+ igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
+ igt_info("%s\n", hwconfig_memtypes[value]);
+ break;
+
+ case INTEL_HWCONFIG_CACHE_TYPES:
+ igt_assert(len == 1);
+
+ if (!value)
+ igt_info("-\n");
+
+ j = 0;
+ while (value) {
+ if (value & BIT(j)) {
+ value &= ~BIT(j);
+ igt_assert(j < __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
+ igt_info("%s%s", hwconfig_cachetypes[j], value ? ", " : "\n");
+ }
+ }
+ break;
+
+ default:
+ for (j = i + 2; j < i + 1 + len; j++)
+ igt_info("%d, ", data[j]);
+ igt_info("%d\n", data[j]);
+ }
+
+ /* Advance to next key */
+ i += 2 + len;
+ }
+
+ free(data);
+}
+
igt_main
{
int fd = -1;
@@ -986,6 +1162,9 @@ igt_main
engines(fd);
}
+ igt_subtest("hwconfig_table")
+ query_parse_and_validate_hwconfig_table(fd);
+
igt_fixture {
close(fd);
}
--
2.36.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Update DRM UAPI and add test for new hw info query
2022-06-03 0:54 [Intel-gfx] [PATCH v3 i-g-t 0/2] Update DRM UAPI and add test for new hw info query John.C.Harrison
2022-06-03 0:54 ` [igt-dev] " John.C.Harrison
2022-06-03 0:54 ` [Intel-gfx] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
@ 2022-06-03 3:46 ` Patchwork
2022-06-03 7:44 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-06-03 3:46 UTC (permalink / raw)
To: john.c.harrison; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 5650 bytes --]
== Series Details ==
Series: Update DRM UAPI and add test for new hw info query
URL : https://patchwork.freedesktop.org/series/104693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11724 -> IGTPW_7219
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/index.html
Participating hosts (42 -> 40)
------------------------------
Additional (1): fi-kbl-soraka
Missing (3): fi-hsw-4770 bat-dg2-9 bat-atsm-1
Known issues
------------
Here are the changes found in IGTPW_7219 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@gem:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-pnv-d510/igt@i915_selftest@live@gem.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][5] ([i915#4494] / [i915#4957])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][6] -> [DMESG-FAIL][7] ([i915#4528])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/fi-blb-e6850/igt@i915_selftest@live@requests.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg1-6: NOTRUN -> [INCOMPLETE][8] ([i915#6011])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/bat-dg1-6/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +7 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-kbl-soraka/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +9 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [INCOMPLETE][12] ([i915#4418]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [DMESG-FAIL][14] ([i915#4528]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/fi-pnv-d510/igt@i915_selftest@live@requests.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/fi-pnv-d510/igt@i915_selftest@live@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5356]: https://gitlab.freedesktop.org/drm/intel/issues/5356
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6505 -> IGTPW_7219
CI-20190529: 20190529
CI_DRM_11724: d85a4921e88b2c0c5c61ab452aa302a969e108e3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7219: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/index.html
IGT_6505: edb1a467fb622b23b927e28ff603fa43851fea97 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Testlist changes
----------------
+igt@i915_query@hwconfig_table
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/index.html
[-- Attachment #2: Type: text/html, Size: 6609 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH v3 i-g-t 1/2] include/drm-uapi: Update to latest i915_drm.h
2022-06-03 0:54 ` [igt-dev] " John.C.Harrison
@ 2022-06-03 7:25 ` Petri Latvala
-1 siblings, 0 replies; 10+ messages in thread
From: Petri Latvala @ 2022-06-03 7:25 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX
On Thu, Jun 02, 2022 at 05:54:03PM -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Update to the latest master version of the DRM UAPI header file.
>
> NB: Had to remove '__user' keywords as they do not appear to be
> supported outside of kernel builds.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> include/drm-uapi/i915_drm.h | 410 ++++++++++++++++++++++++++++--------
> 1 file changed, 318 insertions(+), 92 deletions(-)
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 9c9e1afa61ba..5d4166eb80a3 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -24,8 +24,8 @@
> *
> */
>
> -#ifndef _I915_DRM_H_
> -#define _I915_DRM_H_
> +#ifndef _UAPI_I915_DRM_H_
> +#define _UAPI_I915_DRM_H_
This and the note about having to remove __user tells me you didn't
get this header through `make headers_install`.
Also please include the used kernel sha in the commit message.
I tried to replicate this with the current drm-tip version and there
are some differences. Most probably because of not using
headers_install for this patch. I don't know what branch 'master
version' refers to.
--
Petri Latvala
>
> #include "drm.h"
>
> @@ -75,7 +75,7 @@ extern "C" {
> * redefine the interface more easily than an ever growing struct of
> * increasing complexity, and for large parts of that interface to be
> * entirely optional. The downside is more pointer chasing; chasing across
> - * the boundary with pointers encapsulated inside u64.
> + * the __user boundary with pointers encapsulated inside u64.
> *
> * Example chaining:
> *
> @@ -154,25 +154,77 @@ enum i915_mocs_table_index {
> I915_MOCS_CACHED,
> };
>
> -/*
> +/**
> + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> + *
> * Different engines serve different roles, and there may be more than one
> - * engine serving each role. enum drm_i915_gem_engine_class provides a
> - * classification of the role of the engine, which may be used when requesting
> - * operations to be performed on a certain subset of engines, or for providing
> - * information about that group.
> + * engine serving each role. This enum provides a classification of the role
> + * of the engine, which may be used when requesting operations to be performed
> + * on a certain subset of engines, or for providing information about that
> + * group.
> */
> enum drm_i915_gem_engine_class {
> + /**
> + * @I915_ENGINE_CLASS_RENDER:
> + *
> + * Render engines support instructions used for 3D, Compute (GPGPU),
> + * and programmable media workloads. These instructions fetch data and
> + * dispatch individual work items to threads that operate in parallel.
> + * The threads run small programs (called "kernels" or "shaders") on
> + * the GPU's execution units (EUs).
> + */
> I915_ENGINE_CLASS_RENDER = 0,
> +
> + /**
> + * @I915_ENGINE_CLASS_COPY:
> + *
> + * Copy engines (also referred to as "blitters") support instructions
> + * that move blocks of data from one location in memory to another,
> + * or that fill a specified location of memory with fixed data.
> + * Copy engines can perform pre-defined logical or bitwise operations
> + * on the source, destination, or pattern data.
> + */
> I915_ENGINE_CLASS_COPY = 1,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO:
> + *
> + * Video engines (also referred to as "bit stream decode" (BSD) or
> + * "vdbox") support instructions that perform fixed-function media
> + * decode and encode.
> + */
> I915_ENGINE_CLASS_VIDEO = 2,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> + *
> + * Video enhancement engines (also referred to as "vebox") support
> + * instructions related to image enhancement.
> + */
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
>
> - /* should be kept compact */
> + /**
> + * @I915_ENGINE_CLASS_COMPUTE:
> + *
> + * Compute engines support a subset of the instructions available
> + * on render engines: compute engines support Compute (GPGPU) and
> + * programmable media workloads, but do not support the 3D pipeline.
> + */
> + I915_ENGINE_CLASS_COMPUTE = 4,
> +
> + /* Values in this enum should be kept compact. */
>
> + /**
> + * @I915_ENGINE_CLASS_INVALID:
> + *
> + * Placeholder value to represent an invalid engine class assignment.
> + */
> I915_ENGINE_CLASS_INVALID = -1
> };
>
> -/*
> +/**
> + * struct i915_engine_class_instance - Engine class/instance identifier
> + *
> * There may be more than one engine fulfilling any role within the system.
> * Each engine of a class is given a unique instance number and therefore
> * any engine can be specified by its class:instance tuplet. APIs that allow
> @@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
> * for this identification.
> */
> struct i915_engine_class_instance {
> - __u16 engine_class; /* see enum drm_i915_gem_engine_class */
> - __u16 engine_instance;
> + /**
> + * @engine_class:
> + *
> + * Engine class from enum drm_i915_gem_engine_class
> + */
> + __u16 engine_class;
> #define I915_ENGINE_CLASS_INVALID_NONE -1
> #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
> +
> + /**
> + * @engine_instance:
> + *
> + * Engine instance.
> + */
> + __u16 engine_instance;
> };
>
> /**
> @@ -1118,10 +1181,16 @@ struct drm_i915_gem_exec_object2 {
> /**
> * When the EXEC_OBJECT_PINNED flag is specified this is populated by
> * the user with the GTT offset at which this object will be pinned.
> + *
> * When the I915_EXEC_NO_RELOC flag is specified this must contain the
> * presumed_offset of the object.
> + *
> * During execbuffer2 the kernel populates it with the value of the
> * current GTT offset of the object, for future presumed_offset writes.
> + *
> + * See struct drm_i915_gem_create_ext for the rules when dealing with
> + * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
> + * minimum page sizes, like DG2.
> */
> __u64 offset;
>
> @@ -2221,7 +2290,7 @@ struct i915_context_engines_parallel_submit {
> */
> struct i915_engine_class_instance engines[0];
>
> -} __attribute__((packed));
> +} __packed;
>
> #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
> struct i915_user_extension base; \
> @@ -2594,7 +2663,7 @@ struct drm_i915_perf_open_param {
> * Change metrics_set captured by a stream.
> *
> * If the stream is bound to a specific context, the configuration change
> - * will performed __inline__ with that context such that it takes effect before
> + * will performed inline with that context such that it takes effect before
> * the next execbuf submission.
> *
> * Returns the previously bound metrics set id, or a negative error code.
> @@ -2651,24 +2720,65 @@ enum drm_i915_perf_record_type {
> DRM_I915_PERF_RECORD_MAX /* non-ABI */
> };
>
> -/*
> +/**
> + * struct drm_i915_perf_oa_config
> + *
> * Structure to upload perf dynamic configuration into the kernel.
> */
> struct drm_i915_perf_oa_config {
> - /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
> + /**
> + * @uuid:
> + *
> + * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
> + */
> char uuid[36];
>
> + /**
> + * @n_mux_regs:
> + *
> + * Number of mux regs in &mux_regs_ptr.
> + */
> __u32 n_mux_regs;
> +
> + /**
> + * @n_boolean_regs:
> + *
> + * Number of boolean regs in &boolean_regs_ptr.
> + */
> __u32 n_boolean_regs;
> +
> + /**
> + * @n_flex_regs:
> + *
> + * Number of flex regs in &flex_regs_ptr.
> + */
> __u32 n_flex_regs;
>
> - /*
> - * These fields are pointers to tuples of u32 values (register address,
> - * value). For example the expected length of the buffer pointed by
> - * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
> + /**
> + * @mux_regs_ptr:
> + *
> + * Pointer to tuples of u32 values (register address, value) for mux
> + * registers. Expected length of buffer is (2 * sizeof(u32) *
> + * &n_mux_regs).
> */
> __u64 mux_regs_ptr;
> +
> + /**
> + * @boolean_regs_ptr:
> + *
> + * Pointer to tuples of u32 values (register address, value) for mux
> + * registers. Expected length of buffer is (2 * sizeof(u32) *
> + * &n_boolean_regs).
> + */
> __u64 boolean_regs_ptr;
> +
> + /**
> + * @flex_regs_ptr:
> + *
> + * Pointer to tuples of u32 values (register address, value) for mux
> + * registers. Expected length of buffer is (2 * sizeof(u32) *
> + * &n_flex_regs).
> + */
> __u64 flex_regs_ptr;
> };
>
> @@ -2679,12 +2789,24 @@ struct drm_i915_perf_oa_config {
> * @data_ptr is also depends on the specific @query_id.
> */
> struct drm_i915_query_item {
> - /** @query_id: The id for this query */
> + /**
> + * @query_id:
> + *
> + * The id for this query. Currently accepted query IDs are:
> + * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
> + * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
> + * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
> + * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
> + * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
> + * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
> + */
> __u64 query_id;
> -#define DRM_I915_QUERY_TOPOLOGY_INFO 1
> -#define DRM_I915_QUERY_ENGINE_INFO 2
> -#define DRM_I915_QUERY_PERF_CONFIG 3
> -#define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_TOPOLOGY_INFO 1
> +#define DRM_I915_QUERY_ENGINE_INFO 2
> +#define DRM_I915_QUERY_PERF_CONFIG 3
> +#define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_BLOB 5
> +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
> /* Must be kept compact -- no holes and well documented */
>
> /**
> @@ -2700,14 +2822,17 @@ struct drm_i915_query_item {
> /**
> * @flags:
> *
> - * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
> + * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
> *
> - * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
> + * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
> * following:
> *
> - * - DRM_I915_QUERY_PERF_CONFIG_LIST
> - * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> - * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> + * - %DRM_I915_QUERY_PERF_CONFIG_LIST
> + * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> + * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> + *
> + * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
> + * a struct i915_engine_class_instance that references a render engine.
> */
> __u32 flags;
> #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
> @@ -2765,66 +2890,112 @@ struct drm_i915_query {
> __u64 items_ptr;
> };
>
> -/*
> - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> - *
> - * data: contains the 3 pieces of information :
> - *
> - * - the slice mask with one bit per slice telling whether a slice is
> - * available. The availability of slice X can be queried with the following
> - * formula :
> - *
> - * (data[X / 8] >> (X % 8)) & 1
> - *
> - * - the subslice mask for each slice with one bit per subslice telling
> - * whether a subslice is available. Gen12 has dual-subslices, which are
> - * similar to two gen11 subslices. For gen12, this array represents dual-
> - * subslices. The availability of subslice Y in slice X can be queried
> - * with the following formula :
> - *
> - * (data[subslice_offset +
> - * X * subslice_stride +
> - * Y / 8] >> (Y % 8)) & 1
> - *
> - * - the EU mask for each subslice in each slice with one bit per EU telling
> - * whether an EU is available. The availability of EU Z in subslice Y in
> - * slice X can be queried with the following formula :
> +/**
> + * struct drm_i915_query_topology_info
> *
> - * (data[eu_offset +
> - * (X * max_subslices + Y) * eu_stride +
> - * Z / 8] >> (Z % 8)) & 1
> + * Describes slice/subslice/EU information queried by
> + * %DRM_I915_QUERY_TOPOLOGY_INFO
> */
> struct drm_i915_query_topology_info {
> - /*
> + /**
> + * @flags:
> + *
> * Unused for now. Must be cleared to zero.
> */
> __u16 flags;
>
> + /**
> + * @max_slices:
> + *
> + * The number of bits used to express the slice mask.
> + */
> __u16 max_slices;
> +
> + /**
> + * @max_subslices:
> + *
> + * The number of bits used to express the subslice mask.
> + */
> __u16 max_subslices;
> +
> + /**
> + * @max_eus_per_subslice:
> + *
> + * The number of bits in the EU mask that correspond to a single
> + * subslice's EUs.
> + */
> __u16 max_eus_per_subslice;
>
> - /*
> + /**
> + * @subslice_offset:
> + *
> * Offset in data[] at which the subslice masks are stored.
> */
> __u16 subslice_offset;
>
> - /*
> + /**
> + * @subslice_stride:
> + *
> * Stride at which each of the subslice masks for each slice are
> * stored.
> */
> __u16 subslice_stride;
>
> - /*
> + /**
> + * @eu_offset:
> + *
> * Offset in data[] at which the EU masks are stored.
> */
> __u16 eu_offset;
>
> - /*
> + /**
> + * @eu_stride:
> + *
> * Stride at which each of the EU masks for each subslice are stored.
> */
> __u16 eu_stride;
>
> + /**
> + * @data:
> + *
> + * Contains 3 pieces of information :
> + *
> + * - The slice mask with one bit per slice telling whether a slice is
> + * available. The availability of slice X can be queried with the
> + * following formula :
> + *
> + * .. code:: c
> + *
> + * (data[X / 8] >> (X % 8)) & 1
> + *
> + * Starting with Xe_HP platforms, Intel hardware no longer has
> + * traditional slices so i915 will always report a single slice
> + * (hardcoded slicemask = 0x1) which contains all of the platform's
> + * subslices. I.e., the mask here does not reflect any of the newer
> + * hardware concepts such as "gslices" or "cslices" since userspace
> + * is capable of inferring those from the subslice mask.
> + *
> + * - The subslice mask for each slice with one bit per subslice telling
> + * whether a subslice is available. Starting with Gen12 we use the
> + * term "subslice" to refer to what the hardware documentation
> + * describes as a "dual-subslices." The availability of subslice Y
> + * in slice X can be queried with the following formula :
> + *
> + * .. code:: c
> + *
> + * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
> + *
> + * - The EU mask for each subslice in each slice, with one bit per EU
> + * telling whether an EU is available. The availability of EU Z in
> + * subslice Y in slice X can be queried with the following formula :
> + *
> + * .. code:: c
> + *
> + * (data[eu_offset +
> + * (X * max_subslices + Y) * eu_stride +
> + * Z / 8
> + * ] >> (Z % 8)) & 1
> + */
> __u8 data[];
> };
>
> @@ -2945,52 +3116,68 @@ struct drm_i915_query_engine_info {
> struct drm_i915_engine_info engines[];
> };
>
> -/*
> - * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
> +/**
> + * struct drm_i915_query_perf_config
> + *
> + * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
> + * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
> */
> struct drm_i915_query_perf_config {
> union {
> - /*
> - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
> - * this fields to the number of configurations available.
> + /**
> + * @n_configs:
> + *
> + * When &drm_i915_query_item.flags ==
> + * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
> + * the number of configurations available.
> */
> __u64 n_configs;
>
> - /*
> - * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
> - * i915 will use the value in this field as configuration
> - * identifier to decide what data to write into config_ptr.
> + /**
> + * @config:
> + *
> + * When &drm_i915_query_item.flags ==
> + * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
> + * value in this field as configuration identifier to decide
> + * what data to write into config_ptr.
> */
> __u64 config;
>
> - /*
> - * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
> - * i915 will use the value in this field as configuration
> - * identifier to decide what data to write into config_ptr.
> + /**
> + * @uuid:
> + *
> + * When &drm_i915_query_item.flags ==
> + * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
> + * value in this field as configuration identifier to decide
> + * what data to write into config_ptr.
> *
> * String formatted like "%08x-%04x-%04x-%04x-%012x"
> */
> char uuid[36];
> };
>
> - /*
> + /**
> + * @flags:
> + *
> * Unused for now. Must be cleared to zero.
> */
> __u32 flags;
>
> - /*
> - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
> - * write an array of __u64 of configuration identifiers.
> + /**
> + * @data:
> *
> - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
> - * write a struct drm_i915_perf_oa_config. If the following fields of
> - * drm_i915_perf_oa_config are set not set to 0, i915 will write into
> - * the associated pointers the values of submitted when the
> + * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
> + * i915 will write an array of __u64 of configuration identifiers.
> + *
> + * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
> + * i915 will write a struct drm_i915_perf_oa_config. If the following
> + * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
> + * write into the associated pointers the values of submitted when the
> * configuration was created :
> *
> - * - n_mux_regs
> - * - n_boolean_regs
> - * - n_flex_regs
> + * - &drm_i915_perf_oa_config.n_mux_regs
> + * - &drm_i915_perf_oa_config.n_boolean_regs
> + * - &drm_i915_perf_oa_config.n_flex_regs
> */
> __u8 data[];
> };
> @@ -3128,6 +3315,16 @@ struct drm_i915_query_memory_regions {
> struct drm_i915_memory_region_info regions[];
> };
>
> +/**
> + * DOC: GuC HWCONFIG blob uAPI
> + *
> + * The GuC produces a blob with information about the current device.
> + * i915 reads this blob from GuC and makes it available via this uAPI.
> + *
> + * The format and meaning of the blob content are documented in the
> + * Programmer's Reference Manual.
> + */
> +
> /**
> * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
> * extension support using struct i915_user_extension.
> @@ -3144,11 +3341,40 @@ struct drm_i915_gem_create_ext {
> *
> * The (page-aligned) allocated size for the object will be returned.
> *
> - * Note that for some devices we have might have further minimum
> - * page-size restrictions(larger than 4K), like for device local-memory.
> - * However in general the final size here should always reflect any
> - * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
> - * extension to place the object in device local-memory.
> + *
> + * DG2 64K min page size implications:
> + *
> + * On discrete platforms, starting from DG2, we have to contend with GTT
> + * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
> + * objects. Specifically the hardware only supports 64K or larger GTT
> + * page sizes for such memory. The kernel will already ensure that all
> + * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
> + * sizes underneath.
> + *
> + * Note that the returned size here will always reflect any required
> + * rounding up done by the kernel, i.e 4K will now become 64K on devices
> + * such as DG2.
> + *
> + * Special DG2 GTT address alignment requirement:
> + *
> + * The GTT alignment will also need to be at least 2M for such objects.
> + *
> + * Note that due to how the hardware implements 64K GTT page support, we
> + * have some further complications:
> + *
> + * 1) The entire PDE (which covers a 2MB virtual address range), must
> + * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
> + * PDE is forbidden by the hardware.
> + *
> + * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
> + * objects.
> + *
> + * To keep things simple for userland, we mandate that any GTT mappings
> + * must be aligned to and rounded up to 2MB. The kernel will internally
> + * pad them out to the next 2MB boundary. As this only wastes virtual
> + * address space and avoids userland having to copy any needlessly
> + * complicated PDE sharing scheme (coloring) and only affects DG2, this
> + * is deemed to be a good compromise.
> */
> __u64 size;
> /**
> @@ -3282,4 +3508,4 @@ struct drm_i915_gem_create_ext_protected_content {
> }
> #endif
>
> -#endif /* _I915_DRM_H_ */
> +#endif /* _UAPI_I915_DRM_H_ */
> --
> 2.36.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [igt-dev] [PATCH v3 i-g-t 1/2] include/drm-uapi: Update to latest i915_drm.h
@ 2022-06-03 7:25 ` Petri Latvala
0 siblings, 0 replies; 10+ messages in thread
From: Petri Latvala @ 2022-06-03 7:25 UTC (permalink / raw)
To: John.C.Harrison; +Cc: IGT-Dev, Intel-GFX
On Thu, Jun 02, 2022 at 05:54:03PM -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> Update to the latest master version of the DRM UAPI header file.
>
> NB: Had to remove '__user' keywords as they do not appear to be
> supported outside of kernel builds.
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> ---
> include/drm-uapi/i915_drm.h | 410 ++++++++++++++++++++++++++++--------
> 1 file changed, 318 insertions(+), 92 deletions(-)
>
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index 9c9e1afa61ba..5d4166eb80a3 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -24,8 +24,8 @@
> *
> */
>
> -#ifndef _I915_DRM_H_
> -#define _I915_DRM_H_
> +#ifndef _UAPI_I915_DRM_H_
> +#define _UAPI_I915_DRM_H_
This and the note about having to remove __user tells me you didn't
get this header through `make headers_install`.
Also please include the used kernel sha in the commit message.
I tried to replicate this with the current drm-tip version and there
are some differences. Most probably because of not using
headers_install for this patch. I don't know what branch 'master
version' refers to.
--
Petri Latvala
>
> #include "drm.h"
>
> @@ -75,7 +75,7 @@ extern "C" {
> * redefine the interface more easily than an ever growing struct of
> * increasing complexity, and for large parts of that interface to be
> * entirely optional. The downside is more pointer chasing; chasing across
> - * the boundary with pointers encapsulated inside u64.
> + * the __user boundary with pointers encapsulated inside u64.
> *
> * Example chaining:
> *
> @@ -154,25 +154,77 @@ enum i915_mocs_table_index {
> I915_MOCS_CACHED,
> };
>
> -/*
> +/**
> + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> + *
> * Different engines serve different roles, and there may be more than one
> - * engine serving each role. enum drm_i915_gem_engine_class provides a
> - * classification of the role of the engine, which may be used when requesting
> - * operations to be performed on a certain subset of engines, or for providing
> - * information about that group.
> + * engine serving each role. This enum provides a classification of the role
> + * of the engine, which may be used when requesting operations to be performed
> + * on a certain subset of engines, or for providing information about that
> + * group.
> */
> enum drm_i915_gem_engine_class {
> + /**
> + * @I915_ENGINE_CLASS_RENDER:
> + *
> + * Render engines support instructions used for 3D, Compute (GPGPU),
> + * and programmable media workloads. These instructions fetch data and
> + * dispatch individual work items to threads that operate in parallel.
> + * The threads run small programs (called "kernels" or "shaders") on
> + * the GPU's execution units (EUs).
> + */
> I915_ENGINE_CLASS_RENDER = 0,
> +
> + /**
> + * @I915_ENGINE_CLASS_COPY:
> + *
> + * Copy engines (also referred to as "blitters") support instructions
> + * that move blocks of data from one location in memory to another,
> + * or that fill a specified location of memory with fixed data.
> + * Copy engines can perform pre-defined logical or bitwise operations
> + * on the source, destination, or pattern data.
> + */
> I915_ENGINE_CLASS_COPY = 1,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO:
> + *
> + * Video engines (also referred to as "bit stream decode" (BSD) or
> + * "vdbox") support instructions that perform fixed-function media
> + * decode and encode.
> + */
> I915_ENGINE_CLASS_VIDEO = 2,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> + *
> + * Video enhancement engines (also referred to as "vebox") support
> + * instructions related to image enhancement.
> + */
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
>
> - /* should be kept compact */
> + /**
> + * @I915_ENGINE_CLASS_COMPUTE:
> + *
> + * Compute engines support a subset of the instructions available
> + * on render engines: compute engines support Compute (GPGPU) and
> + * programmable media workloads, but do not support the 3D pipeline.
> + */
> + I915_ENGINE_CLASS_COMPUTE = 4,
> +
> + /* Values in this enum should be kept compact. */
>
> + /**
> + * @I915_ENGINE_CLASS_INVALID:
> + *
> + * Placeholder value to represent an invalid engine class assignment.
> + */
> I915_ENGINE_CLASS_INVALID = -1
> };
>
> -/*
> +/**
> + * struct i915_engine_class_instance - Engine class/instance identifier
> + *
> * There may be more than one engine fulfilling any role within the system.
> * Each engine of a class is given a unique instance number and therefore
> * any engine can be specified by its class:instance tuplet. APIs that allow
> @@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
> * for this identification.
> */
> struct i915_engine_class_instance {
> - __u16 engine_class; /* see enum drm_i915_gem_engine_class */
> - __u16 engine_instance;
> + /**
> + * @engine_class:
> + *
> + * Engine class from enum drm_i915_gem_engine_class
> + */
> + __u16 engine_class;
> #define I915_ENGINE_CLASS_INVALID_NONE -1
> #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
> +
> + /**
> + * @engine_instance:
> + *
> + * Engine instance.
> + */
> + __u16 engine_instance;
> };
>
> /**
> @@ -1118,10 +1181,16 @@ struct drm_i915_gem_exec_object2 {
> /**
> * When the EXEC_OBJECT_PINNED flag is specified this is populated by
> * the user with the GTT offset at which this object will be pinned.
> + *
> * When the I915_EXEC_NO_RELOC flag is specified this must contain the
> * presumed_offset of the object.
> + *
> * During execbuffer2 the kernel populates it with the value of the
> * current GTT offset of the object, for future presumed_offset writes.
> + *
> + * See struct drm_i915_gem_create_ext for the rules when dealing with
> + * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
> + * minimum page sizes, like DG2.
> */
> __u64 offset;
>
> @@ -2221,7 +2290,7 @@ struct i915_context_engines_parallel_submit {
> */
> struct i915_engine_class_instance engines[0];
>
> -} __attribute__((packed));
> +} __packed;
>
> #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
> struct i915_user_extension base; \
> @@ -2594,7 +2663,7 @@ struct drm_i915_perf_open_param {
> * Change metrics_set captured by a stream.
> *
> * If the stream is bound to a specific context, the configuration change
> - * will performed __inline__ with that context such that it takes effect before
> + * will performed inline with that context such that it takes effect before
> * the next execbuf submission.
> *
> * Returns the previously bound metrics set id, or a negative error code.
> @@ -2651,24 +2720,65 @@ enum drm_i915_perf_record_type {
> DRM_I915_PERF_RECORD_MAX /* non-ABI */
> };
>
> -/*
> +/**
> + * struct drm_i915_perf_oa_config
> + *
> * Structure to upload perf dynamic configuration into the kernel.
> */
> struct drm_i915_perf_oa_config {
> - /** String formatted like "%08x-%04x-%04x-%04x-%012x" */
> + /**
> + * @uuid:
> + *
> + * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
> + */
> char uuid[36];
>
> + /**
> + * @n_mux_regs:
> + *
> + * Number of mux regs in &mux_regs_ptr.
> + */
> __u32 n_mux_regs;
> +
> + /**
> + * @n_boolean_regs:
> + *
> + * Number of boolean regs in &boolean_regs_ptr.
> + */
> __u32 n_boolean_regs;
> +
> + /**
> + * @n_flex_regs:
> + *
> + * Number of flex regs in &flex_regs_ptr.
> + */
> __u32 n_flex_regs;
>
> - /*
> - * These fields are pointers to tuples of u32 values (register address,
> - * value). For example the expected length of the buffer pointed by
> - * mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
> + /**
> + * @mux_regs_ptr:
> + *
> + * Pointer to tuples of u32 values (register address, value) for mux
> + * registers. Expected length of buffer is (2 * sizeof(u32) *
> + * &n_mux_regs).
> */
> __u64 mux_regs_ptr;
> +
> + /**
> + * @boolean_regs_ptr:
> + *
> + * Pointer to tuples of u32 values (register address, value) for mux
> + * registers. Expected length of buffer is (2 * sizeof(u32) *
> + * &n_boolean_regs).
> + */
> __u64 boolean_regs_ptr;
> +
> + /**
> + * @flex_regs_ptr:
> + *
> + * Pointer to tuples of u32 values (register address, value) for mux
> + * registers. Expected length of buffer is (2 * sizeof(u32) *
> + * &n_flex_regs).
> + */
> __u64 flex_regs_ptr;
> };
>
> @@ -2679,12 +2789,24 @@ struct drm_i915_perf_oa_config {
> * @data_ptr is also depends on the specific @query_id.
> */
> struct drm_i915_query_item {
> - /** @query_id: The id for this query */
> + /**
> + * @query_id:
> + *
> + * The id for this query. Currently accepted query IDs are:
> + * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
> + * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
> + * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
> + * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
> + * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
> + * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
> + */
> __u64 query_id;
> -#define DRM_I915_QUERY_TOPOLOGY_INFO 1
> -#define DRM_I915_QUERY_ENGINE_INFO 2
> -#define DRM_I915_QUERY_PERF_CONFIG 3
> -#define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_TOPOLOGY_INFO 1
> +#define DRM_I915_QUERY_ENGINE_INFO 2
> +#define DRM_I915_QUERY_PERF_CONFIG 3
> +#define DRM_I915_QUERY_MEMORY_REGIONS 4
> +#define DRM_I915_QUERY_HWCONFIG_BLOB 5
> +#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
> /* Must be kept compact -- no holes and well documented */
>
> /**
> @@ -2700,14 +2822,17 @@ struct drm_i915_query_item {
> /**
> * @flags:
> *
> - * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
> + * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
> *
> - * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
> + * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
> * following:
> *
> - * - DRM_I915_QUERY_PERF_CONFIG_LIST
> - * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> - * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> + * - %DRM_I915_QUERY_PERF_CONFIG_LIST
> + * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
> + * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
> + *
> + * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
> + * a struct i915_engine_class_instance that references a render engine.
> */
> __u32 flags;
> #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
> @@ -2765,66 +2890,112 @@ struct drm_i915_query {
> __u64 items_ptr;
> };
>
> -/*
> - * Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
> - *
> - * data: contains the 3 pieces of information :
> - *
> - * - the slice mask with one bit per slice telling whether a slice is
> - * available. The availability of slice X can be queried with the following
> - * formula :
> - *
> - * (data[X / 8] >> (X % 8)) & 1
> - *
> - * - the subslice mask for each slice with one bit per subslice telling
> - * whether a subslice is available. Gen12 has dual-subslices, which are
> - * similar to two gen11 subslices. For gen12, this array represents dual-
> - * subslices. The availability of subslice Y in slice X can be queried
> - * with the following formula :
> - *
> - * (data[subslice_offset +
> - * X * subslice_stride +
> - * Y / 8] >> (Y % 8)) & 1
> - *
> - * - the EU mask for each subslice in each slice with one bit per EU telling
> - * whether an EU is available. The availability of EU Z in subslice Y in
> - * slice X can be queried with the following formula :
> +/**
> + * struct drm_i915_query_topology_info
> *
> - * (data[eu_offset +
> - * (X * max_subslices + Y) * eu_stride +
> - * Z / 8] >> (Z % 8)) & 1
> + * Describes slice/subslice/EU information queried by
> + * %DRM_I915_QUERY_TOPOLOGY_INFO
> */
> struct drm_i915_query_topology_info {
> - /*
> + /**
> + * @flags:
> + *
> * Unused for now. Must be cleared to zero.
> */
> __u16 flags;
>
> + /**
> + * @max_slices:
> + *
> + * The number of bits used to express the slice mask.
> + */
> __u16 max_slices;
> +
> + /**
> + * @max_subslices:
> + *
> + * The number of bits used to express the subslice mask.
> + */
> __u16 max_subslices;
> +
> + /**
> + * @max_eus_per_subslice:
> + *
> + * The number of bits in the EU mask that correspond to a single
> + * subslice's EUs.
> + */
> __u16 max_eus_per_subslice;
>
> - /*
> + /**
> + * @subslice_offset:
> + *
> * Offset in data[] at which the subslice masks are stored.
> */
> __u16 subslice_offset;
>
> - /*
> + /**
> + * @subslice_stride:
> + *
> * Stride at which each of the subslice masks for each slice are
> * stored.
> */
> __u16 subslice_stride;
>
> - /*
> + /**
> + * @eu_offset:
> + *
> * Offset in data[] at which the EU masks are stored.
> */
> __u16 eu_offset;
>
> - /*
> + /**
> + * @eu_stride:
> + *
> * Stride at which each of the EU masks for each subslice are stored.
> */
> __u16 eu_stride;
>
> + /**
> + * @data:
> + *
> + * Contains 3 pieces of information :
> + *
> + * - The slice mask with one bit per slice telling whether a slice is
> + * available. The availability of slice X can be queried with the
> + * following formula :
> + *
> + * .. code:: c
> + *
> + * (data[X / 8] >> (X % 8)) & 1
> + *
> + * Starting with Xe_HP platforms, Intel hardware no longer has
> + * traditional slices so i915 will always report a single slice
> + * (hardcoded slicemask = 0x1) which contains all of the platform's
> + * subslices. I.e., the mask here does not reflect any of the newer
> + * hardware concepts such as "gslices" or "cslices" since userspace
> + * is capable of inferring those from the subslice mask.
> + *
> + * - The subslice mask for each slice with one bit per subslice telling
> + * whether a subslice is available. Starting with Gen12 we use the
> + * term "subslice" to refer to what the hardware documentation
> + * describes as a "dual-subslices." The availability of subslice Y
> + * in slice X can be queried with the following formula :
> + *
> + * .. code:: c
> + *
> + * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
> + *
> + * - The EU mask for each subslice in each slice, with one bit per EU
> + * telling whether an EU is available. The availability of EU Z in
> + * subslice Y in slice X can be queried with the following formula :
> + *
> + * .. code:: c
> + *
> + * (data[eu_offset +
> + * (X * max_subslices + Y) * eu_stride +
> + * Z / 8
> + * ] >> (Z % 8)) & 1
> + */
> __u8 data[];
> };
>
> @@ -2945,52 +3116,68 @@ struct drm_i915_query_engine_info {
> struct drm_i915_engine_info engines[];
> };
>
> -/*
> - * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
> +/**
> + * struct drm_i915_query_perf_config
> + *
> + * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
> + * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
> */
> struct drm_i915_query_perf_config {
> union {
> - /*
> - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
> - * this fields to the number of configurations available.
> + /**
> + * @n_configs:
> + *
> + * When &drm_i915_query_item.flags ==
> + * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
> + * the number of configurations available.
> */
> __u64 n_configs;
>
> - /*
> - * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
> - * i915 will use the value in this field as configuration
> - * identifier to decide what data to write into config_ptr.
> + /**
> + * @config:
> + *
> + * When &drm_i915_query_item.flags ==
> + * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
> + * value in this field as configuration identifier to decide
> + * what data to write into config_ptr.
> */
> __u64 config;
>
> - /*
> - * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
> - * i915 will use the value in this field as configuration
> - * identifier to decide what data to write into config_ptr.
> + /**
> + * @uuid:
> + *
> + * When &drm_i915_query_item.flags ==
> + * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
> + * value in this field as configuration identifier to decide
> + * what data to write into config_ptr.
> *
> * String formatted like "%08x-%04x-%04x-%04x-%012x"
> */
> char uuid[36];
> };
>
> - /*
> + /**
> + * @flags:
> + *
> * Unused for now. Must be cleared to zero.
> */
> __u32 flags;
>
> - /*
> - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
> - * write an array of __u64 of configuration identifiers.
> + /**
> + * @data:
> *
> - * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
> - * write a struct drm_i915_perf_oa_config. If the following fields of
> - * drm_i915_perf_oa_config are set not set to 0, i915 will write into
> - * the associated pointers the values of submitted when the
> + * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
> + * i915 will write an array of __u64 of configuration identifiers.
> + *
> + * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
> + * i915 will write a struct drm_i915_perf_oa_config. If the following
> + * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
> + * write into the associated pointers the values of submitted when the
> * configuration was created :
> *
> - * - n_mux_regs
> - * - n_boolean_regs
> - * - n_flex_regs
> + * - &drm_i915_perf_oa_config.n_mux_regs
> + * - &drm_i915_perf_oa_config.n_boolean_regs
> + * - &drm_i915_perf_oa_config.n_flex_regs
> */
> __u8 data[];
> };
> @@ -3128,6 +3315,16 @@ struct drm_i915_query_memory_regions {
> struct drm_i915_memory_region_info regions[];
> };
>
> +/**
> + * DOC: GuC HWCONFIG blob uAPI
> + *
> + * The GuC produces a blob with information about the current device.
> + * i915 reads this blob from GuC and makes it available via this uAPI.
> + *
> + * The format and meaning of the blob content are documented in the
> + * Programmer's Reference Manual.
> + */
> +
> /**
> * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
> * extension support using struct i915_user_extension.
> @@ -3144,11 +3341,40 @@ struct drm_i915_gem_create_ext {
> *
> * The (page-aligned) allocated size for the object will be returned.
> *
> - * Note that for some devices we have might have further minimum
> - * page-size restrictions(larger than 4K), like for device local-memory.
> - * However in general the final size here should always reflect any
> - * rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS
> - * extension to place the object in device local-memory.
> + *
> + * DG2 64K min page size implications:
> + *
> + * On discrete platforms, starting from DG2, we have to contend with GTT
> + * page size restrictions when dealing with I915_MEMORY_CLASS_DEVICE
> + * objects. Specifically the hardware only supports 64K or larger GTT
> + * page sizes for such memory. The kernel will already ensure that all
> + * I915_MEMORY_CLASS_DEVICE memory is allocated using 64K or larger page
> + * sizes underneath.
> + *
> + * Note that the returned size here will always reflect any required
> + * rounding up done by the kernel, i.e 4K will now become 64K on devices
> + * such as DG2.
> + *
> + * Special DG2 GTT address alignment requirement:
> + *
> + * The GTT alignment will also need to be at least 2M for such objects.
> + *
> + * Note that due to how the hardware implements 64K GTT page support, we
> + * have some further complications:
> + *
> + * 1) The entire PDE (which covers a 2MB virtual address range), must
> + * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
> + * PDE is forbidden by the hardware.
> + *
> + * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
> + * objects.
> + *
> + * To keep things simple for userland, we mandate that any GTT mappings
> + * must be aligned to and rounded up to 2MB. The kernel will internally
> + * pad them out to the next 2MB boundary. As this only wastes virtual
> + * address space and avoids userland having to copy any needlessly
> + * complicated PDE sharing scheme (coloring) and only affects DG2, this
> + * is deemed to be a good compromise.
> */
> __u64 size;
> /**
> @@ -3282,4 +3508,4 @@ struct drm_i915_gem_create_ext_protected_content {
> }
> #endif
>
> -#endif /* _I915_DRM_H_ */
> +#endif /* _UAPI_I915_DRM_H_ */
> --
> 2.36.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for Update DRM UAPI and add test for new hw info query
2022-06-03 0:54 [Intel-gfx] [PATCH v3 i-g-t 0/2] Update DRM UAPI and add test for new hw info query John.C.Harrison
` (2 preceding siblings ...)
2022-06-03 3:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Update DRM UAPI and add test for new hw info query Patchwork
@ 2022-06-03 7:44 ` Patchwork
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2022-06-03 7:44 UTC (permalink / raw)
To: john.c.harrison; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 57394 bytes --]
== Series Details ==
Series: Update DRM UAPI and add test for new hw info query
URL : https://patchwork.freedesktop.org/series/104693/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11724_full -> IGTPW_7219_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with IGTPW_7219_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_7219_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/index.html
Participating hosts (13 -> 10)
------------------------------
Missing (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_7219_full:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_query@hwconfig_table} (NEW):
- {shard-dg1}: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-12/igt@i915_query@hwconfig_table.html
- {shard-tglu}: NOTRUN -> [SKIP][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglu-3/igt@i915_query@hwconfig_table.html
- shard-tglb: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@i915_query@hwconfig_table.html
- shard-iclb: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@i915_query@hwconfig_table.html
- {shard-rkl}: NOTRUN -> [SKIP][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-rkl-4/igt@i915_query@hwconfig_table.html
#### Warnings ####
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: [FAIL][6] ([i915#454]) -> [FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl6/igt@i915_pm_dc@dc6-dpms.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl3/igt@i915_pm_dc@dc6-dpms.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_suspend@forcewake:
- {shard-rkl}: [PASS][8] -> [DMESG-WARN][9] +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-rkl-1/igt@i915_suspend@forcewake.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-rkl-5/igt@i915_suspend@forcewake.html
- {shard-tglu}: [PASS][10] -> [DMESG-WARN][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-tglu-3/igt@i915_suspend@forcewake.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglu-1/igt@i915_suspend@forcewake.html
* igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs:
- {shard-dg1}: NOTRUN -> [SKIP][12]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-16/igt@kms_ccs@pipe-a-bad-pixel-format-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_mc_ccs:
- {shard-dg1}: [SKIP][13] ([i915#6095]) -> [SKIP][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-dg1-17/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_mc_ccs.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-16/igt@kms_ccs@pipe-c-random-ccs-data-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_mc_ccs:
- {shard-dg1}: [SKIP][15] ([i915#3689]) -> [SKIP][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-dg1-13/igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_mc_ccs.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-16/igt@kms_ccs@pipe-d-crc-primary-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_color@pipe-c-invalid-degamma-lut-sizes:
- {shard-dg1}: [PASS][17] -> [WARN][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-dg1-15/igt@kms_color@pipe-c-invalid-degamma-lut-sizes.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-16/igt@kms_color@pipe-c-invalid-degamma-lut-sizes.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- {shard-dg1}: NOTRUN -> [FAIL][19] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-18/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_legacy@pipe-d-forked-move:
- {shard-dg1}: NOTRUN -> [WARN][20]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-16/igt@kms_cursor_legacy@pipe-d-forked-move.html
* igt@kms_lease@page_flip_implicit_plane:
- {shard-dg1}: [PASS][21] -> [FAIL][22] +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-dg1-12/igt@kms_lease@page_flip_implicit_plane.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-dg1-16/igt@kms_lease@page_flip_implicit_plane.html
New tests
---------
New tests have been introduced between CI_DRM_11724_full and IGTPW_7219_full:
### New IGT tests (1) ###
* igt@i915_query@hwconfig_table:
- Statuses : 9 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_7219_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-glk: NOTRUN -> [DMESG-WARN][23] ([i915#4991])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk6/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@legacy-engines-mixed-process:
- shard-snb: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#1099])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed-process.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][25] -> [SKIP][26] ([i915#4525]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb4/igt@gem_exec_balancer@parallel-out-fence.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_endless@dispatch@vcs1:
- shard-tglb: [PASS][27] -> [INCOMPLETE][28] ([i915#3778])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-tglb6/igt@gem_exec_endless@dispatch@vcs1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb6/igt@gem_exec_endless@dispatch@vcs1.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [PASS][29] -> [FAIL][30] ([i915#2842])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-kbl: NOTRUN -> [FAIL][31] ([i915#2842]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: NOTRUN -> [FAIL][32] ([i915#2842])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#2842]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_flush@basic-wb-prw-default:
- shard-snb: [PASS][35] -> [SKIP][36] ([fdo#109271]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-snb4/igt@gem_exec_flush@basic-wb-prw-default.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-snb6/igt@gem_exec_flush@basic-wb-prw-default.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][37] -> [SKIP][38] ([i915#2190])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-tglb3/igt@gem_huc_copy@huc-copy.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#4613]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#4613]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk4/igt@gem_lmem_swapping@random-engines.html
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#4613])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb7/igt@gem_lmem_swapping@random-engines.html
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#4613])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl8/igt@gem_lmem_swapping@random-engines.html
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#4613])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb5/igt@gem_lmem_swapping@random-engines.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][44] ([i915#2658])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl1/igt@gem_pread@exhaustion.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-tglb: NOTRUN -> [SKIP][45] ([i915#4270]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb1/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
- shard-iclb: NOTRUN -> [SKIP][46] ([i915#4270]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb5/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][47] ([i915#4991])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl1/igt@gem_userptr_blits@input-checking.html
* igt@gen3_render_linear_blits:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109289])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb1/igt@gen3_render_linear_blits.html
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#109289])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb2/igt@gen3_render_linear_blits.html
* igt@gen9_exec_parse@batch-without-end:
- shard-iclb: NOTRUN -> [SKIP][50] ([i915#2856])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb5/igt@gen9_exec_parse@batch-without-end.html
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#2527] / [i915#2856])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@gen9_exec_parse@batch-without-end.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][52] -> [FAIL][53] ([i915#454])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb7/igt@i915_pm_dc@dc6-dpms.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#110892])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb4/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#111644] / [i915#1397] / [i915#2411])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb3/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglb: NOTRUN -> [SKIP][56] ([fdo#109506] / [i915#2411])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb1/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#109293] / [fdo#109506])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb2/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_query@test-query-geometry-subslices:
- shard-iclb: NOTRUN -> [SKIP][58] ([i915#5723])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb4/igt@i915_query@test-query-geometry-subslices.html
- shard-tglb: NOTRUN -> [SKIP][59] ([i915#5723])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb2/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][60] -> [INCOMPLETE][61] ([i915#3921])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-snb7/igt@i915_selftest@live@hangcheck.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-snb6/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [PASS][62] -> [DMESG-WARN][63] ([i915#180]) +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl4/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_big_fb@4-tiled-addfb-size-overflow:
- shard-iclb: NOTRUN -> [SKIP][64] ([i915#5286])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb5/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#5286])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-iclb: NOTRUN -> [SKIP][66] ([fdo#110723])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#3886]) +9 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc:
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#6095])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][69] ([fdo#111615] / [i915#3689])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#3886]) +11 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl3/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs:
- shard-tglb: NOTRUN -> [SKIP][71] ([i915#3689]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb3/igt@kms_ccs@pipe-c-crc-primary-rotation-180-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][72] ([i915#3689] / [i915#3886])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb3/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
- shard-glk: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3886]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109278] / [i915#3886]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb7/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271]) +138 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl6/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-hpd-enable-disable-mode:
- shard-glk: NOTRUN -> [SKIP][76] ([fdo#109271] / [fdo#111827]) +5 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk9/igt@kms_chamelium@dp-hpd-enable-disable-mode.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-tglb: NOTRUN -> [SKIP][77] ([fdo#109284] / [fdo#111827])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb6/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109284] / [fdo#111827])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
- shard-snb: NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-snb7/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@vga-hpd-without-ddc:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [fdo#111827]) +3 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl2/igt@kms_chamelium@vga-hpd-without-ddc.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +6 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][82] ([i915#1319])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl1/igt@kms_content_protection@srm.html
- shard-apl: NOTRUN -> [TIMEOUT][83] ([i915#1319])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl7/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109278]) +12 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-max-size-rapid-movement.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [PASS][85] -> [DMESG-WARN][86] ([i915#180]) +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen:
- shard-tglb: NOTRUN -> [SKIP][87] ([i915#3359]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][88] ([i915#180]) +2 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
- shard-apl: NOTRUN -> [DMESG-WARN][89] ([i915#180])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#3319]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109279] / [i915#3359])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x512-rapid-movement.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-tglb: NOTRUN -> [SKIP][92] ([fdo#109274] / [fdo#111825]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
- shard-iclb: NOTRUN -> [SKIP][93] ([fdo#109274] / [fdo#109278])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb3/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@hdmi-a-1-pipe-a:
- shard-glk: [PASS][94] -> [SKIP][95] ([fdo#109271])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-glk7/igt@kms_dither@fb-8bpc-vs-panel-8bpc@hdmi-a-1-pipe-a.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk8/igt@kms_dither@fb-8bpc-vs-panel-8bpc@hdmi-a-1-pipe-a.html
* igt@kms_draw_crc@draw-method-rgb565-render-4tiled:
- shard-tglb: NOTRUN -> [SKIP][96] ([i915#5287])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@kms_draw_crc@draw-method-rgb565-render-4tiled.html
- shard-iclb: NOTRUN -> [SKIP][97] ([i915#5287])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb3/igt@kms_draw_crc@draw-method-rgb565-render-4tiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271]) +202 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-plain-flip:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109274])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb5/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling:
- shard-iclb: NOTRUN -> [SKIP][100] ([i915#2587])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [PASS][101] -> [SKIP][102] ([i915#3701])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-snb: NOTRUN -> [SKIP][103] ([fdo#109271]) +89 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
- shard-iclb: NOTRUN -> [SKIP][104] ([fdo#109280]) +7 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt:
- shard-tglb: NOTRUN -> [SKIP][105] ([fdo#109280] / [fdo#111825]) +7 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
- shard-tglb: [PASS][106] -> [DMESG-WARN][107] ([i915#1982])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-tglb3/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: [PASS][108] -> [DMESG-FAIL][109] ([i915#180])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl4/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#533])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl1/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][111] ([fdo#108145] / [i915#265])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][112] ([fdo#108145] / [i915#265]) +1 similar issue
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][113] ([i915#265])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
- shard-glk: NOTRUN -> [FAIL][114] ([i915#265])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk3/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
- shard-kbl: NOTRUN -> [FAIL][115] ([i915#265])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-c-tiling-yf:
- shard-glk: [PASS][116] -> [FAIL][117] ([i915#1888])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-glk7/igt@kms_plane_lowres@pipe-c-tiling-yf.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk5/igt@kms_plane_lowres@pipe-c-tiling-yf.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][118] ([fdo#111615]) +2 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb5/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1:
- shard-tglb: NOTRUN -> [SKIP][119] ([i915#5176]) +3 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb6/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1.html
- shard-iclb: NOTRUN -> [SKIP][120] ([i915#5176]) +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][121] ([fdo#109271]) +106 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-c-hdmi-a-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#658]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
- shard-tglb: NOTRUN -> [SKIP][123] ([i915#2920])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
- shard-glk: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#658])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
- shard-iclb: NOTRUN -> [SKIP][125] ([fdo#111068] / [i915#658])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-kbl: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#658]) +2 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl4/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: [PASS][127] -> [SKIP][128] ([fdo#109441]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb2/igt@kms_psr@psr2_primary_render.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb8/igt@kms_psr@psr2_primary_render.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
- shard-iclb: NOTRUN -> [SKIP][129] ([i915#5289])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
- shard-tglb: NOTRUN -> [SKIP][130] ([i915#5289])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb3/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-tglb: NOTRUN -> [SKIP][131] ([fdo#111615] / [i915#5289])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-iclb: NOTRUN -> [SKIP][132] ([i915#3555])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb7/igt@kms_setmode@basic-clone-single-crtc.html
- shard-tglb: NOTRUN -> [SKIP][133] ([i915#3555])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb3/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_writeback@writeback-fb-id:
- shard-tglb: NOTRUN -> [SKIP][134] ([i915#2437])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@kms_writeback@writeback-fb-id.html
- shard-glk: NOTRUN -> [SKIP][135] ([fdo#109271] / [i915#2437])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk5/igt@kms_writeback@writeback-fb-id.html
- shard-iclb: NOTRUN -> [SKIP][136] ([i915#2437])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb3/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-a-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][137] ([i915#2530]) +1 similar issue
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb7/igt@nouveau_crc@pipe-a-source-outp-complete.html
- shard-iclb: NOTRUN -> [SKIP][138] ([i915#2530])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@nouveau_crc@pipe-a-source-outp-complete.html
* igt@nouveau_crc@pipe-d-source-rg:
- shard-iclb: NOTRUN -> [SKIP][139] ([fdo#109278] / [i915#2530])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb1/igt@nouveau_crc@pipe-d-source-rg.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-tglb: NOTRUN -> [SKIP][140] ([fdo#109291]) +2 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb2/igt@prime_nv_api@i915_nv_import_twice.html
- shard-iclb: NOTRUN -> [SKIP][141] ([fdo#109291]) +2 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb4/igt@prime_nv_api@i915_nv_import_twice.html
* igt@sw_sync@sync_multi_timeline_wait:
- shard-apl: NOTRUN -> [FAIL][142] ([i915#6140])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl3/igt@sw_sync@sync_multi_timeline_wait.html
* igt@sysfs_clients@sema-25:
- shard-apl: NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#2994])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl1/igt@sysfs_clients@sema-25.html
- shard-kbl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#2994]) +3 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@sysfs_clients@sema-25.html
* igt@sysfs_clients@split-50:
- shard-tglb: NOTRUN -> [SKIP][145] ([i915#2994])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb1/igt@sysfs_clients@split-50.html
- shard-glk: NOTRUN -> [SKIP][146] ([fdo#109271] / [i915#2994])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk4/igt@sysfs_clients@split-50.html
- shard-iclb: NOTRUN -> [SKIP][147] ([i915#2994])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb2/igt@sysfs_clients@split-50.html
#### Possible fixes ####
* igt@fbdev@write:
- {shard-rkl}: [SKIP][148] ([i915#2582]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-rkl-2/igt@fbdev@write.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-rkl-5/igt@fbdev@write.html
* igt@gem_ctx_persistence@smoketest:
- shard-tglb: [FAIL][150] ([i915#5099]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-tglb5/igt@gem_ctx_persistence@smoketest.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb1/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [TIMEOUT][152] ([i915#3070]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb4/igt@gem_eio@unwedge-stress.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][154] ([i915#2842]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-glk8/igt@gem_exec_fair@basic-pace-share@rcs0.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][156] ([i915#2842]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-snb: [SKIP][158] ([fdo#109271]) -> [PASS][159] +3 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-snb6/igt@gem_exec_flush@basic-uc-pro-default.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-snb4/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][160] ([i915#5566] / [i915#716]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-glk7/igt@gen9_exec_parse@allowed-all.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk9/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_rps@min-max-config-idle:
- {shard-rkl}: [FAIL][162] ([i915#4016]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-rkl-2/igt@i915_pm_rps@min-max-config-idle.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-rkl-1/igt@i915_pm_rps@min-max-config-idle.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [FAIL][164] ([i915#2346]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_cursor_legacy@pipe-c-single-bo:
- {shard-rkl}: [SKIP][166] ([i915#4070]) -> [PASS][167] +1 similar issue
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-rkl-1/igt@kms_cursor_legacy@pipe-c-single-bo.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-rkl-5/igt@kms_cursor_legacy@pipe-c-single-bo.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [DMESG-WARN][168] ([i915#180]) -> [PASS][169] +3 similar issues
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-glk: [FAIL][170] ([i915#1888] / [i915#2546]) -> [PASS][171]
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-glk5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-glk9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_hdmi_inject@inject-audio:
- {shard-rkl}: [SKIP][172] ([i915#433]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-rkl-5/igt@kms_hdmi_inject@inject-audio.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-rkl-2/igt@kms_hdmi_inject@inject-audio.html
- shard-tglb: [SKIP][174] ([i915#433]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-tglb6/igt@kms_hdmi_inject@inject-audio.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb6/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][176] ([fdo#109441]) -> [PASS][177] +2 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][178] ([i915#180]) -> [PASS][179] +5 similar issues
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][180] ([i915#4525]) -> [FAIL][181] ([i915#6117])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][182] ([i915#2842]) -> [FAIL][183] ([i915#2852])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb8/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@kms_content_protection@mei_interface:
- shard-tglb: [SKIP][184] ([i915#1063]) -> [SKIP][185] ([fdo#109300])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-tglb5/igt@kms_content_protection@mei_interface.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-tglb2/igt@kms_content_protection@mei_interface.html
- shard-iclb: [SKIP][186] ([fdo#109300] / [fdo#111066]) -> [SKIP][187] ([fdo#109300])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb8/igt@kms_content_protection@mei_interface.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb1/igt@kms_content_protection@mei_interface.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][188] ([i915#658]) -> [SKIP][189] ([i915#2920]) +1 similar issue
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-iclb6/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@runner@aborted:
- shard-apl: ([FAIL][190], [FAIL][191], [FAIL][192], [FAIL][193], [FAIL][194], [FAIL][195], [FAIL][196]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][197], [FAIL][198], [FAIL][199], [FAIL][200], [FAIL][201], [FAIL][202], [FAIL][203], [FAIL][204]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl6/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl8/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl6/igt@runner@aborted.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl2/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl1/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl3/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-apl1/igt@runner@aborted.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl6/igt@runner@aborted.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl8/igt@runner@aborted.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl6/igt@runner@aborted.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl3/igt@runner@aborted.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl6/igt@runner@aborted.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl1/igt@runner@aborted.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl1/igt@runner@aborted.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-apl1/igt@runner@aborted.html
- shard-kbl: ([FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl4/igt@runner@aborted.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl4/igt@runner@aborted.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl1/igt@runner@aborted.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl3/igt@runner@aborted.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl1/igt@runner@aborted.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl1/igt@runner@aborted.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl6/igt@runner@aborted.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl6/igt@runner@aborted.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl4/igt@runner@aborted.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl7/igt@runner@aborted.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl7/igt@runner@aborted.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11724/shard-kbl4/igt@runner@aborted.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl1/igt@runner@aborted.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl1/igt@runner@aborted.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl4/igt@runner@aborted.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl1/igt@runner@aborted.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl6/igt@runner@aborted.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl6/igt@runner@aborted.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@runner@aborted.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl6/igt@runner@aborted.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl6/igt@runner@aborted.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl4/igt@runner@aborted.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl4/igt@runner@aborted.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@runner@aborted.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/shard-kbl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3736]: https://gitlab.freedesktop.org/drm/intel/issues/3736
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4241]: https://gitlab.freedesktop.org/drm/intel/issues/4241
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4929]: https://gitlab.freedesktop.org/drm/intel/issues/4929
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
[i915#5115]: https://gitlab.freedesktop.org/drm/intel/issues/5115
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5357]: https://gitlab.freedesktop.org/drm/intel/issues/5357
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_6505 -> IGTPW_7219
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_11724: d85a4921e88b2c0c5c61ab452aa302a969e108e3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7219: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/index.html
IGT_6505: edb1a467fb622b23b927e28ff603fa43851fea97 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7219/index.html
[-- Attachment #2: Type: text/html, Size: 63778 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [igt-dev] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table
2022-06-03 0:54 ` [Intel-gfx] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
@ 2022-06-03 15:50 ` Kamil Konieczny
0 siblings, 0 replies; 10+ messages in thread
From: Kamil Konieczny @ 2022-06-03 15:50 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
Hi John,
On 2022-06-02 at 17:54:04 -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the existing query API. So add a test for it as both an
> example of how to fetch the table and to validate the contents as much
> as is possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> lib/intel_hwconfig_types.h | 118 ++++++++++++++++++++++++
> tests/i915/i915_query.c | 179 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 297 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000000..d5db217afba2
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE, /* 74 */
> + INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK, /* 75 */
> + INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES, /* 76 */
> + INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES, /* 77 */
> + INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES, /* 78 */
> + INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES, /* 79 */
> + INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES, /* 80 */
> + __INTEL_HWCONFIG_KEY_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> + INTEL_HWCONFIG_MEMORY_TYPE_HBM2,
> + INTEL_HWCONFIG_MEMORY_TYPE_HBM2e,
> + INTEL_HWCONFIG_MEMORY_TYPE_GDDR6,
> + __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_CACHE_TYPE_L3 = 0,
> + INTEL_HWCONFIG_CACHE_TYPE_LLC,
> + INTEL_HWCONFIG_CACHE_TYPE_EDRAM,
> + __INTEL_HWCONFIG_CACHE_TYPE_LIMIT
> +};
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 246a979af72a..c47a74117d8d 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -912,6 +913,181 @@ static void test_query_geometry_subslices(int fd)
> }
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> + [INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE] = "Num HBM Stacks Per Tile",
> + [INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK] = "Num Channels Per HBM Stack",
> + [INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES] = "HBM Channel Width (in bytes)",
> + [INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES] = "Min Task URB Entries",
> + [INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES] = "Max Task URB Entries",
> + [INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES] = "Min Mesh URB Entries",
> + [INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES] = "Max Mesh URB Entries",
> +};
> +
> +static const char * const hwconfig_memtypes[] = {
> + [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4] = "LPDDR4",
> + [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5] = "LPDDR5",
> + [INTEL_HWCONFIG_MEMORY_TYPE_HBM2] = "HBM2",
> + [INTEL_HWCONFIG_MEMORY_TYPE_HBM2e] = "HBM2e",
> + [INTEL_HWCONFIG_MEMORY_TYPE_GDDR6] = "GDDR6",
> +};
> +
> +static const char * const hwconfig_cachetypes[] = {
> + [INTEL_HWCONFIG_CACHE_TYPE_L3] = "L3",
> + [INTEL_HWCONFIG_CACHE_TYPE_LLC] = "LLC",
> + [INTEL_HWCONFIG_CACHE_TYPE_EDRAM] = "EDRAM",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_BLOB,
> + };
> + uint32_t *data, value;
> + int i = 0;
> + int len, j, max_words, table_size;
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_KEY_LIMIT);
> + igt_assert(ARRAY_SIZE(hwconfig_memtypes) == __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
> + igt_assert(ARRAY_SIZE(hwconfig_cachetypes) == __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + table_size = item.length;
> + igt_require(table_size > 0);
> +
> + data = malloc(table_size);
> + igt_assert(data);
> + memset(data, 0, table_size);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_assert(item.length == table_size);
> + igt_info("Table size = %d bytes\n", table_size);
> + igt_assert(table_size > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = table_size / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == table_size);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT);
> +
> + len = data[i + 1];
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
> +
> + value = data[i + 2];
> + switch (data[i]) {
> + case INTEL_HWCONFIG_MEMORY_TYPE:
> + igt_assert(len == 1);
> + igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
> + igt_info("%s\n", hwconfig_memtypes[value]);
> + break;
> +
> + case INTEL_HWCONFIG_CACHE_TYPES:
> + igt_assert(len == 1);
> +
> + if (!value)
> + igt_info("-\n");
> +
> + j = 0;
> + while (value) {
> + if (value & BIT(j)) {
> + value &= ~BIT(j);
> + igt_assert(j < __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
> + igt_info("%s%s", hwconfig_cachetypes[j], value ? ", " : "\n");
> + }
> + }
> + break;
> +
> + default:
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info("%d, ", data[j]);
> + igt_info("%d\n", data[j]);
> + }
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -986,6 +1162,9 @@ igt_main
> engines(fd);
> }
>
Please add description before every new test you are adding
with igt_describe().
BR,
Kamil
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.36.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [igt-dev] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table
@ 2022-06-03 15:50 ` Kamil Konieczny
0 siblings, 0 replies; 10+ messages in thread
From: Kamil Konieczny @ 2022-06-03 15:50 UTC (permalink / raw)
To: igt-dev; +Cc: Intel-GFX, Slawomir Milczarek, Rodrigo Vivi
Hi John,
On 2022-06-02 at 17:54:04 -0700, John.C.Harrison@Intel.com wrote:
> From: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Newer platforms have an embedded table giving details about that
> platform's hardware configuration. This table can be retrieved from
> the KMD via the existing query API. So add a test for it as both an
> example of how to fetch the table and to validate the contents as much
> as is possible.
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
> Cc: Slawomir Milczarek <slawomir.milczarek@intel.com>
> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
> lib/intel_hwconfig_types.h | 118 ++++++++++++++++++++++++
> tests/i915/i915_query.c | 179 +++++++++++++++++++++++++++++++++++++
> 2 files changed, 297 insertions(+)
> create mode 100644 lib/intel_hwconfig_types.h
>
> diff --git a/lib/intel_hwconfig_types.h b/lib/intel_hwconfig_types.h
> new file mode 100644
> index 000000000000..d5db217afba2
> --- /dev/null
> +++ b/lib/intel_hwconfig_types.h
> @@ -0,0 +1,118 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _INTEL_HWCONFIG_TYPES_H_
> +#define _INTEL_HWCONFIG_TYPES_H_
> +
> +#include "intel_chipset.h"
> +
> +/**
> + * enum intel_hwconfig - Global definition of hwconfig table attributes
> + *
> + * Intel devices provide a KLV (Key/Length/Value) table containing
> + * the static hardware configuration for that platform.
> + * This enum defines the current attribute keys for this KLV.
> + */
> +enum intel_hwconfig {
> + INTEL_HWCONFIG_MAX_SLICES_SUPPORTED = 1,
> + INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED, /* 2 */
> + INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS, /* 3 */
> + INTEL_HWCONFIG_NUM_PIXEL_PIPES, /* 4 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES, /* 5 */
> + INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB, /* 6 */
> + INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT, /* 7 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES, /* 8 */
> + INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR, /* 9 */
> + INTEL_HWCONFIG_MAX_MEMORY_CHANNELS, /* 10 */
> + INTEL_HWCONFIG_MEMORY_TYPE, /* 11 */
> + INTEL_HWCONFIG_CACHE_TYPES, /* 12 */
> + INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED, /* 13 */
> + INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB, /* 14 */
> + INTEL_HWCONFIG_NUM_THREADS_PER_EU, /* 15 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS, /* 16 */
> + INTEL_HWCONFIG_TOTAL_GS_THREADS, /* 17 */
> + INTEL_HWCONFIG_TOTAL_HS_THREADS, /* 18 */
> + INTEL_HWCONFIG_TOTAL_DS_THREADS, /* 19 */
> + INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS, /* 20 */
> + INTEL_HWCONFIG_TOTAL_PS_THREADS, /* 21 */
> + INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE, /* 22 */
> + INTEL_HWCONFIG_MAX_RCS, /* 23 */
> + INTEL_HWCONFIG_MAX_CCS, /* 24 */
> + INTEL_HWCONFIG_MAX_VCS, /* 25 */
> + INTEL_HWCONFIG_MAX_VECS, /* 26 */
> + INTEL_HWCONFIG_MAX_COPY_CS, /* 27 */
> + INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB, /* 28 */
> + INTEL_HWCONFIG_MIN_VS_URB_ENTRIES, /* 29 */
> + INTEL_HWCONFIG_MAX_VS_URB_ENTRIES, /* 30 */
> + INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES, /* 31 */
> + INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES, /* 32 */
> + INTEL_HWCONFIG_MIN_HS_URB_ENTRIES, /* 33 */
> + INTEL_HWCONFIG_MAX_HS_URB_ENTRIES, /* 34 */
> + INTEL_HWCONFIG_MIN_GS_URB_ENTRIES, /* 35 */
> + INTEL_HWCONFIG_MAX_GS_URB_ENTRIES, /* 36 */
> + INTEL_HWCONFIG_MIN_DS_URB_ENTRIES, /* 37 */
> + INTEL_HWCONFIG_MAX_DS_URB_ENTRIES, /* 38 */
> + INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 39 */
> + INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE, /* 40 */
> + INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES, /* 41 */
> + INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES, /* 42 */
> + INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES, /* 43 */
> + INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 44 */
> + INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT, /* 45 */
> + INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS, /* 46 */
> + INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS, /* 47 */
> + INTEL_HWCONFIG_MIN_CS_URB_ENTRIES, /* 48 */
> + INTEL_HWCONFIG_MAX_CS_URB_ENTRIES, /* 49 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB, /* 50 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST, /* 51 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC, /* 52 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO, /* 53 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z, /* 54 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR, /* 55 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE, /* 56 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER, /* 57 */
> + INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW, /* 58 */
> + INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS, /* 59 */
> + INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT, /* 60 */
> + INTEL_HWCONFIG_RESERVED_CCS_WAYS, /* 61 */
> + INTEL_HWCONFIG_CSR_SIZE_IN_MB, /* 62 */
> + INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE, /* 63 */
> + INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB, /* 64 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_DSS, /* 65 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE, /* 66 */
> + INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS, /* 67 */
> + INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB, /* 68 */
> + INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB, /* 69 */
> + INTEL_HWCONFIG_MAX_SUBSLICE, /* 70 */
> + INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE, /* 71 */
> + INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB, /* 72 */
> + INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB, /* 73 */
> + INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE, /* 74 */
> + INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK, /* 75 */
> + INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES, /* 76 */
> + INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES, /* 77 */
> + INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES, /* 78 */
> + INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES, /* 79 */
> + INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES, /* 80 */
> + __INTEL_HWCONFIG_KEY_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4 = 0,
> + INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5,
> + INTEL_HWCONFIG_MEMORY_TYPE_HBM2,
> + INTEL_HWCONFIG_MEMORY_TYPE_HBM2e,
> + INTEL_HWCONFIG_MEMORY_TYPE_GDDR6,
> + __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT
> +};
> +
> +enum {
> + INTEL_HWCONFIG_CACHE_TYPE_L3 = 0,
> + INTEL_HWCONFIG_CACHE_TYPE_LLC,
> + INTEL_HWCONFIG_CACHE_TYPE_EDRAM,
> + __INTEL_HWCONFIG_CACHE_TYPE_LIMIT
> +};
> +
> +#endif /* _INTEL_HWCONFIG_TYPES_H_ */
> diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c
> index 246a979af72a..c47a74117d8d 100644
> --- a/tests/i915/i915_query.c
> +++ b/tests/i915/i915_query.c
> @@ -22,6 +22,7 @@
> */
>
> #include "igt.h"
> +#include "intel_hwconfig_types.h"
>
> #include <limits.h>
>
> @@ -912,6 +913,181 @@ static void test_query_geometry_subslices(int fd)
> }
> }
>
> +static const char * const hwconfig_keys[] = {
> + [INTEL_HWCONFIG_MAX_SLICES_SUPPORTED] = "Maximum number of Slices",
> + [INTEL_HWCONFIG_MAX_DUAL_SUBSLICES_SUPPORTED] = "Maximum number of DSS",
> + [INTEL_HWCONFIG_MAX_NUM_EU_PER_DSS] = "Maximum number of EUs per DSS",
> + [INTEL_HWCONFIG_NUM_PIXEL_PIPES] = "Pixel Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_NUM_GEOMETRY_PIPES] = "[DEPRECATED] Geometry Pipes",
> + [INTEL_HWCONFIG_DEPRECATED_L3_CACHE_SIZE_IN_KB] = "[DEPRECATED] L3 Size (in KB)",
> + [INTEL_HWCONFIG_DEPRECATED_L3_BANK_COUNT] = "[DEPRECATED] L3 Bank Count",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_SIZE_IN_BYTES] = "L3 Cache Ways Size (in bytes)",
> + [INTEL_HWCONFIG_L3_CACHE_WAYS_PER_SECTOR] = "L3 Cache Ways Per Sector",
> + [INTEL_HWCONFIG_MAX_MEMORY_CHANNELS] = "Memory Channels",
> + [INTEL_HWCONFIG_MEMORY_TYPE] = "Memory type",
> + [INTEL_HWCONFIG_CACHE_TYPES] = "Cache types",
> + [INTEL_HWCONFIG_LOCAL_MEMORY_PAGE_SIZES_SUPPORTED] = "Local memory page size",
> + [INTEL_HWCONFIG_DEPRECATED_SLM_SIZE_IN_KB] = "[DEPRECATED] SLM Size (in KB)",
> + [INTEL_HWCONFIG_NUM_THREADS_PER_EU] = "Num thread per EU",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS] = "Maximum Vertex Shader threads",
> + [INTEL_HWCONFIG_TOTAL_GS_THREADS] = "Maximum Geometry Shader threads",
> + [INTEL_HWCONFIG_TOTAL_HS_THREADS] = "Maximum Hull Shader threads",
> + [INTEL_HWCONFIG_TOTAL_DS_THREADS] = "Maximum Domain Shader threads",
> + [INTEL_HWCONFIG_TOTAL_VS_THREADS_POCS] = "Maximum Vertex Shader Threads for POCS",
> + [INTEL_HWCONFIG_TOTAL_PS_THREADS] = "Maximum Pixel Shader Threads",
> + [INTEL_HWCONFIG_DEPRECATED_MAX_FILL_RATE] = "[DEPRECATED] Maximum pixel rate for Fill",
> + [INTEL_HWCONFIG_MAX_RCS] = "MaxRCS",
> + [INTEL_HWCONFIG_MAX_CCS] = "MaxCCS",
> + [INTEL_HWCONFIG_MAX_VCS] = "MaxVCS",
> + [INTEL_HWCONFIG_MAX_VECS] = "MaxVECS",
> + [INTEL_HWCONFIG_MAX_COPY_CS] = "MaxCopyCS",
> + [INTEL_HWCONFIG_DEPRECATED_URB_SIZE_IN_KB] = "[DEPRECATED] URB Size (in KB)",
> + [INTEL_HWCONFIG_MIN_VS_URB_ENTRIES] = "The minimum number of VS URB entries.",
> + [INTEL_HWCONFIG_MAX_VS_URB_ENTRIES] = "The maximum number of VS URB entries.",
> + [INTEL_HWCONFIG_MIN_PCS_URB_ENTRIES] = "The minimum number of PCS URB entries",
> + [INTEL_HWCONFIG_MAX_PCS_URB_ENTRIES] = "The maximum number of PCS URB entries",
> + [INTEL_HWCONFIG_MIN_HS_URB_ENTRIES] = "The minimum number of HS URB entries",
> + [INTEL_HWCONFIG_MAX_HS_URB_ENTRIES] = "The maximum number of HS URB entries",
> + [INTEL_HWCONFIG_MIN_GS_URB_ENTRIES] = "The minimum number of GS URB entries",
> + [INTEL_HWCONFIG_MAX_GS_URB_ENTRIES] = "The maximum number of GS URB entries",
> + [INTEL_HWCONFIG_MIN_DS_URB_ENTRIES] = "The minimum number of DS URB Entries",
> + [INTEL_HWCONFIG_MAX_DS_URB_ENTRIES] = "The maximum number of DS URB Entries",
> + [INTEL_HWCONFIG_PUSH_CONSTANT_URB_RESERVED_SIZE] = "Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_POCS_PUSH_CONSTANT_URB_RESERVED_SIZE] = "POCS Push Constant URB Reserved Size (in bytes)",
> + [INTEL_HWCONFIG_URB_REGION_ALIGNMENT_SIZE_IN_BYTES] = "URB Region Alignment Size (in bytes)",
> + [INTEL_HWCONFIG_URB_ALLOCATION_SIZE_UNITS_IN_BYTES] = "URB Allocation Size Units (in bytes)",
> + [INTEL_HWCONFIG_MAX_URB_SIZE_CCS_IN_BYTES] = "Max URB Size CCS (in bytes)",
> + [INTEL_HWCONFIG_VS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "VS Min Deref BlockSize Handle Count",
> + [INTEL_HWCONFIG_DS_MIN_DEREF_BLOCK_SIZE_HANDLE_COUNT] = "DS Min Deref Block Size Handle Count",
> + [INTEL_HWCONFIG_NUM_RT_STACKS_PER_DSS] = "Num RT Stacks Per DSS",
> + [INTEL_HWCONFIG_MAX_URB_STARTING_ADDRESS] = "Max URB Starting Address",
> + [INTEL_HWCONFIG_MIN_CS_URB_ENTRIES] = "Min CS URB Entries",
> + [INTEL_HWCONFIG_MAX_CS_URB_ENTRIES] = "Max CS URB Entries",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_URB] = "L3 Alloc Per Bank - URB",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_REST] = "L3 Alloc Per Bank - Rest",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_DC] = "L3 Alloc Per Bank - DC",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RO] = "L3 Alloc Per Bank - RO",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_Z] = "L3 Alloc Per Bank - Z",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COLOR] = "L3 Alloc Per Bank - Color",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_UNIFIED_TILE_CACHE] = "L3 Alloc Per Bank - Unified Tile Cache",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_COMMAND_BUFFER] = "L3 Alloc Per Bank - Command Buffer",
> + [INTEL_HWCONFIG_L3_ALLOC_PER_BANK_RW] = "L3 Alloc Per Bank - RW",
> + [INTEL_HWCONFIG_MAX_NUM_L3_CONFIGS] = "Num L3 Configs",
> + [INTEL_HWCONFIG_BINDLESS_SURFACE_OFFSET_BIT_COUNT] = "Bindless Surface Offset Bit Count",
> + [INTEL_HWCONFIG_RESERVED_CCS_WAYS] = "Reserved CCS ways",
> + [INTEL_HWCONFIG_CSR_SIZE_IN_MB] = "CSR Size (in MB)",
> + [INTEL_HWCONFIG_GEOMETRY_PIPES_PER_SLICE] = "Geometry pipes per slice",
> + [INTEL_HWCONFIG_L3_BANK_SIZE_IN_KB] = "L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_DSS] = "SLM size per DSS",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_SLICE] = "Max pixel fill rate per slice",
> + [INTEL_HWCONFIG_MAX_PIXEL_FILL_RATE_PER_DSS] = "Max pixel fill rate per DSS",
> + [INTEL_HWCONFIG_URB_SIZE_PER_SLICE_IN_KB] = "URB size per slice (in KB)",
> + [INTEL_HWCONFIG_URB_SIZE_PER_L3_BANK_COUNT_IN_KB] = "URB size per L3 bank count (in KB)",
> + [INTEL_HWCONFIG_MAX_SUBSLICE] = "Max subslices",
> + [INTEL_HWCONFIG_MAX_EU_PER_SUBSLICE] = "Max EUs per subslice",
> + [INTEL_HWCONFIG_RAMBO_L3_BANK_SIZE_IN_KB] = "RAMBO L3 bank size (in KB)",
> + [INTEL_HWCONFIG_SLM_SIZE_PER_SS_IN_KB] = "SLM size per SS (in KB)",
> + [INTEL_HWCONFIG_NUM_HBM_STACKS_PER_TILE] = "Num HBM Stacks Per Tile",
> + [INTEL_HWCONFIG_NUM_CHANNELS_PER_HBM_STACK] = "Num Channels Per HBM Stack",
> + [INTEL_HWCONFIG_HBM_CHANNEL_WIDTH_IN_BYTES] = "HBM Channel Width (in bytes)",
> + [INTEL_HWCONFIG_MIN_TASK_URB_ENTRIES] = "Min Task URB Entries",
> + [INTEL_HWCONFIG_MAX_TASK_URB_ENTRIES] = "Max Task URB Entries",
> + [INTEL_HWCONFIG_MIN_MESH_URB_ENTRIES] = "Min Mesh URB Entries",
> + [INTEL_HWCONFIG_MAX_MESH_URB_ENTRIES] = "Max Mesh URB Entries",
> +};
> +
> +static const char * const hwconfig_memtypes[] = {
> + [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR4] = "LPDDR4",
> + [INTEL_HWCONFIG_MEMORY_TYPE_LPDDR5] = "LPDDR5",
> + [INTEL_HWCONFIG_MEMORY_TYPE_HBM2] = "HBM2",
> + [INTEL_HWCONFIG_MEMORY_TYPE_HBM2e] = "HBM2e",
> + [INTEL_HWCONFIG_MEMORY_TYPE_GDDR6] = "GDDR6",
> +};
> +
> +static const char * const hwconfig_cachetypes[] = {
> + [INTEL_HWCONFIG_CACHE_TYPE_L3] = "L3",
> + [INTEL_HWCONFIG_CACHE_TYPE_LLC] = "LLC",
> + [INTEL_HWCONFIG_CACHE_TYPE_EDRAM] = "EDRAM",
> +};
> +
> +static void query_parse_and_validate_hwconfig_table(int i915)
> +{
> + struct drm_i915_query_item item = {
> + .query_id = DRM_I915_QUERY_HWCONFIG_BLOB,
> + };
> + uint32_t *data, value;
> + int i = 0;
> + int len, j, max_words, table_size;
> +
> + igt_assert(ARRAY_SIZE(hwconfig_keys) == __INTEL_HWCONFIG_KEY_LIMIT);
> + igt_assert(ARRAY_SIZE(hwconfig_memtypes) == __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
> + igt_assert(ARRAY_SIZE(hwconfig_cachetypes) == __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
> +
> + i915_query_items(i915, &item, 1);
> + table_size = item.length;
> + igt_require(table_size > 0);
> +
> + data = malloc(table_size);
> + igt_assert(data);
> + memset(data, 0, table_size);
> + item.data_ptr = to_user_pointer(data);
> +
> + i915_query_items(i915, &item, 1);
> + igt_assert(item.length == table_size);
> + igt_info("Table size = %d bytes\n", table_size);
> + igt_assert(table_size > 0);
> +
> + /* HWConfig table is a list of KLV sets */
> + max_words = table_size / sizeof(uint32_t);
> + igt_assert(max_words * sizeof(uint32_t) == table_size);
> + while (i < max_words) {
> + /* Attribute ID zero is invalid */
> + igt_assert(data[i] > 0);
> + igt_assert(data[i] < __INTEL_HWCONFIG_KEY_LIMIT);
> +
> + len = data[i + 1];
> + igt_assert(len > 0);
> + igt_assert((i + 2 + len) <= max_words);
> +
> + igt_info("[%2d] %s: ", data[i], hwconfig_keys[data[i]]);
> +
> + value = data[i + 2];
> + switch (data[i]) {
> + case INTEL_HWCONFIG_MEMORY_TYPE:
> + igt_assert(len == 1);
> + igt_assert(value < __INTEL_HWCONFIG_MEMORY_TYPE_LIMIT);
> + igt_info("%s\n", hwconfig_memtypes[value]);
> + break;
> +
> + case INTEL_HWCONFIG_CACHE_TYPES:
> + igt_assert(len == 1);
> +
> + if (!value)
> + igt_info("-\n");
> +
> + j = 0;
> + while (value) {
> + if (value & BIT(j)) {
> + value &= ~BIT(j);
> + igt_assert(j < __INTEL_HWCONFIG_CACHE_TYPE_LIMIT);
> + igt_info("%s%s", hwconfig_cachetypes[j], value ? ", " : "\n");
> + }
> + }
> + break;
> +
> + default:
> + for (j = i + 2; j < i + 1 + len; j++)
> + igt_info("%d, ", data[j]);
> + igt_info("%d\n", data[j]);
> + }
> +
> + /* Advance to next key */
> + i += 2 + len;
> + }
> +
> + free(data);
> +}
> +
> igt_main
> {
> int fd = -1;
> @@ -986,6 +1162,9 @@ igt_main
> engines(fd);
> }
>
Please add description before every new test you are adding
with igt_describe().
BR,
Kamil
> + igt_subtest("hwconfig_table")
> + query_parse_and_validate_hwconfig_table(fd);
> +
> igt_fixture {
> close(fd);
> }
> --
> 2.36.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-06-03 15:50 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2022-06-03 0:54 [Intel-gfx] [PATCH v3 i-g-t 0/2] Update DRM UAPI and add test for new hw info query John.C.Harrison
2022-06-03 0:54 ` [Intel-gfx] [PATCH v3 i-g-t 1/2] include/drm-uapi: Update to latest i915_drm.h John.C.Harrison
2022-06-03 0:54 ` [igt-dev] " John.C.Harrison
2022-06-03 7:25 ` [Intel-gfx] " Petri Latvala
2022-06-03 7:25 ` Petri Latvala
2022-06-03 0:54 ` [Intel-gfx] [PATCH v3 i-g-t 2/2] tests/i915/query: Query, parse and validate the hwconfig table John.C.Harrison
2022-06-03 15:50 ` [Intel-gfx] [igt-dev] " Kamil Konieczny
2022-06-03 15:50 ` Kamil Konieczny
2022-06-03 3:46 ` [igt-dev] ✓ Fi.CI.BAT: success for Update DRM UAPI and add test for new hw info query Patchwork
2022-06-03 7:44 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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