From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8160C43334 for ; Fri, 3 Jun 2022 12:48:54 +0000 (UTC) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E62B42B95; Fri, 3 Jun 2022 14:48:49 +0200 (CEST) Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2045.outbound.protection.outlook.com [40.107.102.45]) by mails.dpdk.org (Postfix) with ESMTP id E585F42B95 for ; Fri, 3 Jun 2022 14:48:47 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=a3iHp1czH7KqXBVK/9YGv8Juy23qEVs2JI4jx8hAc6paggMnh03Wl98HjY3nB+nhDhOFOCeD6huzmxobnwzDifakmPofp8Y73i+G8XUwGgmRgMvhIAxEBRwKN1Ln8MFpK6bpI1J/0mg3r50lGO+gghQGfhD1dIZrsHhaE5Z7I+Plp6emT3yRhLE7xVRH3+aN3VRI7u2UjDGs/RXAQUlmlQV21M+gfAOxNEcJ+vH883VbHExHBpRYws7RPA23Hju5Y4WKdRxWR1VPMNVGXYkisv7dGZpEn6iENiTXoBuhne1g5/j2kP9ml2HsfcBrhEcvCn6bKQIOnSduuhK+nH0ZKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pg+675AZbOTwl+uP1L76mj0+hcvbGz+qkG/pSn7NMe8=; b=OR0q8+u1t628PC3kS40lqidI/Qx/uThiZYPLFwFA4E1HypbDK0aLyEnUzmkYeGVzRs0biZMJcfL9mrWdC5/JCNHNFqnTj3ykI1+6uMCnxxBjawZmjbzH2LHMe0E7F2ce0DN8ZALxzc7zOZLP+SOS1uBF+G+8OWSXeSASpue/sVK3qXRCbXZauFZ1pUkkEhIQxzOQa94/fGfdX9S3MQdVKcBrCoa/u5JN/CG7/QZP5LS2schVs8HJxmtOAoZNgcNEDET/hJc6NtyHzL2ou7FZlDp2Yab1D8J2AyyVil7gY+9GKTRLTH6QKInNjT4nJEoLczJQG2cN43k1xSuh67qQEQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=smartsharesystems.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pg+675AZbOTwl+uP1L76mj0+hcvbGz+qkG/pSn7NMe8=; b=C5x2ANG7Srv+6yZL56L1dYtH+LuBsSRxH6MS5drl0seHDuTZJCDStRXQmz+/L3umNiAq0arXeFyywrUTW+uQ89q6/ymalWQ9MOvQ1U921Yb52uZi3BVnOZ9Z6FiE3mhBuvlCsQonq+QSTGU9IGD3mOgp7f2KjDdiKgwpWxZ4PLUNhDnWbhx/UoMFtcntiaOjzl1CWd/DrKRUKhrgSTCZVW9CFWEiZaISDZv7O1Cp9K7HFiKvDehBdPfz+gBHYlU1TbPI4exUTlcfm+ZlERLxNgAHBBcE+ATn9/dLcVPxjNkJM9Dx2WQRc9VaBQhR3sbpUwzqNxUS44MxM8uGozgfpQ== Received: from CO2PR07CA0084.namprd07.prod.outlook.com (2603:10b6:100::52) by BYAPR12MB3448.namprd12.prod.outlook.com (2603:10b6:a03:ad::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.12; Fri, 3 Jun 2022 12:48:45 +0000 Received: from CO1NAM11FT019.eop-nam11.prod.protection.outlook.com (2603:10b6:100:0:cafe::a8) by CO2PR07CA0084.outlook.office365.com (2603:10b6:100::52) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5314.15 via Frontend Transport; Fri, 3 Jun 2022 12:48:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.236) by CO1NAM11FT019.mail.protection.outlook.com (10.13.175.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5314.12 via Frontend Transport; Fri, 3 Jun 2022 12:48:44 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Fri, 3 Jun 2022 12:48:44 +0000 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 3 Jun 2022 05:48:41 -0700 From: Spike Du To: , , , , Shahaf Shuler CC: , , , , Subject: [PATCH v4 1/7] net/mlx5: add LWM support for Rxq Date: Fri, 3 Jun 2022 15:48:15 +0300 Message-ID: <20220603124821.1148119-2-spiked@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220603124821.1148119-1-spiked@nvidia.com> References: <20220524152041.737154-1-spiked@nvidia.com> <20220603124821.1148119-1-spiked@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5ebb2e75-05f6-4d09-24c4-08da455f6533 X-MS-TrafficTypeDiagnostic: BYAPR12MB3448:EE_ X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: BRHzMrKd30nMvQBktDg1RwQKIIz6ni/pJuo0XyuBt+HP8uTPjrxJR3pR2idrYIbGE/Ri6oGsRECfVkHYHqreni+DXR7NXw8NEkbK6c9jRXvKaxmekM8NyKavfjh6lKcAwTzGWeS9CmI6u+1EmJaPdt/vkO5SA5sSpafm/tdnENwITh64ln9OfCZI0JjhTS8BFaloVzVJ+XiCknObipC0lD/rISbc4SaHmMo+4qkeSNAIOQg5APifc6geXsh9HsGQQwk2WKwJY/1xeiISEzAJ6kDFX/GxBjCYlvUTR7a1PFfKczuig6TvIGtTCpPeJn4FRberd+UN0mTQQkWHikEAwdV1SeClYBuix8X7CxcOOv7yJ4b5n5CwG+gP1sfEGusRaH0EXSy3uj3Afn4YIVROxmvG2+8quKsCmQmsXhLMVDg8VVYbO9Lb31Rl+VPizsXOL2X+bpKM78Pi93iItcmSL20NGJPb1xYLJmBLjZvV/C8AZG7yzUREew6jsJrSEYC8yGUQY/DVYJWvhaJz+4NgtgShqAPjrZ1BCgJDt1a536JkCSXrub4Nzdg0ZA09APBt4jIzkKiJrrU8+xfrs69jNlsRUFpxjNaxhVvd8Jf5AHilinGVelYI+mTXQpW1qwxUglpj24DKWtt02MtvKjXzHJeyrxIh8hpsuKqeACujF/s72TuY+PXujAGq32LAnW0c01OuKC3GUMMJahlKOFdY9g== X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(8676002)(36860700001)(7696005)(40460700003)(2906002)(54906003)(6636002)(6286002)(55016003)(83380400001)(36756003)(336012)(426003)(47076005)(82310400005)(316002)(110136005)(16526019)(70586007)(107886003)(81166007)(86362001)(70206006)(8936002)(2616005)(186003)(4326008)(356005)(5660300002)(1076003)(26005)(6666004)(508600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2022 12:48:44.7313 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ebb2e75-05f6-4d09-24c4-08da455f6533 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3448 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add lwm(Limit WaterMark) field to Rxq object which indicates the percentage of RX queue size used by HW to raise LWM event to the user. Allow LWM setting in modify_rq command. Allow the LWM configuration dynamically by adding RDY2RDY state change. Signed-off-by: Spike Du --- drivers/net/mlx5/mlx5.h | 1 + drivers/net/mlx5/mlx5_devx.c | 13 ++++++++++++- drivers/net/mlx5/mlx5_devx.h | 1 + drivers/net/mlx5/mlx5_rx.h | 1 + 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index ef755ee..305edff 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1395,6 +1395,7 @@ enum mlx5_rxq_modify_type { MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ + MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ }; enum mlx5_txq_modify_type { diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 4b48f94..c918a50 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -62,7 +62,7 @@ * @return * 0 on success, a negative errno value otherwise and rte_errno is set. */ -static int +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type) { struct mlx5_devx_modify_rq_attr rq_attr; @@ -76,6 +76,11 @@ case MLX5_RXQ_MOD_RST2RDY: rq_attr.rq_state = MLX5_RQC_STATE_RST; rq_attr.state = MLX5_RQC_STATE_RDY; + if (rxq->lwm) { + rq_attr.modify_bitmask |= + MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + } break; case MLX5_RXQ_MOD_RDY2ERR: rq_attr.rq_state = MLX5_RQC_STATE_RDY; @@ -85,6 +90,12 @@ rq_attr.rq_state = MLX5_RQC_STATE_RDY; rq_attr.state = MLX5_RQC_STATE_RST; break; + case MLX5_RXQ_MOD_RDY2RDY: + rq_attr.rq_state = MLX5_RQC_STATE_RDY; + rq_attr.state = MLX5_RQC_STATE_RDY; + rq_attr.modify_bitmask |= MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM; + rq_attr.lwm = rxq->lwm; + break; default: break; } diff --git a/drivers/net/mlx5/mlx5_devx.h b/drivers/net/mlx5/mlx5_devx.h index a95207a..ebd1da4 100644 --- a/drivers/net/mlx5/mlx5_devx.h +++ b/drivers/net/mlx5/mlx5_devx.h @@ -11,6 +11,7 @@ int mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type, uint8_t dev_port); void mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj); +int mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type); extern struct mlx5_obj_ops devx_obj_ops; diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index e715ed6..25a5f2c 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -175,6 +175,7 @@ struct mlx5_rxq_priv { struct mlx5_devx_rq devx_rq; struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */ uint32_t hairpin_status; /* Hairpin binding status. */ + uint32_t lwm:16; }; /* External RX queue descriptor. */ -- 1.8.3.1