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From: "Christian König" <ckoenig.leichtzumerken@gmail.com>
To: Arunpravin.PaneerSelvam@amd.com, amd-gfx@lists.freedesktop.org
Subject: [PATCH] drm/amdgpu: always flush the TLB on gfx8
Date: Fri,  3 Jun 2022 15:05:04 +0200	[thread overview]
Message-ID: <20220603130504.81147-1-christian.koenig@amd.com> (raw)

The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
are set.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 9596c22fded6..b747488c28ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
 		     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
 
+	/*
+	 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
+	 */
+	flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
+
 	memset(&params, 0, sizeof(params));
 	params.adev = adev;
 	params.vm = vm;
-- 
2.25.1


             reply	other threads:[~2022-06-03 13:05 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-03 13:05 Christian König [this message]
2022-06-03 13:44 ` [PATCH] drm/amdgpu: always flush the TLB on gfx8 Pierre-Eric Pelloux-Prayer
2022-06-07 20:27 ` Alex Deucher
2022-06-08 13:58   ` Christian König
2022-06-08 14:03     ` Alex Deucher
2022-06-03 13:05 Christian König

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