From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A59BC433EF for ; Sat, 4 Jun 2022 16:48:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238892AbiFDQsF (ORCPT ); Sat, 4 Jun 2022 12:48:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238847AbiFDQsE (ORCPT ); Sat, 4 Jun 2022 12:48:04 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17B5FDEAB for ; Sat, 4 Jun 2022 09:48:03 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AF31760EED for ; Sat, 4 Jun 2022 16:48:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9D5DC385B8; Sat, 4 Jun 2022 16:47:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654361282; bh=3ivT9PXy6icmgU9Iu0djqXUoi+X3SKa6WsfkhLP+nuc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=eMks49+axnOzkrxKW+emSNSQ2Oq9HaOqwRnxXHyOK4fDbWCi5UdH4Sa5Qeqt+ok39 Mk6fNPPddgvnzM/No8Qzkyv1BS6wYa9yDzYojNYbsg/cfwPPgkPcJjfyK7QZl3HRUA EkardrfTNmbRwv6zVCYxNy0UPneJZsAP2p1W5DYdy/eMJdLBD45m228wKLGVDI3vxv YaEwbnl6Thqy0B0ATscUmmO+cfmpxwQM5msd+wy4C8AEvz3cy5ZURgMl5/ER5fISDJ aR/k9tp/u+Wt943VQABNqtV1mYb5+xManIwGOy3CPElr3DPgQnx0r9VTaUFKROMAxl /gz84+pTmoThg== Date: Sat, 4 Jun 2022 17:56:57 +0100 From: Jonathan Cameron To: linux-iio@vger.kernel.org Cc: Alexandru Lazar , Akinobu Mita , Alexandru Tachici , Antoniu Miclaus , Charles-Antoine Couret , Cosmin Tanislav , David Lechner , Ivan Mikhaylov , Jacopo Mondi , Jean-Baptiste Maneyrol , Lars-Peter Clausen , Marcelo Schmitt , =?UTF-8?B?TcOlcnRlbg==?= Lindahl , Matt Ranostay , Matt Ranostay , Michael Hennerich , Michael Welling , Mugilraj Dhavachelvan , Navin Sankar Velliangiri , Nuno =?UTF-8?B?U8Oh?= , Paul Cercueil , Phil Reid , Puranjay Mohan , Ricardo Ribalda , Robert Jones , Rui Miguel Silva , Sean Nyekjaer , Tomas Melin , Tomislav Denis , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= , Jonathan Cameron Subject: Re: [PATCH v2 01/92] iio: core: Fix IIO_ALIGN and rename as it was not sufficiently large Message-ID: <20220604175657.1f309718@jic23-huawei> In-Reply-To: <20220508175712.647246-2-jic23@kernel.org> References: <20220508175712.647246-1-jic23@kernel.org> <20220508175712.647246-2-jic23@kernel.org> X-Mailer: Claws Mail 4.1.0 (GTK 3.24.34; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-iio@vger.kernel.org On Sun, 8 May 2022 18:55:41 +0100 Jonathan Cameron wrote: > From: Jonathan Cameron >=20 > Discussion of the series: > https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.c= om/ > mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that > our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm > platforms out their with non coherent DMA and larger cache lines at > at higher levels of their cache hierarchy. >=20 > Rename the define to make it's purpose more explicit. It will be used > much more widely going forwards (to replace incorrect ____cacheline_align= ed > markings. >=20 > Note this patch will greatly reduce the padding on some architectures > that have smaller requirements for DMA safe buffers. >=20 > The history of changing values of ARCH_KMALLOC_MINALIGN via > ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this > as fixing a particular patch from that route as it's not clear what to ta= g. >=20 > Most recently a change to bring them back inline was reverted because > of some Qualcomm Kryo cores with an L2 cache with 128-byte lines > sitting above the point of coherency. >=20 > c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACH= E_BYTES)" > That reverts: > 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)= which > refers to the change originally being motivated by Thunder x1 performance > rather than correctness. >=20 > Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data = space to iio_allocate_device") > Signed-off-by: Jonathan Cameron > Acked-by: Nuno S=C3=A1 This crossed with a patch adding another use of IIO_ALIGN in bma400. I've f= ixed that rename up whilst applying. Thanks, Jonathan > --- > drivers/iio/adc/adi-axi-adc.c | 7 ++++--- > drivers/iio/industrialio-core.c | 4 ++-- > include/linux/iio/iio.h | 10 ++++++++-- > 3 files changed, 14 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/iio/adc/adi-axi-adc.c b/drivers/iio/adc/adi-axi-adc.c > index a73e3c2d212f..099be9d47223 100644 > --- a/drivers/iio/adc/adi-axi-adc.c > +++ b/drivers/iio/adc/adi-axi-adc.c > @@ -84,7 +84,8 @@ void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *co= nv) > { > struct adi_axi_adc_client *cl =3D conv_to_client(conv); > =20 > - return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); > + return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), > + IIO_DMA_MINALIGN); > } > EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv); > =20 > @@ -169,9 +170,9 @@ static struct adi_axi_adc_conv *adi_axi_adc_conv_regi= ster(struct device *dev, > struct adi_axi_adc_client *cl; > size_t alloc_size; > =20 > - alloc_size =3D ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); > + alloc_size =3D ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIG= N); > if (sizeof_priv) > - alloc_size +=3D ALIGN(sizeof_priv, IIO_ALIGN); > + alloc_size +=3D ALIGN(sizeof_priv, IIO_DMA_MINALIGN); > =20 > cl =3D kzalloc(alloc_size, GFP_KERNEL); > if (!cl) > diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-c= ore.c > index e1ed44dec2ab..b4218f3b1ac2 100644 > --- a/drivers/iio/industrialio-core.c > +++ b/drivers/iio/industrialio-core.c > @@ -1640,7 +1640,7 @@ struct iio_dev *iio_device_alloc(struct device *par= ent, int sizeof_priv) > =20 > alloc_size =3D sizeof(struct iio_dev_opaque); > if (sizeof_priv) { > - alloc_size =3D ALIGN(alloc_size, IIO_ALIGN); > + alloc_size =3D ALIGN(alloc_size, IIO_DMA_MINALIGN); > alloc_size +=3D sizeof_priv; > } > =20 > @@ -1650,7 +1650,7 @@ struct iio_dev *iio_device_alloc(struct device *par= ent, int sizeof_priv) > =20 > indio_dev =3D &iio_dev_opaque->indio_dev; > indio_dev->priv =3D (char *)iio_dev_opaque + > - ALIGN(sizeof(struct iio_dev_opaque), IIO_ALIGN); > + ALIGN(sizeof(struct iio_dev_opaque), IIO_DMA_MINALIGN); > =20 > indio_dev->dev.parent =3D parent; > indio_dev->dev.type =3D &iio_device_type; > diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h > index faf00f2c0be6..c4ce02293f1f 100644 > --- a/include/linux/iio/iio.h > +++ b/include/linux/iio/iio.h > @@ -9,6 +9,7 @@ > =20 > #include > #include > +#include > #include > #include > /* IIO TODO LIST */ > @@ -657,8 +658,13 @@ static inline void *iio_device_get_drvdata(const str= uct iio_dev *indio_dev) > return dev_get_drvdata(&indio_dev->dev); > } > =20 > -/* Can we make this smaller? */ > -#define IIO_ALIGN L1_CACHE_BYTES > +/* > + * Used to ensure the iio_priv() structure is aligned to allow that stru= cture > + * to in turn include IIO_DMA_MINALIGN'd elements such as buffers which > + * must not share cachelines with the rest of the structure, thus making > + * them safe for use with non-coherent DMA. > + */ > +#define IIO_DMA_MINALIGN ARCH_KMALLOC_MINALIGN > struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv); > =20 > /* The information at the returned address is guaranteed to be cacheline= aligned */