From: Christoph Hellwig <hch@lst.de>
To: Robin Murphy <robin.murphy@arm.com>
Cc: "Russell King (Oracle)" <linux@armlinux.org.uk>,
Will Deacon <will@kernel.org>,
linux-arch@vger.kernel.org, catalin.marinas@arm.com,
maz@kernel.org, mark.rutland@arm.com, hch@lst.de,
vgupta@kernel.org, arnd@arndb.de, bcain@quicinc.com,
geert@linux-m68k.org, monstr@monstr.eu, dinguyen@kernel.org,
shorne@gmail.com, mpe@ellerman.id.au, dalias@libc.org
Subject: Re: Cache maintenance for non-coherent DMA in arch_sync_dma_for_device()
Date: Wed, 8 Jun 2022 10:49:51 +0200 [thread overview]
Message-ID: <20220608084951.GB17806@lst.de> (raw)
In-Reply-To: <1a8cc7af-87ac-b0e7-7fb9-d11a5eebef55@arm.com>
On Mon, Jun 06, 2022 at 05:02:50PM +0100, Robin Murphy wrote:
> No, partial DMA writes can sometimes effectively be expected behaviour, see
> the whole SWIOTLB CVE fiasco for the most recent discussion on that:
Yes, and I still have a TODO list item for interfaces that deal
with the case of a transfer smaller than the mapping sanely, but
I haven't managed to get to it yet.
next prev parent reply other threads:[~2022-06-08 9:26 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 15:21 Cache maintenance for non-coherent DMA in arch_sync_dma_for_device() Will Deacon
2022-06-06 15:35 ` Russell King (Oracle)
2022-06-06 16:02 ` Robin Murphy
2022-06-06 16:16 ` Russell King (Oracle)
2022-06-08 8:49 ` Christoph Hellwig [this message]
2022-06-06 16:13 ` Catalin Marinas
2022-06-06 16:15 ` Ard Biesheuvel
2022-06-08 16:51 ` Catalin Marinas
2022-06-08 8:48 ` Christoph Hellwig
2022-06-08 12:02 ` Russell King (Oracle)
2022-06-08 15:14 ` Christoph Hellwig
2022-06-09 13:59 ` Will Deacon
2022-06-09 14:18 ` Christoph Hellwig
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