From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A6E1CCA47E for ; Wed, 8 Jun 2022 10:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237026AbiFHKwx (ORCPT ); Wed, 8 Jun 2022 06:52:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237075AbiFHKws (ORCPT ); Wed, 8 Jun 2022 06:52:48 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D80B10C4 for ; Wed, 8 Jun 2022 03:52:45 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id s6so32568815lfo.13 for ; Wed, 08 Jun 2022 03:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QE6MV/SSiskw4Oh1dEc1tPN6Esn/x4TkybkUdyYRtK4=; b=QKXimZ4DlV/UrPTjLnQeUTXotl36I+mbzsKE9+AsF0UVCg1gl0blsM6QuMc2uvZsqI TllJCRm6rPAYxELkm5Q8DgJpGeJl1yeIWNzQHHp0qHeLFsdpIDWJPe84VE/SqvsZVMPv AxDCF7YlKOrMwMiQVr6N2DuXL2sbsXwwa0dWQ4qE8RSWjvEcNnsIr/wxy7rRe+X5q3HT S3ITTVJAQsvtD0WFCiWe/GO6Q3mBlD9gJCQ9p8BlqdhwY8hlrLe/ENM6B11797tv4Bej 7aCDfIQ/vcfRWkRVCyqtd1Qp+HWTFOquIGvCf9oB9rVLxrdheOsklMA4E0wS0av8tfjW lUfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QE6MV/SSiskw4Oh1dEc1tPN6Esn/x4TkybkUdyYRtK4=; b=kqEuat3w2XRLfl84zXxsqf69h6URfg33/Q6hhCAPypkhQ9A3k9NcIJDDcuZfLtNjEY 4BqesqtcxKjVOZu1YXQ0eQwoEU6LcMfeh3TXKBOzDr1kMP5sexrd4OD9cXtT6EZcK8eT B1sBK24l0H8C97ZGnBr9rr4lFnC+eKwlIGYCvta/DvyVbXjaCc4yd02LgDb8W0W9tMZW K3dxENag2MWcY9VGHr4331E/KTM1CCilW2fQq63rTcybOjeahZbKgXzwx4qciwFXSoFk GjmzFYU17fZ1vfDN5MxU+MNCMzNqtJrmmzSx7fSARmrIWE/0kw0sI/bfFoyp29RwMtJD xE3Q== X-Gm-Message-State: AOAM532J5CiJhtxk9tZcw6xvuHXu0Zspe8FpU5qcd4uNquN2sjB9zCon 77x3bXdd9VGKcI3WA3bcsImkvw== X-Google-Smtp-Source: ABdhPJy1UY0nm5cKxnglUt6BuyckSKzz7cNsZxytrHA5/JnRbTh7xPy7GROuydqa75F4bBYyOPDv1w== X-Received: by 2002:a05:6512:158c:b0:479:307c:e73e with SMTP id bp12-20020a056512158c00b00479307ce73emr11963288lfb.576.1654685564535; Wed, 08 Jun 2022 03:52:44 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id e9-20020a2e5009000000b002556b0cd5acsm3232337ljb.56.2022.06.08.03.52.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jun 2022 03:52:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas Cc: Johan Hovold , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold Subject: [PATCH v11 5/5] PCI: qcom: Drop manual pipe_clk_src handling Date: Wed, 8 Jun 2022 13:52:38 +0300 Message-Id: <20220608105238.2973600-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220608105238.2973600-1-dmitry.baryshkov@linaro.org> References: <20220608105238.2973600-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Manual reparenting of pipe_clk_src is being replaced with the parking of the clock with clk_disable()/clk_enable() in the phy driver. Drop redundant code switching of the pipe clock between the PHY clock source and the safe bi_tcxo. Reviewed-by: Bjorn Andersson Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 39 +------------------------- 1 file changed, 1 insertion(+), 38 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8c1073452196..9a95ecf5a688 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -164,9 +164,6 @@ struct qcom_pcie_resources_2_7_0 { int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; - struct clk *pipe_clk_src; - struct clk *phy_pipe_clk; - struct clk *ref_clk_src; }; union qcom_pcie_resources { @@ -192,7 +189,6 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; - unsigned int pipe_clk_need_muxing:1; unsigned int has_tbu_clk:1; unsigned int has_ddrss_sf_tbu_clk:1; unsigned int has_aggre0_clk:1; @@ -1158,20 +1154,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) if (ret < 0) return ret; - if (pcie->cfg->pipe_clk_need_muxing) { - res->pipe_clk_src = devm_clk_get(dev, "pipe_mux"); - if (IS_ERR(res->pipe_clk_src)) - return PTR_ERR(res->pipe_clk_src); - - res->phy_pipe_clk = devm_clk_get(dev, "phy_pipe"); - if (IS_ERR(res->phy_pipe_clk)) - return PTR_ERR(res->phy_pipe_clk); - - res->ref_clk_src = devm_clk_get(dev, "ref"); - if (IS_ERR(res->ref_clk_src)) - return PTR_ERR(res->ref_clk_src); - } - return 0; } @@ -1189,10 +1171,6 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - /* Set TCXO as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->ref_clk_src); - ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1254,18 +1232,8 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; clk_bulk_disable_unprepare(res->num_clks, res->clks); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -} -static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) -{ - struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - - /* Set pipe clock as clock source for pcie_pipe_clk_src */ - if (pcie->cfg->pipe_clk_need_muxing) - clk_set_parent(res->pipe_clk_src, res->phy_pipe_clk); - - return 0; + regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } static int qcom_pcie_link_up(struct dw_pcie *pci) @@ -1441,7 +1409,6 @@ static const struct qcom_pcie_ops ops_2_7_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, }; /* Qcom IP rev.: 1.9.0 */ @@ -1450,7 +1417,6 @@ static const struct qcom_pcie_ops ops_1_9_0 = { .init = qcom_pcie_init_2_7_0, .deinit = qcom_pcie_deinit_2_7_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, - .post_init = qcom_pcie_post_init_2_7_0, .config_sid = qcom_pcie_config_sid_sm8250, }; @@ -1495,7 +1461,6 @@ static const struct qcom_pcie_cfg sm8250_cfg = { static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre0_clk = true, .has_aggre1_clk = true, }; @@ -1503,14 +1468,12 @@ static const struct qcom_pcie_cfg sm8450_pcie0_cfg = { static const struct qcom_pcie_cfg sm8450_pcie1_cfg = { .ops = &ops_1_9_0, .has_ddrss_sf_tbu_clk = true, - .pipe_clk_need_muxing = true, .has_aggre1_clk = true, }; static const struct qcom_pcie_cfg sc7280_cfg = { .ops = &ops_1_9_0, .has_tbu_clk = true, - .pipe_clk_need_muxing = true, }; static const struct qcom_pcie_cfg sc8180x_cfg = { -- 2.35.1