[PATCH 0/2] AIA draft v0.3.0 support for QEMU RISC-V

From: Anup Patel <apatel@ventanamicro.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atishp@atishpatra.org>,
	Anup Patel <anup@brainfault.org>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH 0/2] AIA draft v0.3.0 support for QEMU RISC-V
Date: Thu, 16 Jun 2022 08:45:41 +0530	[thread overview]
Message-ID: <20220616031543.953776-1-apatel@ventanamicro.com> (raw)

The latest AIA draft v0.3.0 addresses comments from the architecture
review committee.
(Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31)

There are primarily two changes:
1) Removing various [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum,
   and [m|s|vs]clrei;num CSRs because these CSRs were mostly for software
   convienence.
2) Simplifying the default priority assignment for local interrupts

These patches can also be found in riscv_aia_update_v1 branch at:
https://github.com/avpatel/qemu.git

Corresponding changes in OpenSBI and Linux were small and these can be
found at:
 riscv_aia_update_v1 branch of https://github.com/avpatel/opensbi.git
 riscv_aia_v1 branch of https://github.com/avpatel/linux.git

Anup Patel (2):
  target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
  target/riscv: Update default priority table for local interrupts

 target/riscv/cpu_bits.h   |  26 +------
 target/riscv/cpu_helper.c | 134 +++++++++++++++++-----------------
 target/riscv/csr.c        | 150 +-------------------------------------
 3 files changed, 72 insertions(+), 238 deletions(-)

-- 
2.34.1