From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5372C43334 for ; Mon, 20 Jun 2022 09:19:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 925CC10FABD; Mon, 20 Jun 2022 09:19:49 +0000 (UTC) Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8F8D810FA90 for ; Mon, 20 Jun 2022 09:19:42 +0000 (UTC) X-UUID: da09cf18439441d3b373eff4a761064c-20220620 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6, REQID:640ca0bd-8f32-4af4-a96e-fb1709127ac7, OB:0, LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:b14ad71, CLOUDID:7a1c882d-1756-4fa3-be7f-474a6e4be921, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: da09cf18439441d3b373eff4a761064c-20220620 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1564993028; Mon, 20 Jun 2022 17:19:34 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 20 Jun 2022 17:19:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 20 Jun 2022 17:19:33 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , Subject: [PATCH v23 07/14] drm/mediatek: add display merge async reset control Date: Mon, 20 Jun 2022 17:19:23 +0800 Message-ID: <20220620091930.27797-8-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220620091930.27797-1-nancy.lin@mediatek.com> References: <20220620091930.27797-1-nancy.lin@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Yongqiang Niu , David Airlie , "jason-jh . lin" , singo.chang@mediatek.com, llvm@lists.linux.dev, Nick Desaulniers , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Nathan Chancellor , "Nancy . Lin" , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add merge async reset control in mtk_merge_stop. Async hw doesn't do self reset on each sof signal(start of frame), so need to reset the async to clear the hw status for the next merge start. Signed-off-by: Nancy.Lin Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index 2e13d2fb429e..6428b6203ffe 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mtk_drm_ddp_comp.h" @@ -67,6 +68,7 @@ struct mtk_disp_merge { struct cmdq_client_reg cmdq_reg; bool fifo_en; bool mute_support; + struct reset_control *reset_ctl; }; void mtk_merge_start(struct device *dev) @@ -101,6 +103,9 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL); + + if (priv->async_clk) + reset_control_reset(priv->reset_ctl); } static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, @@ -264,6 +269,12 @@ static int mtk_disp_merge_probe(struct platform_device *pdev) return PTR_ERR(priv->async_clk); } + if (priv->async_clk) { + priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(priv->reset_ctl)) + return PTR_ERR(priv->reset_ctl); + } + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); if (ret) -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C349804 for ; Mon, 20 Jun 2022 09:19:42 +0000 (UTC) X-UUID: da09cf18439441d3b373eff4a761064c-20220620 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:640ca0bd-8f32-4af4-a96e-fb1709127ac7,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:b14ad71,CLOUDID:7a1c882d-1756-4fa3-be7f-474a6e4be921,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: da09cf18439441d3b373eff4a761064c-20220620 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1564993028; Mon, 20 Jun 2022 17:19:34 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 20 Jun 2022 17:19:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 20 Jun 2022 17:19:33 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "Nancy . Lin" , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Subject: [PATCH v23 07/14] drm/mediatek: add display merge async reset control Date: Mon, 20 Jun 2022 17:19:23 +0800 Message-ID: <20220620091930.27797-8-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220620091930.27797-1-nancy.lin@mediatek.com> References: <20220620091930.27797-1-nancy.lin@mediatek.com> Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Add merge async reset control in mtk_merge_stop. Async hw doesn't do self reset on each sof signal(start of frame), so need to reset the async to clear the hw status for the next merge start. Signed-off-by: Nancy.Lin Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index 2e13d2fb429e..6428b6203ffe 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mtk_drm_ddp_comp.h" @@ -67,6 +68,7 @@ struct mtk_disp_merge { struct cmdq_client_reg cmdq_reg; bool fifo_en; bool mute_support; + struct reset_control *reset_ctl; }; void mtk_merge_start(struct device *dev) @@ -101,6 +103,9 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL); + + if (priv->async_clk) + reset_control_reset(priv->reset_ctl); } static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, @@ -264,6 +269,12 @@ static int mtk_disp_merge_probe(struct platform_device *pdev) return PTR_ERR(priv->async_clk); } + if (priv->async_clk) { + priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(priv->reset_ctl)) + return PTR_ERR(priv->reset_ctl); + } + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); if (ret) -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6FF08C433EF for ; Mon, 20 Jun 2022 09:29:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pviwqdB5XG4bBwrKaqz6rHINJ8AdgjWeBdVY7wp4ybU=; b=Cemsp6HHT9FQRE MR0i8JFDEq0sZcizIQveZXRYWarWrsx7TO6FQge6bCRWKm1pOKxi3M22i6AmQL4ExCYU8KMo2tyf8 eeZVmR2fGxtWARAKR25GdRa2BU9aGoMxVAEVAU4Hdk5goID0gvFWBT2DsaNMJcQww92ASRaWy9hDj mA1ZI2D1Ka+AEonNvIEzE59OJ3olhCYqWA+2l589dt0ncNEhNFq1MnxVDhGnNL5kKGax6kwxVIsro RW4ogAdnIFMymmNoUnt/chSyuhfckQbXuJ40rxCU+T1AppgxN+XN+5PciGXObqBSRu+iP4r2sjskS PaejQimR4gteRRr89+nA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3Dha-00HB7V-UM; Mon, 20 Jun 2022 09:28:11 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o3Dfx-00HAQv-EW; Mon, 20 Jun 2022 09:26:32 +0000 X-UUID: d08a2f17798f41fc846c1450d27d4060-20220620 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.6,REQID:a04f35ec-ceb9-449b-906a-e4afc38e8eed,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:b14ad71,CLOUDID:3ede2f3d-9948-4b2a-a784-d8a6c1086106,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: d08a2f17798f41fc846c1450d27d4060-20220620 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1478185398; Mon, 20 Jun 2022 02:26:22 -0700 Received: from mtkmbs10n2.mediatek.inc (172.21.101.183) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 20 Jun 2022 02:19:37 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 20 Jun 2022 17:19:33 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 20 Jun 2022 17:19:33 +0800 From: Nancy.Lin To: Rob Herring , Matthias Brugger , Chun-Kuang Hu , "Philipp Zabel" , , "AngeloGioacchino Del Regno" , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "Nancy . Lin" , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Subject: [PATCH v23 07/14] drm/mediatek: add display merge async reset control Date: Mon, 20 Jun 2022 17:19:23 +0800 Message-ID: <20220620091930.27797-8-nancy.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220620091930.27797-1-nancy.lin@mediatek.com> References: <20220620091930.27797-1-nancy.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220620_022629_547946_572AD481 X-CRM114-Status: GOOD ( 13.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add merge async reset control in mtk_merge_stop. Async hw doesn't do self reset on each sof signal(start of frame), so need to reset the async to clear the hw status for the next merge start. Signed-off-by: Nancy.Lin Reviewed-by: CK Hu Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Tested-by: Bo-Chen Chen --- drivers/gpu/drm/mediatek/mtk_disp_merge.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index 2e13d2fb429e..6428b6203ffe 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "mtk_drm_ddp_comp.h" @@ -67,6 +68,7 @@ struct mtk_disp_merge { struct cmdq_client_reg cmdq_reg; bool fifo_en; bool mute_support; + struct reset_control *reset_ctl; }; void mtk_merge_start(struct device *dev) @@ -101,6 +103,9 @@ void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt) mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL); + + if (priv->async_clk) + reset_control_reset(priv->reset_ctl); } static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, @@ -264,6 +269,12 @@ static int mtk_disp_merge_probe(struct platform_device *pdev) return PTR_ERR(priv->async_clk); } + if (priv->async_clk) { + priv->reset_ctl = devm_reset_control_get_optional_exclusive(dev, NULL); + if (IS_ERR(priv->reset_ctl)) + return PTR_ERR(priv->reset_ctl); + } + #if IS_REACHABLE(CONFIG_MTK_CMDQ) ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0); if (ret) -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel