From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3C70FC433EF for ; Mon, 20 Jun 2022 10:54:58 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F08D380584; Mon, 20 Jun 2022 12:54:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="O/W5Nr7g"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 586D8805F4; Mon, 20 Jun 2022 12:54:55 +0200 (CEST) Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 36F5F803DF for ; Mon, 20 Jun 2022 12:54:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=kernel.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C4545B8101F; Mon, 20 Jun 2022 10:54:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 53D77C3411B; Mon, 20 Jun 2022 10:54:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1655722491; bh=deKKv6vs33fYWu5UXad+PnrgSNRVUGj6oM+lXiyzV4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O/W5Nr7gXCJYM2bHU6Ok8BmOwdVrvE3P1SvTVzv+ted0H6wVAHQqCc6TqErMMVDyw BkMWrt8R/iVOkjXyE+qY9Yfk7jyzbw0VYQ9IYRXGDVLS9gj+Z3kwESymWChfRC59F/ J0Z8/9fRP1y9bb6VOsmIkEyqYhxQdKRqXxtR8ubF621CZ36OvnK7I/mK/YSx6L9REd nZHi5ftR5VivRatLpHaP+RCFrD+ZLL8gWh+z/5xm7dQrBpFUJe4ERvwHfhMsjzaE9P OCuB+1ORcAdE5s58S6H4yYZGF2ZSv2BQhgVa3vcFJtUehNtwJ5GPCib5buGUJKKwBI z++auSz8uq2RQ== Received: by pali.im (Postfix) id 2FD90F8F; Mon, 20 Jun 2022 12:54:48 +0200 (CEST) From: =?UTF-8?q?Pali=20Roh=C3=A1r?= To: "Peng Fan (OSS)" Cc: Jaehoon Chung , Priyanka Jain , Sinan Akman , u-boot@lists.denx.de Subject: [PATCH v2] mmc: fsl_esdhc_spl: Add support for loading proper U-Boot from unaligned location Date: Mon, 20 Jun 2022 12:54:26 +0200 Message-Id: <20220620105426.23665-1-pali@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <129747c1-2218-f319-9e30-528fb9adbb31@oss.nxp.com> References: <129747c1-2218-f319-9e30-528fb9adbb31@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean This allows to concatenate SPL and proper U-Boot without extra alignment. Signed-off-by: Pali Rohár --- Changes in v2: * Rebased on top of the U-Boot next branch, commit 98c4828740f4944462b7d9608b95d5b73850c7b0 --- drivers/mmc/fsl_esdhc_spl.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_spl.c b/drivers/mmc/fsl_esdhc_spl.c index 760f13d24018..54bf8152ca7a 100644 --- a/drivers/mmc/fsl_esdhc_spl.c +++ b/drivers/mmc/fsl_esdhc_spl.c @@ -58,10 +58,10 @@ void __noreturn mmc_boot(void) { __attribute__((noreturn)) void (*uboot)(void); uint blk_start, blk_cnt, err; + u32 blk_off; #ifndef CONFIG_FSL_CORENET uchar *tmp_buf; u32 blklen; - u32 blk_off; uchar val; #ifndef CONFIG_SPL_FSL_PBL u32 val32; @@ -155,10 +155,21 @@ again: * Load U-Boot image from mmc into RAM */ code_len = CONFIG_SYS_MMC_U_BOOT_SIZE; - blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len; - blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len; + blk_start = offset / mmc->read_bl_len; + blk_off = offset % mmc->read_bl_len; + blk_cnt = ALIGN(code_len, mmc->read_bl_len) / mmc->read_bl_len + 1; + if (blk_off) { + err = mmc->block_dev.block_read(&mmc->block_dev, + blk_start, 1, tmp_buf); + if (err != 1) { + puts("spl: mmc read failed!!\n"); + hang(); + } + blk_start++; + } err = mmc->block_dev.block_read(&mmc->block_dev, blk_start, blk_cnt, - (uchar *)CONFIG_SYS_MMC_U_BOOT_DST); + (uchar *)CONFIG_SYS_MMC_U_BOOT_DST + + (blk_off ? (mmc->read_bl_len - blk_off) : 0)); if (err != blk_cnt) { puts("spl: mmc read failed!!\n"); #ifndef CONFIG_FSL_CORENET @@ -166,6 +177,14 @@ again: #endif hang(); } + /* + * SDHC DMA may erase bytes at dst + bl_len - blk_off - 8 + * due to unaligned access. So copy leading bytes from tmp_buf + * after SDHC DMA transfer. + */ + if (blk_off) + memcpy((uchar *)CONFIG_SYS_MMC_U_BOOT_DST, + tmp_buf + blk_off, mmc->read_bl_len - blk_off); /* * Clean d-cache and invalidate i-cache, to -- 2.20.1