From: Atish Patra <atishp@rivosinc.com>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Atish Patra <atishp@rivosinc.com>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
qemu-riscv@nongnu.org, frank.chang@sifive.com
Subject: [PATCH v10 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
Date: Mon, 20 Jun 2022 16:15:52 -0700 [thread overview]
Message-ID: <20220620231603.2547260-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20220620231603.2547260-1-atishp@rivosinc.com>
From: Atish Patra <atish.patra@wdc.com>
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 46bd417cc182..58d07c511f98 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -79,6 +79,57 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if (env->priv == PRV_S) {
+ switch (csrno) {
+ case CSR_CYCLE:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIME:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRET:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ switch (csrno) {
+ case CSR_CYCLEH:
+ if (!get_field(env->mcounteren, COUNTEREN_CY)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_TIMEH:
+ if (!get_field(env->mcounteren, COUNTEREN_TM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_INSTRETH:
+ if (!get_field(env->mcounteren, COUNTEREN_IR)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->mcounteren, 1 << ctr_index)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ break;
+ }
+ }
+ }
+
if (riscv_cpu_virt_enabled(env)) {
switch (csrno) {
case CSR_CYCLE:
--
2.25.1
next prev parent reply other threads:[~2022-06-20 23:19 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-20 23:15 [PATCH v10 00/12] Improve PMU support Atish Patra
2022-06-20 23:15 ` [PATCH v10 01/12] target/riscv: Fix PMU CSR predicate function Atish Patra
2022-06-20 23:15 ` Atish Patra [this message]
2022-06-20 23:15 ` [PATCH v10 03/12] target/riscv: pmu: Rename the counters extension to pmu Atish Patra
2022-06-20 23:15 ` [PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable Atish Patra
2022-07-04 15:26 ` Weiwei Li
2022-07-05 0:38 ` Weiwei Li
2022-07-05 7:51 ` Atish Kumar Patra
2022-07-05 8:16 ` Weiwei Li
2022-07-26 22:19 ` Atish Patra
2022-06-20 23:15 ` [PATCH v10 05/12] target/riscv: Implement mcountinhibit CSR Atish Patra
2022-07-04 15:31 ` Weiwei Li
2022-07-05 7:47 ` Atish Kumar Patra
2022-06-20 23:15 ` [PATCH v10 06/12] target/riscv: Add support for hpmcounters/hpmevents Atish Patra
2022-06-20 23:15 ` [PATCH v10 07/12] target/riscv: Support mcycle/minstret write operation Atish Patra
2022-06-20 23:15 ` [PATCH v10 08/12] target/riscv: Add sscofpmf extension support Atish Patra
2022-07-05 0:31 ` Weiwei Li
2022-07-05 1:30 ` Weiwei Li
2022-07-05 7:36 ` Atish Kumar Patra
2022-07-05 7:48 ` Weiwei Li
2022-07-14 9:53 ` Heiko Stübner
2022-07-18 1:23 ` Alistair Francis
2022-06-20 23:15 ` [PATCH v10 09/12] target/riscv: Simplify counter predicate function Atish Patra
2022-07-04 15:19 ` Weiwei Li
2022-07-05 8:00 ` Atish Kumar Patra
2022-07-05 8:41 ` Weiwei Li
2022-07-14 9:54 ` Heiko Stübner
2022-06-20 23:16 ` [PATCH v10 10/12] target/riscv: Add few cache related PMU events Atish Patra
2022-07-14 9:55 ` Heiko Stübner
2022-06-20 23:16 ` [PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree Atish Patra
2022-07-14 10:27 ` Heiko Stübner
2022-07-26 21:51 ` Atish Patra
2022-06-20 23:16 ` [PATCH v10 12/12] target/riscv: Update the privilege field for sscofpmf CSRs Atish Patra
2022-07-14 10:29 ` Heiko Stübner
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