From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4384FC433EF for ; Tue, 21 Jun 2022 10:21:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347769AbiFUKU7 (ORCPT ); Tue, 21 Jun 2022 06:20:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243563AbiFUKUx (ORCPT ); Tue, 21 Jun 2022 06:20:53 -0400 Received: from mx0b-001ae601.pphosted.com (mx0a-001ae601.pphosted.com [67.231.149.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B396A2871C for ; Tue, 21 Jun 2022 03:20:52 -0700 (PDT) Received: from pps.filterd (m0077473.ppops.net [127.0.0.1]) by mx0a-001ae601.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 25L7wQ94011194; Tue, 21 Jun 2022 05:20:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cirrus.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=PODMain02222019; bh=V8BsBPLcWqkZbi4o13owpXVyxD3Le6lVb4WyABIu+K0=; b=lYL4jHyyasDxuSDllGvsUPULf8L2aYvQl16sTr2dhp9s6JHuYWBrhP3Na+3EzQi399Pr EADiAb1wwCIelMkM+Bcj/ZdtLdZ8MAi6CSna1WkzeNWwhfLhnX1+POTERcTr5qIcki0G aCLMcCNNhyxdOCdzzZ0qNXNSEgScjmPzOJ28AseLbdUTzO1/NOA7uc7+BVSXrTBm/9oT jrsIB7qe+0A05OdQh4pPR36ACmC/eI50b5I0DNUMUuImGNl3GPStSZuP/bu5vSxaD1ON koGVUR5F5Lx4oNCZT3y9RMX1pzYLXZyA7DzQNLlqmPniT7Ukd7uaXnT9U4BBsSx2l66W Vg== Received: from ediex02.ad.cirrus.com ([84.19.233.68]) by mx0a-001ae601.pphosted.com (PPS) with ESMTPS id 3gsc41bcxp-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Tue, 21 Jun 2022 05:20:46 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 21 Jun 2022 11:20:42 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Tue, 21 Jun 2022 11:20:42 +0100 Received: from algalon.ad.cirrus.com (algalon.ad.cirrus.com [198.90.251.122]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 2C35D11D4; Tue, 21 Jun 2022 10:20:42 +0000 (UTC) From: Charles Keepax To: CC: , , , , , Subject: [PATCH 4/4] ASoC: core: Add new SOC_DOUBLE_SX_TLV macro Date: Tue, 21 Jun 2022 11:20:41 +0100 Message-ID: <20220621102041.1713504-4-ckeepax@opensource.cirrus.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220621102041.1713504-1-ckeepax@opensource.cirrus.com> References: <20220621102041.1713504-1-ckeepax@opensource.cirrus.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: n4YPNgZV-FIDC4NVgaabiWhq3SJmMRbO X-Proofpoint-ORIG-GUID: n4YPNgZV-FIDC4NVgaabiWhq3SJmMRbO X-Proofpoint-Spam-Reason: safe Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently macros only exist for SX style (implicit sign bit 2's compliment) volume controls where the volumes for left and right are in separate registers. Some future Cirrus devices will have both volumes in the same register, as such add a new macro to support this. Signed-off-by: Charles Keepax --- include/sound/soc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/sound/soc.h b/include/sound/soc.h index 8909cc7d311ef..76ee3c2b8b56c 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -136,6 +136,18 @@ .put = snd_soc_put_volsw, \ .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ max, invert, 0) } +#define SOC_DOUBLE_SX_TLV(xname, xreg, shift_left, shift_right, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx, \ + .put = snd_soc_put_volsw_sx, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, \ + .shift = shift_left, .rshift = shift_right, \ + .max = xmax, .min = xmin} } #define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ -- 2.30.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F700C433EF for ; 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Tue, 21 Jun 2022 05:20:46 -0500 Received: from EDIEX01.ad.cirrus.com (198.61.84.80) by EDIEX02.ad.cirrus.com (198.61.84.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Tue, 21 Jun 2022 11:20:42 +0100 Received: from ediswmail.ad.cirrus.com (198.61.86.93) by EDIEX01.ad.cirrus.com (198.61.84.80) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Tue, 21 Jun 2022 11:20:42 +0100 Received: from algalon.ad.cirrus.com (algalon.ad.cirrus.com [198.90.251.122]) by ediswmail.ad.cirrus.com (Postfix) with ESMTP id 2C35D11D4; Tue, 21 Jun 2022 10:20:42 +0000 (UTC) From: Charles Keepax To: Subject: [PATCH 4/4] ASoC: core: Add new SOC_DOUBLE_SX_TLV macro Date: Tue, 21 Jun 2022 11:20:41 +0100 Message-ID: <20220621102041.1713504-4-ckeepax@opensource.cirrus.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220621102041.1713504-1-ckeepax@opensource.cirrus.com> References: <20220621102041.1713504-1-ckeepax@opensource.cirrus.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: n4YPNgZV-FIDC4NVgaabiWhq3SJmMRbO X-Proofpoint-ORIG-GUID: n4YPNgZV-FIDC4NVgaabiWhq3SJmMRbO X-Proofpoint-Spam-Reason: safe Cc: alsa-devel@alsa-project.org, patches@opensource.cirrus.com, lgirdwood@gmail.com, david.rhodes@cirrus.com, james.schulman@cirrus.com, linux-kernel@vger.kernel.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Currently macros only exist for SX style (implicit sign bit 2's compliment) volume controls where the volumes for left and right are in separate registers. Some future Cirrus devices will have both volumes in the same register, as such add a new macro to support this. Signed-off-by: Charles Keepax --- include/sound/soc.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/sound/soc.h b/include/sound/soc.h index 8909cc7d311ef..76ee3c2b8b56c 100644 --- a/include/sound/soc.h +++ b/include/sound/soc.h @@ -136,6 +136,18 @@ .put = snd_soc_put_volsw, \ .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ max, invert, 0) } +#define SOC_DOUBLE_SX_TLV(xname, xreg, shift_left, shift_right, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx, \ + .put = snd_soc_put_volsw_sx, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, \ + .shift = shift_left, .rshift = shift_right, \ + .max = xmax, .min = xmin} } #define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ -- 2.30.2