[PATCH 09/10] target/loongarch: Fix the meaning of ECFG reg's VS field

From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, gaosong@loongson.cn,
	maobibo@loongson.cn, mark.cave-ayland@ilande.co.uk,
	mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca,
	f4bug@amsat.org, peter.maydell@linaro.org,
	chenhuacai@loongson.cn
Subject: [PATCH 09/10] target/loongarch: Fix the meaning of ECFG reg's VS field
Date: Wed, 22 Jun 2022 18:43:00 +0800	[thread overview]
Message-ID: <20220622104301.804447-10-yangxiaojuan@loongson.cn> (raw)
In-Reply-To: <20220622104301.804447-1-yangxiaojuan@loongson.cn>

By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
 target/loongarch/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 401d3fd30a..d1a87e8e1c 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -219,6 +219,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
     env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
     env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
 
+    if (vec_size) {
+        vec_size = (1 << vec_size) * 4;
+    }
+
     if  (cs->exception_index == EXCCODE_INT) {
         /* Interrupt */
         uint32_t vector = 0;
-- 
2.31.1


