[PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC

[PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC

[Lad Prabhakar]

Hi All,

This patch series adds PLIC support for Renesas RZ/Five SoC.

Sending this as an RFC based on the discussion [0].

This patches have been tested with I2C and DMAC interface as these
blocks have EDGE interrupts.

[0] https://lore.kernel.org/linux-arm-kernel/87o80a7t2z.wl-maz@kernel.org/T/

v1-v2:
* Fixed review comments pointed by Marc and Krzysztof.

RFC-->v1:
* Fixed review comments pointed by Rob and Geert.
* Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC.

RFC: https://lore.kernel.org/linux-renesas-soc/
20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com/T/

Cheers,
Prabhakar

Lad Prabhakar (2):
  dt-bindings: interrupt-controller: sifive,plic: Document Renesas
    RZ/Five SoC
  irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

 .../sifive,plic-1.0.0.yaml                    | 44 ++++++++++-
 drivers/irqchip/Kconfig                       |  1 +
 drivers/irqchip/irq-sifive-plic.c             | 73 ++++++++++++++++++-
 3 files changed, 113 insertions(+), 5 deletions(-)

-- 
2.25.1

[PATCH v2 0/2] Add PLIC support for Renesas RZ/Five SoC

[Lad Prabhakar]

Hi All,

This patch series adds PLIC support for Renesas RZ/Five SoC.

Sending this as an RFC based on the discussion [0].

This patches have been tested with I2C and DMAC interface as these
blocks have EDGE interrupts.

[0] https://lore.kernel.org/linux-arm-kernel/87o80a7t2z.wl-maz@kernel.org/T/

v1-v2:
* Fixed review comments pointed by Marc and Krzysztof.

RFC-->v1:
* Fixed review comments pointed by Rob and Geert.
* Changed implementation for EDGE interrupt handling on Renesas RZ/Five SoC.

RFC: https://lore.kernel.org/linux-renesas-soc/
20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com/T/

Cheers,
Prabhakar

Lad Prabhakar (2):
  dt-bindings: interrupt-controller: sifive,plic: Document Renesas
    RZ/Five SoC
  irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

 .../sifive,plic-1.0.0.yaml                    | 44 ++++++++++-
 drivers/irqchip/Kconfig                       |  1 +
 drivers/irqchip/irq-sifive-plic.c             | 73 ++++++++++++++++++-
 3 files changed, 113 insertions(+), 5 deletions(-)

-- 
2.25.1


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[PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Lad Prabhakar]

Document Renesas RZ/Five (R9A07G043) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Fixed binding doc
* Fixed review comments pointed by Krzysztof.

RFC->v1:
* Fixed Review comments pointed by Geert and Rob
---
 .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 27092c6a86c4..59df367d1e44 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -28,7 +28,10 @@ description:
 
   While the PLIC supports both edge-triggered and level-triggered interrupts,
   interrupt handlers are oblivious to this distinction and therefore it is not
-  specified in the PLIC device-tree binding.
+  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
+  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
+  to specify the interrupt type as the flow for EDGE interrupts is different
+  compared to LEVEL interrupts.
 
   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -57,6 +60,7 @@ properties:
           - enum:
               - allwinner,sun20i-d1-plic
           - const: thead,c900-plic
+      - const: renesas,r9a07g043-plic
 
   reg:
     maxItems: 1
@@ -64,8 +68,7 @@ properties:
   '#address-cells':
     const: 0
 
-  '#interrupt-cells':
-    const: 1
+  '#interrupt-cells': true
 
   interrupt-controller: true
 
@@ -82,6 +85,12 @@ properties:
     description:
       Specifies how many external interrupts are supported by this controller.
 
+  clocks: true
+
+  power-domains: true
+
+  resets: true
+
 required:
   - compatible
   - '#address-cells'
@@ -91,6 +100,35 @@ required:
   - interrupts-extended
   - riscv,ndev
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043-plic
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        power-domains:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+        '#interrupt-cells':
+          const: 2
+
+      required:
+        - clocks
+        - resets
+        - power-domains
+    else:
+      properties:
+        '#interrupt-cells':
+          const: 1
+
 additionalProperties: false
 
 examples:
-- 
2.25.1

[PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Lad Prabhakar]

Document Renesas RZ/Five (R9A07G043) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Fixed binding doc
* Fixed review comments pointed by Krzysztof.

RFC->v1:
* Fixed Review comments pointed by Geert and Rob
---
 .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 27092c6a86c4..59df367d1e44 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -28,7 +28,10 @@ description:
 
   While the PLIC supports both edge-triggered and level-triggered interrupts,
   interrupt handlers are oblivious to this distinction and therefore it is not
-  specified in the PLIC device-tree binding.
+  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
+  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
+  to specify the interrupt type as the flow for EDGE interrupts is different
+  compared to LEVEL interrupts.
 
   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -57,6 +60,7 @@ properties:
           - enum:
               - allwinner,sun20i-d1-plic
           - const: thead,c900-plic
+      - const: renesas,r9a07g043-plic
 
   reg:
     maxItems: 1
@@ -64,8 +68,7 @@ properties:
   '#address-cells':
     const: 0
 
-  '#interrupt-cells':
-    const: 1
+  '#interrupt-cells': true
 
   interrupt-controller: true
 
@@ -82,6 +85,12 @@ properties:
     description:
       Specifies how many external interrupts are supported by this controller.
 
+  clocks: true
+
+  power-domains: true
+
+  resets: true
+
 required:
   - compatible
   - '#address-cells'
@@ -91,6 +100,35 @@ required:
   - interrupts-extended
   - riscv,ndev
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043-plic
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        power-domains:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+        '#interrupt-cells':
+          const: 2
+
+      required:
+        - clocks
+        - resets
+        - power-domains
+    else:
+      properties:
+        '#interrupt-cells':
+          const: 1
+
 additionalProperties: false
 
 examples:
-- 
2.25.1


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[PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad Prabhakar]

The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
edge until the previous completion message has been received and
NCEPLIC100 doesn't support pending interrupt counter, hence losing the
interrupts if not acknowledged in time.

So the workaround for edge-triggered interrupts to be handled correctly
and without losing is that it needs to be acknowledged first and then
handler must be run so that we don't miss on the next edge-triggered
interrupt.

This patch adds a new compatible string for Renesas RZ/Five SoC and adds
support to change interrupt flow based on the interrupt type. It also
implements irq_ack and irq_set_type callbacks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Implemented IRQ flow as suggested by Marc

RFC-->v1:
* Fixed review comments pointed by Geert
* Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
claim the interrupt by reading the register and then acknowledge it.
* Add a new chained handler for RZ/Five SoC.
---
 drivers/irqchip/Kconfig           |  1 +
 drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
 2 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4ab1038b5482..0245dcabe3e9 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -530,6 +530,7 @@ config SIFIVE_PLIC
 	bool "SiFive Platform-Level Interrupt Controller"
 	depends on RISCV
 	select IRQ_DOMAIN_HIERARCHY
+	select IRQ_FASTEOI_HIERARCHY_HANDLERS
 	help
 	   This enables support for the PLIC chip found in SiFive (and
 	   potentially other) RISC-V systems.  The PLIC controls devices
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index bb87e4c3b88e..9fb9f62afb6a 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -60,10 +60,13 @@
 #define	PLIC_DISABLE_THRESHOLD		0x7
 #define	PLIC_ENABLE_THRESHOLD		0
 
+#define RENESAS_R9A07G043_PLIC		1
+
 struct plic_priv {
 	struct cpumask lmask;
 	struct irq_domain *irqdomain;
 	void __iomem *regs;
+	u8 of_data;
 };
 
 struct plic_handler {
@@ -81,6 +84,8 @@ static int plic_parent_irq __ro_after_init;
 static bool plic_cpuhp_setup_done __ro_after_init;
 static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
 
+static int plic_irq_set_type(struct irq_data *d, unsigned int type);
+
 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
 {
 	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
@@ -176,16 +181,61 @@ static void plic_irq_eoi(struct irq_data *d)
 	}
 }
 
+static void renesas_rzfive_plic_edge_irq_eoi(struct irq_data *data)
+{
+	/* We have nothing to do here */
+}
+
 static struct irq_chip plic_chip = {
 	.name		= "SiFive PLIC",
 	.irq_mask	= plic_irq_mask,
 	.irq_unmask	= plic_irq_unmask,
 	.irq_eoi	= plic_irq_eoi,
+	.irq_set_type	= plic_irq_set_type,
+#ifdef CONFIG_SMP
+	.irq_set_affinity = plic_set_affinity,
+#endif
+};
+
+static struct irq_chip renesas_rzfive_edge_plic_chip = {
+	.name		= "Renesas RZ/Five PLIC",
+	.irq_mask	= plic_irq_mask,
+	.irq_unmask	= plic_irq_unmask,
+	.irq_ack	= plic_irq_eoi,
+	.irq_eoi	= renesas_rzfive_plic_edge_irq_eoi,
+	.irq_set_type	= plic_irq_set_type,
 #ifdef CONFIG_SMP
 	.irq_set_affinity = plic_set_affinity,
 #endif
 };
 
+static int plic_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
+
+	if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
+		return 0;
+
+	switch (type) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
+						 handle_fasteoi_ack_irq,
+						 "Edge");
+		break;
+
+	case IRQ_TYPE_EDGE_RISING:
+		irq_set_chip_handler_name_locked(d, &plic_chip,
+						 handle_fasteoi_irq,
+						 "Level");
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 			      irq_hw_number_t hwirq)
 {
@@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 	return 0;
 }
 
+static int plic_irq_domain_translate(struct irq_domain *d,
+				     struct irq_fwspec *fwspec,
+				     unsigned long *hwirq,
+				     unsigned int *type)
+{
+	struct plic_priv *priv = d->host_data;
+
+	if (priv->of_data == RENESAS_R9A07G043_PLIC)
+		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
+
+	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
+}
+
 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 				 unsigned int nr_irqs, void *arg)
 {
@@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 	unsigned int type;
 	struct irq_fwspec *fwspec = arg;
 
-	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
+	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
 	if (ret)
 		return ret;
 
@@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 }
 
 static const struct irq_domain_ops plic_irqdomain_ops = {
-	.translate	= irq_domain_translate_onecell,
+	.translate	= plic_irq_domain_translate,
 	.alloc		= plic_irq_domain_alloc,
 	.free		= irq_domain_free_irqs_top,
 };
@@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
 	if (!priv)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
+		priv->of_data = RENESAS_R9A07G043_PLIC;
+		plic_chip.name = "Renesas RZ/Five PLIC";
+	}
+
 	priv->regs = of_iomap(node, 0);
 	if (WARN_ON(!priv->regs)) {
 		error = -EIO;
@@ -411,5 +479,6 @@ static int __init plic_init(struct device_node *node,
 }
 
 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
+IRQCHIP_DECLARE(renesas_r9a07g043_plic, "renesas,r9a07g043-plic", plic_init);
 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
-- 
2.25.1

[PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad Prabhakar]

The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
edge until the previous completion message has been received and
NCEPLIC100 doesn't support pending interrupt counter, hence losing the
interrupts if not acknowledged in time.

So the workaround for edge-triggered interrupts to be handled correctly
and without losing is that it needs to be acknowledged first and then
handler must be run so that we don't miss on the next edge-triggered
interrupt.

This patch adds a new compatible string for Renesas RZ/Five SoC and adds
support to change interrupt flow based on the interrupt type. It also
implements irq_ack and irq_set_type callbacks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2:
* Implemented IRQ flow as suggested by Marc

RFC-->v1:
* Fixed review comments pointed by Geert
* Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
claim the interrupt by reading the register and then acknowledge it.
* Add a new chained handler for RZ/Five SoC.
---
 drivers/irqchip/Kconfig           |  1 +
 drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
 2 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 4ab1038b5482..0245dcabe3e9 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -530,6 +530,7 @@ config SIFIVE_PLIC
 	bool "SiFive Platform-Level Interrupt Controller"
 	depends on RISCV
 	select IRQ_DOMAIN_HIERARCHY
+	select IRQ_FASTEOI_HIERARCHY_HANDLERS
 	help
 	   This enables support for the PLIC chip found in SiFive (and
 	   potentially other) RISC-V systems.  The PLIC controls devices
diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index bb87e4c3b88e..9fb9f62afb6a 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -60,10 +60,13 @@
 #define	PLIC_DISABLE_THRESHOLD		0x7
 #define	PLIC_ENABLE_THRESHOLD		0
 
+#define RENESAS_R9A07G043_PLIC		1
+
 struct plic_priv {
 	struct cpumask lmask;
 	struct irq_domain *irqdomain;
 	void __iomem *regs;
+	u8 of_data;
 };
 
 struct plic_handler {
@@ -81,6 +84,8 @@ static int plic_parent_irq __ro_after_init;
 static bool plic_cpuhp_setup_done __ro_after_init;
 static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
 
+static int plic_irq_set_type(struct irq_data *d, unsigned int type);
+
 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
 {
 	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
@@ -176,16 +181,61 @@ static void plic_irq_eoi(struct irq_data *d)
 	}
 }
 
+static void renesas_rzfive_plic_edge_irq_eoi(struct irq_data *data)
+{
+	/* We have nothing to do here */
+}
+
 static struct irq_chip plic_chip = {
 	.name		= "SiFive PLIC",
 	.irq_mask	= plic_irq_mask,
 	.irq_unmask	= plic_irq_unmask,
 	.irq_eoi	= plic_irq_eoi,
+	.irq_set_type	= plic_irq_set_type,
+#ifdef CONFIG_SMP
+	.irq_set_affinity = plic_set_affinity,
+#endif
+};
+
+static struct irq_chip renesas_rzfive_edge_plic_chip = {
+	.name		= "Renesas RZ/Five PLIC",
+	.irq_mask	= plic_irq_mask,
+	.irq_unmask	= plic_irq_unmask,
+	.irq_ack	= plic_irq_eoi,
+	.irq_eoi	= renesas_rzfive_plic_edge_irq_eoi,
+	.irq_set_type	= plic_irq_set_type,
 #ifdef CONFIG_SMP
 	.irq_set_affinity = plic_set_affinity,
 #endif
 };
 
+static int plic_irq_set_type(struct irq_data *d, unsigned int type)
+{
+	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
+
+	if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
+		return 0;
+
+	switch (type) {
+	case IRQ_TYPE_LEVEL_HIGH:
+		irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
+						 handle_fasteoi_ack_irq,
+						 "Edge");
+		break;
+
+	case IRQ_TYPE_EDGE_RISING:
+		irq_set_chip_handler_name_locked(d, &plic_chip,
+						 handle_fasteoi_irq,
+						 "Level");
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 			      irq_hw_number_t hwirq)
 {
@@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 	return 0;
 }
 
+static int plic_irq_domain_translate(struct irq_domain *d,
+				     struct irq_fwspec *fwspec,
+				     unsigned long *hwirq,
+				     unsigned int *type)
+{
+	struct plic_priv *priv = d->host_data;
+
+	if (priv->of_data == RENESAS_R9A07G043_PLIC)
+		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
+
+	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
+}
+
 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 				 unsigned int nr_irqs, void *arg)
 {
@@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 	unsigned int type;
 	struct irq_fwspec *fwspec = arg;
 
-	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
+	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
 	if (ret)
 		return ret;
 
@@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 }
 
 static const struct irq_domain_ops plic_irqdomain_ops = {
-	.translate	= irq_domain_translate_onecell,
+	.translate	= plic_irq_domain_translate,
 	.alloc		= plic_irq_domain_alloc,
 	.free		= irq_domain_free_irqs_top,
 };
@@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
 	if (!priv)
 		return -ENOMEM;
 
+	if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
+		priv->of_data = RENESAS_R9A07G043_PLIC;
+		plic_chip.name = "Renesas RZ/Five PLIC";
+	}
+
 	priv->regs = of_iomap(node, 0);
 	if (WARN_ON(!priv->regs)) {
 		error = -EIO;
@@ -411,5 +479,6 @@ static int __init plic_init(struct device_node *node,
 }
 
 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
+IRQCHIP_DECLARE(renesas_r9a07g043_plic, "renesas,r9a07g043-plic", plic_init);
 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
-- 
2.25.1


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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On Sun, 26 Jun 2022 01:43:26 +0100,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> 
> The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> edge until the previous completion message has been received and
> NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> interrupts if not acknowledged in time.
> 
> So the workaround for edge-triggered interrupts to be handled correctly
> and without losing is that it needs to be acknowledged first and then
> handler must be run so that we don't miss on the next edge-triggered
> interrupt.
> 
> This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> support to change interrupt flow based on the interrupt type. It also
> implements irq_ack and irq_set_type callbacks.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Implemented IRQ flow as suggested by Marc
> 
> RFC-->v1:
> * Fixed review comments pointed by Geert
> * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> claim the interrupt by reading the register and then acknowledge it.
> * Add a new chained handler for RZ/Five SoC.
> ---
>  drivers/irqchip/Kconfig           |  1 +
>  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
>  2 files changed, 72 insertions(+), 2 deletions(-)

[...]

>
> +static int plic_irq_set_type(struct irq_data *d, unsigned int type)
> +{
> +	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> +
> +	if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
> +		return 0;
> +
> +	switch (type) {
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
> +						 handle_fasteoi_ack_irq,
> +						 "Edge");
> +		break;
> +
> +	case IRQ_TYPE_EDGE_RISING:
> +		irq_set_chip_handler_name_locked(d, &plic_chip,
> +						 handle_fasteoi_irq,
> +						 "Level");
> +		break;

Really? Have you even tested this?

> +
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  			      irq_hw_number_t hwirq)
>  {
> @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  	return 0;
>  }
>  
> +static int plic_irq_domain_translate(struct irq_domain *d,
> +				     struct irq_fwspec *fwspec,
> +				     unsigned long *hwirq,
> +				     unsigned int *type)
> +{
> +	struct plic_priv *priv = d->host_data;
> +
> +	if (priv->of_data == RENESAS_R9A07G043_PLIC)
> +		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
> +
> +	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
> +}
> +
>  static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  				 unsigned int nr_irqs, void *arg)
>  {
> @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  	unsigned int type;
>  	struct irq_fwspec *fwspec = arg;
>  
> -	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
> +	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
>  	if (ret)
>  		return ret;
>  
> @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  }
>  
>  static const struct irq_domain_ops plic_irqdomain_ops = {
> -	.translate	= irq_domain_translate_onecell,
> +	.translate	= plic_irq_domain_translate,
>  	.alloc		= plic_irq_domain_alloc,
>  	.free		= irq_domain_free_irqs_top,
>  };
> @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
>  	if (!priv)
>  		return -ENOMEM;
>  
> +	if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> +		priv->of_data = RENESAS_R9A07G043_PLIC;
> +		plic_chip.name = "Renesas RZ/Five PLIC";

NAK. The irq_chip structure isn't the place for platform marketing.
This is way too long anyway (and same for the edge version), and you
even sent me a patch to make that structure const...

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On Sun, 26 Jun 2022 01:43:26 +0100,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> 
> The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> edge until the previous completion message has been received and
> NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> interrupts if not acknowledged in time.
> 
> So the workaround for edge-triggered interrupts to be handled correctly
> and without losing is that it needs to be acknowledged first and then
> handler must be run so that we don't miss on the next edge-triggered
> interrupt.
> 
> This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> support to change interrupt flow based on the interrupt type. It also
> implements irq_ack and irq_set_type callbacks.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Implemented IRQ flow as suggested by Marc
> 
> RFC-->v1:
> * Fixed review comments pointed by Geert
> * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> claim the interrupt by reading the register and then acknowledge it.
> * Add a new chained handler for RZ/Five SoC.
> ---
>  drivers/irqchip/Kconfig           |  1 +
>  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
>  2 files changed, 72 insertions(+), 2 deletions(-)

[...]

>
> +static int plic_irq_set_type(struct irq_data *d, unsigned int type)
> +{
> +	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> +
> +	if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
> +		return 0;
> +
> +	switch (type) {
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
> +						 handle_fasteoi_ack_irq,
> +						 "Edge");
> +		break;
> +
> +	case IRQ_TYPE_EDGE_RISING:
> +		irq_set_chip_handler_name_locked(d, &plic_chip,
> +						 handle_fasteoi_irq,
> +						 "Level");
> +		break;

Really? Have you even tested this?

> +
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  			      irq_hw_number_t hwirq)
>  {
> @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  	return 0;
>  }
>  
> +static int plic_irq_domain_translate(struct irq_domain *d,
> +				     struct irq_fwspec *fwspec,
> +				     unsigned long *hwirq,
> +				     unsigned int *type)
> +{
> +	struct plic_priv *priv = d->host_data;
> +
> +	if (priv->of_data == RENESAS_R9A07G043_PLIC)
> +		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
> +
> +	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
> +}
> +
>  static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  				 unsigned int nr_irqs, void *arg)
>  {
> @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  	unsigned int type;
>  	struct irq_fwspec *fwspec = arg;
>  
> -	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
> +	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
>  	if (ret)
>  		return ret;
>  
> @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  }
>  
>  static const struct irq_domain_ops plic_irqdomain_ops = {
> -	.translate	= irq_domain_translate_onecell,
> +	.translate	= plic_irq_domain_translate,
>  	.alloc		= plic_irq_domain_alloc,
>  	.free		= irq_domain_free_irqs_top,
>  };
> @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
>  	if (!priv)
>  		return -ENOMEM;
>  
> +	if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> +		priv->of_data = RENESAS_R9A07G043_PLIC;
> +		plic_chip.name = "Renesas RZ/Five PLIC";

NAK. The irq_chip structure isn't the place for platform marketing.
This is way too long anyway (and same for the edge version), and you
even sent me a patch to make that structure const...

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

Thank you for the review.

On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sun, 26 Jun 2022 01:43:26 +0100,
> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >
> > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > edge until the previous completion message has been received and
> > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > interrupts if not acknowledged in time.
> >
> > So the workaround for edge-triggered interrupts to be handled correctly
> > and without losing is that it needs to be acknowledged first and then
> > handler must be run so that we don't miss on the next edge-triggered
> > interrupt.
> >
> > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > support to change interrupt flow based on the interrupt type. It also
> > implements irq_ack and irq_set_type callbacks.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2:
> > * Implemented IRQ flow as suggested by Marc
> >
> > RFC-->v1:
> > * Fixed review comments pointed by Geert
> > * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> > claim the interrupt by reading the register and then acknowledge it.
> > * Add a new chained handler for RZ/Five SoC.
> > ---
> >  drivers/irqchip/Kconfig           |  1 +
> >  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
> >  2 files changed, 72 insertions(+), 2 deletions(-)
>
> [...]
>
> >
> > +static int plic_irq_set_type(struct irq_data *d, unsigned int type)
> > +{
> > +     struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> > +
> > +     if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
> > +             return 0;
> > +
> > +     switch (type) {
> > +     case IRQ_TYPE_LEVEL_HIGH:
> > +             irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
> > +                                              handle_fasteoi_ack_irq,
> > +                                              "Edge");
> > +             break;
> > +
> > +     case IRQ_TYPE_EDGE_RISING:
> > +             irq_set_chip_handler_name_locked(d, &plic_chip,
> > +                                              handle_fasteoi_irq,
> > +                                              "Level");
> > +             break;
>
> Really? Have you even tested this?
>
Ouch my bad, while rebasing I did swap this up!

> > +
> > +     default:
> > +             return -EINVAL;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> >  static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
> >                             irq_hw_number_t hwirq)
> >  {
> > @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
> >       return 0;
> >  }
> >
> > +static int plic_irq_domain_translate(struct irq_domain *d,
> > +                                  struct irq_fwspec *fwspec,
> > +                                  unsigned long *hwirq,
> > +                                  unsigned int *type)
> > +{
> > +     struct plic_priv *priv = d->host_data;
> > +
> > +     if (priv->of_data == RENESAS_R9A07G043_PLIC)
> > +             return irq_domain_translate_twocell(d, fwspec, hwirq, type);
> > +
> > +     return irq_domain_translate_onecell(d, fwspec, hwirq, type);
> > +}
> > +
> >  static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> >                                unsigned int nr_irqs, void *arg)
> >  {
> > @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> >       unsigned int type;
> >       struct irq_fwspec *fwspec = arg;
> >
> > -     ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
> > +     ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
> >       if (ret)
> >               return ret;
> >
> > @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> >  }
> >
> >  static const struct irq_domain_ops plic_irqdomain_ops = {
> > -     .translate      = irq_domain_translate_onecell,
> > +     .translate      = plic_irq_domain_translate,
> >       .alloc          = plic_irq_domain_alloc,
> >       .free           = irq_domain_free_irqs_top,
> >  };
> > @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
> >       if (!priv)
> >               return -ENOMEM;
> >
> > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > +             plic_chip.name = "Renesas RZ/Five PLIC";
>
> NAK. The irq_chip structure isn't the place for platform marketing.
> This is way too long anyway (and same for the edge version), and you
> even sent me a patch to make that structure const...
>
My bad will drop this.

Cheers,
Prabhakar

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

Thank you for the review.

On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sun, 26 Jun 2022 01:43:26 +0100,
> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >
> > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > edge until the previous completion message has been received and
> > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > interrupts if not acknowledged in time.
> >
> > So the workaround for edge-triggered interrupts to be handled correctly
> > and without losing is that it needs to be acknowledged first and then
> > handler must be run so that we don't miss on the next edge-triggered
> > interrupt.
> >
> > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > support to change interrupt flow based on the interrupt type. It also
> > implements irq_ack and irq_set_type callbacks.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2:
> > * Implemented IRQ flow as suggested by Marc
> >
> > RFC-->v1:
> > * Fixed review comments pointed by Geert
> > * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> > claim the interrupt by reading the register and then acknowledge it.
> > * Add a new chained handler for RZ/Five SoC.
> > ---
> >  drivers/irqchip/Kconfig           |  1 +
> >  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
> >  2 files changed, 72 insertions(+), 2 deletions(-)
>
> [...]
>
> >
> > +static int plic_irq_set_type(struct irq_data *d, unsigned int type)
> > +{
> > +     struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> > +
> > +     if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
> > +             return 0;
> > +
> > +     switch (type) {
> > +     case IRQ_TYPE_LEVEL_HIGH:
> > +             irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
> > +                                              handle_fasteoi_ack_irq,
> > +                                              "Edge");
> > +             break;
> > +
> > +     case IRQ_TYPE_EDGE_RISING:
> > +             irq_set_chip_handler_name_locked(d, &plic_chip,
> > +                                              handle_fasteoi_irq,
> > +                                              "Level");
> > +             break;
>
> Really? Have you even tested this?
>
Ouch my bad, while rebasing I did swap this up!

> > +
> > +     default:
> > +             return -EINVAL;
> > +     }
> > +
> > +     return 0;
> > +}
> > +
> >  static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
> >                             irq_hw_number_t hwirq)
> >  {
> > @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
> >       return 0;
> >  }
> >
> > +static int plic_irq_domain_translate(struct irq_domain *d,
> > +                                  struct irq_fwspec *fwspec,
> > +                                  unsigned long *hwirq,
> > +                                  unsigned int *type)
> > +{
> > +     struct plic_priv *priv = d->host_data;
> > +
> > +     if (priv->of_data == RENESAS_R9A07G043_PLIC)
> > +             return irq_domain_translate_twocell(d, fwspec, hwirq, type);
> > +
> > +     return irq_domain_translate_onecell(d, fwspec, hwirq, type);
> > +}
> > +
> >  static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> >                                unsigned int nr_irqs, void *arg)
> >  {
> > @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> >       unsigned int type;
> >       struct irq_fwspec *fwspec = arg;
> >
> > -     ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
> > +     ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
> >       if (ret)
> >               return ret;
> >
> > @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> >  }
> >
> >  static const struct irq_domain_ops plic_irqdomain_ops = {
> > -     .translate      = irq_domain_translate_onecell,
> > +     .translate      = plic_irq_domain_translate,
> >       .alloc          = plic_irq_domain_alloc,
> >       .free           = irq_domain_free_irqs_top,
> >  };
> > @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
> >       if (!priv)
> >               return -ENOMEM;
> >
> > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > +             plic_chip.name = "Renesas RZ/Five PLIC";
>
> NAK. The irq_chip structure isn't the place for platform marketing.
> This is way too long anyway (and same for the edge version), and you
> even sent me a patch to make that structure const...
>
My bad will drop this.

Cheers,
Prabhakar

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On Sun, 26 Jun 2022 10:38:18 +0100,
"Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> 
> Hi Marc,
> 
> Thank you for the review.
> 
> On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Sun, 26 Jun 2022 01:43:26 +0100,
> > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > >
> > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > edge until the previous completion message has been received and
> > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > interrupts if not acknowledged in time.
> > >
> > > So the workaround for edge-triggered interrupts to be handled correctly
> > > and without losing is that it needs to be acknowledged first and then
> > > handler must be run so that we don't miss on the next edge-triggered
> > > interrupt.
> > >
> > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > support to change interrupt flow based on the interrupt type. It also
> > > implements irq_ack and irq_set_type callbacks.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2:
> > > * Implemented IRQ flow as suggested by Marc
> > >
> > > RFC-->v1:
> > > * Fixed review comments pointed by Geert
> > > * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> > > claim the interrupt by reading the register and then acknowledge it.
> > > * Add a new chained handler for RZ/Five SoC.
> > > ---
> > >  drivers/irqchip/Kconfig           |  1 +
> > >  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
> > >  2 files changed, 72 insertions(+), 2 deletions(-)
> >

[...]

> > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> >
> > NAK. The irq_chip structure isn't the place for platform marketing.
> > This is way too long anyway (and same for the edge version), and you
> > even sent me a patch to make that structure const...
> >
> My bad will drop this.

And why you're at it, please turn this rather random 'of_data' into
something like:

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index bb87e4c3b88e..cd1683b77caf 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -64,6 +64,10 @@ struct plic_priv {
 	struct cpumask lmask;
 	struct irq_domain *irqdomain;
 	void __iomem *regs;
+	enum {
+		VANILLA_PLIC,
+		RENESAS_R9A07G043_PLIC,
+	} flavour;
 };
 
 struct plic_handler {

to give some structure to the whole thing, because I'm pretty sure
we'll see more braindead implementations as time goes by.

It almost feels like I've written this whole patch. Oh wait...

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On Sun, 26 Jun 2022 10:38:18 +0100,
"Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> 
> Hi Marc,
> 
> Thank you for the review.
> 
> On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> >
> > On Sun, 26 Jun 2022 01:43:26 +0100,
> > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > >
> > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > edge until the previous completion message has been received and
> > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > interrupts if not acknowledged in time.
> > >
> > > So the workaround for edge-triggered interrupts to be handled correctly
> > > and without losing is that it needs to be acknowledged first and then
> > > handler must be run so that we don't miss on the next edge-triggered
> > > interrupt.
> > >
> > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > support to change interrupt flow based on the interrupt type. It also
> > > implements irq_ack and irq_set_type callbacks.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2:
> > > * Implemented IRQ flow as suggested by Marc
> > >
> > > RFC-->v1:
> > > * Fixed review comments pointed by Geert
> > > * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> > > claim the interrupt by reading the register and then acknowledge it.
> > > * Add a new chained handler for RZ/Five SoC.
> > > ---
> > >  drivers/irqchip/Kconfig           |  1 +
> > >  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
> > >  2 files changed, 72 insertions(+), 2 deletions(-)
> >

[...]

> > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> >
> > NAK. The irq_chip structure isn't the place for platform marketing.
> > This is way too long anyway (and same for the edge version), and you
> > even sent me a patch to make that structure const...
> >
> My bad will drop this.

And why you're at it, please turn this rather random 'of_data' into
something like:

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index bb87e4c3b88e..cd1683b77caf 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -64,6 +64,10 @@ struct plic_priv {
 	struct cpumask lmask;
 	struct irq_domain *irqdomain;
 	void __iomem *regs;
+	enum {
+		VANILLA_PLIC,
+		RENESAS_R9A07G043_PLIC,
+	} flavour;
 };
 
 struct plic_handler {

to give some structure to the whole thing, because I'm pretty sure
we'll see more braindead implementations as time goes by.

It almost feels like I've written this whole patch. Oh wait...

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Marc Zyngier]

On Sun, 26 Jun 2022 01:43:25 +0100,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> 
> Document Renesas RZ/Five (R9A07G043) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Fixed binding doc
> * Fixed review comments pointed by Krzysztof.
> 
> RFC->v1:
> * Fixed Review comments pointed by Geert and Rob
> ---
>  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
>  1 file changed, 41 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 27092c6a86c4..59df367d1e44 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -28,7 +28,10 @@ description:
>  
>    While the PLIC supports both edge-triggered and level-triggered interrupts,
>    interrupt handlers are oblivious to this distinction and therefore it is not
> -  specified in the PLIC device-tree binding.
> +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> +  to specify the interrupt type as the flow for EDGE interrupts is different
> +  compared to LEVEL interrupts.
>  
>    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
>    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> @@ -57,6 +60,7 @@ properties:
>            - enum:
>                - allwinner,sun20i-d1-plic
>            - const: thead,c900-plic
> +      - const: renesas,r9a07g043-plic

Since it is the NCEPLIC100 that is broken, shouldn't the compatible
string actually reflect that? I'd rather see 'andes,nceplic100' once
and for all instead of starting with Renesas, quickly followed by all
the other licensees that will inevitably integrate the same IP (which
isn't even specific to the AX45MP).

This IP also comes with all sort of added (mis-)features, which may or
may not be used in the future, and it would make sense to identify it
specifically.

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Marc Zyngier]

On Sun, 26 Jun 2022 01:43:25 +0100,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> 
> Document Renesas RZ/Five (R9A07G043) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Fixed binding doc
> * Fixed review comments pointed by Krzysztof.
> 
> RFC->v1:
> * Fixed Review comments pointed by Geert and Rob
> ---
>  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
>  1 file changed, 41 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 27092c6a86c4..59df367d1e44 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -28,7 +28,10 @@ description:
>  
>    While the PLIC supports both edge-triggered and level-triggered interrupts,
>    interrupt handlers are oblivious to this distinction and therefore it is not
> -  specified in the PLIC device-tree binding.
> +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> +  to specify the interrupt type as the flow for EDGE interrupts is different
> +  compared to LEVEL interrupts.
>  
>    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
>    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> @@ -57,6 +60,7 @@ properties:
>            - enum:
>                - allwinner,sun20i-d1-plic
>            - const: thead,c900-plic
> +      - const: renesas,r9a07g043-plic

Since it is the NCEPLIC100 that is broken, shouldn't the compatible
string actually reflect that? I'd rather see 'andes,nceplic100' once
and for all instead of starting with Renesas, quickly followed by all
the other licensees that will inevitably integrate the same IP (which
isn't even specific to the AX45MP).

This IP also comes with all sort of added (mis-)features, which may or
may not be used in the future, and it would make sense to identify it
specifically.

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Samuel Holland]

Hi Marc, Prabhakar,

On 6/25/22 7:43 PM, Lad Prabhakar wrote:
> The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> edge until the previous completion message has been received and
> NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> interrupts if not acknowledged in time.

Looking at its HDL[1], I realized the T-HEAD C9xx PLIC has the same issue. Its
pending transitions simplify to:

always @(posedge clock)
begin
  if (hreg_int_claim_kid_x)
    int_pending <= 1'b0;
  else if (
    // The input level is currently high
    int_vld &&
    // Either this is a rising edge,
    // or a level interrupt is being completed this clock cycle
    (!int_vld_ff || (!pad_plic_int_cfg_x && hreg_int_complete_kid_x)) &&
    // Either the interrupt is not currently being handled,
    // or it is being completed this clock cycle
    (!int_active || hreg_int_complete_kid_x)
  )
    int_pending <= 1'b1;
end

So an interrupt will never go pending while it is active. (And the hardware's
"level" mode does not clear the pending state when the IRQ is deasserted, but
that is a more minor issue.)

I am about to send a series implementing this fix for the C9xx PLIC as found in
the Allwinner D1, crediting you on the driver change -- hopefully that is okay
with you. I tried to make it easy for you to rebase your series on top. And I
think all of the comments should be resolved, including a couple of things
brought up below.

Regards,
Samuel

[1]:
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/plic/rtl/plic_int_kid.v

> So the workaround for edge-triggered interrupts to be handled correctly
> and without losing is that it needs to be acknowledged first and then
> handler must be run so that we don't miss on the next edge-triggered
> interrupt.
> 
> This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> support to change interrupt flow based on the interrupt type. It also
> implements irq_ack and irq_set_type callbacks.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Implemented IRQ flow as suggested by Marc
> 
> RFC-->v1:
> * Fixed review comments pointed by Geert
> * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> claim the interrupt by reading the register and then acknowledge it.
> * Add a new chained handler for RZ/Five SoC.
> ---
>  drivers/irqchip/Kconfig           |  1 +
>  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
>  2 files changed, 72 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 4ab1038b5482..0245dcabe3e9 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -530,6 +530,7 @@ config SIFIVE_PLIC
>  	bool "SiFive Platform-Level Interrupt Controller"
>  	depends on RISCV
>  	select IRQ_DOMAIN_HIERARCHY
> +	select IRQ_FASTEOI_HIERARCHY_HANDLERS
>  	help
>  	   This enables support for the PLIC chip found in SiFive (and
>  	   potentially other) RISC-V systems.  The PLIC controls devices
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index bb87e4c3b88e..9fb9f62afb6a 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -60,10 +60,13 @@
>  #define	PLIC_DISABLE_THRESHOLD		0x7
>  #define	PLIC_ENABLE_THRESHOLD		0
>  
> +#define RENESAS_R9A07G043_PLIC		1
> +
>  struct plic_priv {
>  	struct cpumask lmask;
>  	struct irq_domain *irqdomain;
>  	void __iomem *regs;
> +	u8 of_data;
>  };
>  
>  struct plic_handler {
> @@ -81,6 +84,8 @@ static int plic_parent_irq __ro_after_init;
>  static bool plic_cpuhp_setup_done __ro_after_init;
>  static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
>  
> +static int plic_irq_set_type(struct irq_data *d, unsigned int type);
> +
>  static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
>  {
>  	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
> @@ -176,16 +181,61 @@ static void plic_irq_eoi(struct irq_data *d)
>  	}
>  }
>  
> +static void renesas_rzfive_plic_edge_irq_eoi(struct irq_data *data)
> +{
> +	/* We have nothing to do here */
> +}
> +
>  static struct irq_chip plic_chip = {
>  	.name		= "SiFive PLIC",
>  	.irq_mask	= plic_irq_mask,
>  	.irq_unmask	= plic_irq_unmask,
>  	.irq_eoi	= plic_irq_eoi,
> +	.irq_set_type	= plic_irq_set_type,
> +#ifdef CONFIG_SMP
> +	.irq_set_affinity = plic_set_affinity,
> +#endif
> +};
> +
> +static struct irq_chip renesas_rzfive_edge_plic_chip = {
> +	.name		= "Renesas RZ/Five PLIC",
> +	.irq_mask	= plic_irq_mask,
> +	.irq_unmask	= plic_irq_unmask,
> +	.irq_ack	= plic_irq_eoi,
> +	.irq_eoi	= renesas_rzfive_plic_edge_irq_eoi,
> +	.irq_set_type	= plic_irq_set_type,
>  #ifdef CONFIG_SMP
>  	.irq_set_affinity = plic_set_affinity,
>  #endif
>  };
>  
> +static int plic_irq_set_type(struct irq_data *d, unsigned int type)
> +{
> +	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> +
> +	if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
> +		return 0;
> +
> +	switch (type) {
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
> +						 handle_fasteoi_ack_irq,
> +						 "Edge");

This has a problem: for handle_fasteoi_ack_irq, in the !irq_may_run path, only
.irq_eoi gets called, so the interrupt never gets "completed" (EOI'd).

It looks to me like handle_edge_irq is the right flow to use here, since it
unconditionally calls .irq_ack (either on its own or as part of of mask_ack_irq).

> +		break;
> +
> +	case IRQ_TYPE_EDGE_RISING:
> +		irq_set_chip_handler_name_locked(d, &plic_chip,
> +						 handle_fasteoi_irq,
> +						 "Level");
> +		break;
> +
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  			      irq_hw_number_t hwirq)
>  {
> @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  	return 0;
>  }
>  
> +static int plic_irq_domain_translate(struct irq_domain *d,
> +				     struct irq_fwspec *fwspec,
> +				     unsigned long *hwirq,
> +				     unsigned int *type)
> +{
> +	struct plic_priv *priv = d->host_data;
> +
> +	if (priv->of_data == RENESAS_R9A07G043_PLIC)
> +		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
> +
> +	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
> +}
> +
>  static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  				 unsigned int nr_irqs, void *arg)
>  {
> @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  	unsigned int type;
>  	struct irq_fwspec *fwspec = arg;
>  
> -	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
> +	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
>  	if (ret)
>  		return ret;
>  
> @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  }
>  
>  static const struct irq_domain_ops plic_irqdomain_ops = {
> -	.translate	= irq_domain_translate_onecell,
> +	.translate	= plic_irq_domain_translate,
>  	.alloc		= plic_irq_domain_alloc,
>  	.free		= irq_domain_free_irqs_top,
>  };
> @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
>  	if (!priv)
>  		return -ENOMEM;
>  
> +	if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> +		priv->of_data = RENESAS_R9A07G043_PLIC;

This really should be a feature flag, passed in to plic_init, so it can be
enabled for whichever variants need it.

> +		plic_chip.name = "Renesas RZ/Five PLIC";
> +	}
> +
>  	priv->regs = of_iomap(node, 0);
>  	if (WARN_ON(!priv->regs)) {
>  		error = -EIO;
> @@ -411,5 +479,6 @@ static int __init plic_init(struct device_node *node,
>  }
>  
>  IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
> +IRQCHIP_DECLARE(renesas_r9a07g043_plic, "renesas,r9a07g043-plic", plic_init);
>  IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
>  IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
> 

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Samuel Holland]

Hi Marc, Prabhakar,

On 6/25/22 7:43 PM, Lad Prabhakar wrote:
> The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> edge until the previous completion message has been received and
> NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> interrupts if not acknowledged in time.

Looking at its HDL[1], I realized the T-HEAD C9xx PLIC has the same issue. Its
pending transitions simplify to:

always @(posedge clock)
begin
  if (hreg_int_claim_kid_x)
    int_pending <= 1'b0;
  else if (
    // The input level is currently high
    int_vld &&
    // Either this is a rising edge,
    // or a level interrupt is being completed this clock cycle
    (!int_vld_ff || (!pad_plic_int_cfg_x && hreg_int_complete_kid_x)) &&
    // Either the interrupt is not currently being handled,
    // or it is being completed this clock cycle
    (!int_active || hreg_int_complete_kid_x)
  )
    int_pending <= 1'b1;
end

So an interrupt will never go pending while it is active. (And the hardware's
"level" mode does not clear the pending state when the IRQ is deasserted, but
that is a more minor issue.)

I am about to send a series implementing this fix for the C9xx PLIC as found in
the Allwinner D1, crediting you on the driver change -- hopefully that is okay
with you. I tried to make it easy for you to rebase your series on top. And I
think all of the comments should be resolved, including a couple of things
brought up below.

Regards,
Samuel

[1]:
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/plic/rtl/plic_int_kid.v

> So the workaround for edge-triggered interrupts to be handled correctly
> and without losing is that it needs to be acknowledged first and then
> handler must be run so that we don't miss on the next edge-triggered
> interrupt.
> 
> This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> support to change interrupt flow based on the interrupt type. It also
> implements irq_ack and irq_set_type callbacks.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2:
> * Implemented IRQ flow as suggested by Marc
> 
> RFC-->v1:
> * Fixed review comments pointed by Geert
> * Dropped handle_fasteoi_ack_irq support as for the PLIC we need to
> claim the interrupt by reading the register and then acknowledge it.
> * Add a new chained handler for RZ/Five SoC.
> ---
>  drivers/irqchip/Kconfig           |  1 +
>  drivers/irqchip/irq-sifive-plic.c | 73 ++++++++++++++++++++++++++++++-
>  2 files changed, 72 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index 4ab1038b5482..0245dcabe3e9 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -530,6 +530,7 @@ config SIFIVE_PLIC
>  	bool "SiFive Platform-Level Interrupt Controller"
>  	depends on RISCV
>  	select IRQ_DOMAIN_HIERARCHY
> +	select IRQ_FASTEOI_HIERARCHY_HANDLERS
>  	help
>  	   This enables support for the PLIC chip found in SiFive (and
>  	   potentially other) RISC-V systems.  The PLIC controls devices
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index bb87e4c3b88e..9fb9f62afb6a 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -60,10 +60,13 @@
>  #define	PLIC_DISABLE_THRESHOLD		0x7
>  #define	PLIC_ENABLE_THRESHOLD		0
>  
> +#define RENESAS_R9A07G043_PLIC		1
> +
>  struct plic_priv {
>  	struct cpumask lmask;
>  	struct irq_domain *irqdomain;
>  	void __iomem *regs;
> +	u8 of_data;
>  };
>  
>  struct plic_handler {
> @@ -81,6 +84,8 @@ static int plic_parent_irq __ro_after_init;
>  static bool plic_cpuhp_setup_done __ro_after_init;
>  static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
>  
> +static int plic_irq_set_type(struct irq_data *d, unsigned int type);
> +
>  static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
>  {
>  	u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
> @@ -176,16 +181,61 @@ static void plic_irq_eoi(struct irq_data *d)
>  	}
>  }
>  
> +static void renesas_rzfive_plic_edge_irq_eoi(struct irq_data *data)
> +{
> +	/* We have nothing to do here */
> +}
> +
>  static struct irq_chip plic_chip = {
>  	.name		= "SiFive PLIC",
>  	.irq_mask	= plic_irq_mask,
>  	.irq_unmask	= plic_irq_unmask,
>  	.irq_eoi	= plic_irq_eoi,
> +	.irq_set_type	= plic_irq_set_type,
> +#ifdef CONFIG_SMP
> +	.irq_set_affinity = plic_set_affinity,
> +#endif
> +};
> +
> +static struct irq_chip renesas_rzfive_edge_plic_chip = {
> +	.name		= "Renesas RZ/Five PLIC",
> +	.irq_mask	= plic_irq_mask,
> +	.irq_unmask	= plic_irq_unmask,
> +	.irq_ack	= plic_irq_eoi,
> +	.irq_eoi	= renesas_rzfive_plic_edge_irq_eoi,
> +	.irq_set_type	= plic_irq_set_type,
>  #ifdef CONFIG_SMP
>  	.irq_set_affinity = plic_set_affinity,
>  #endif
>  };
>  
> +static int plic_irq_set_type(struct irq_data *d, unsigned int type)
> +{
> +	struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
> +
> +	if (handler->priv->of_data != RENESAS_R9A07G043_PLIC)
> +		return 0;
> +
> +	switch (type) {
> +	case IRQ_TYPE_LEVEL_HIGH:
> +		irq_set_chip_handler_name_locked(d, &renesas_rzfive_edge_plic_chip,
> +						 handle_fasteoi_ack_irq,
> +						 "Edge");

This has a problem: for handle_fasteoi_ack_irq, in the !irq_may_run path, only
.irq_eoi gets called, so the interrupt never gets "completed" (EOI'd).

It looks to me like handle_edge_irq is the right flow to use here, since it
unconditionally calls .irq_ack (either on its own or as part of of mask_ack_irq).

> +		break;
> +
> +	case IRQ_TYPE_EDGE_RISING:
> +		irq_set_chip_handler_name_locked(d, &plic_chip,
> +						 handle_fasteoi_irq,
> +						 "Level");
> +		break;
> +
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
>  static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  			      irq_hw_number_t hwirq)
>  {
> @@ -198,6 +248,19 @@ static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
>  	return 0;
>  }
>  
> +static int plic_irq_domain_translate(struct irq_domain *d,
> +				     struct irq_fwspec *fwspec,
> +				     unsigned long *hwirq,
> +				     unsigned int *type)
> +{
> +	struct plic_priv *priv = d->host_data;
> +
> +	if (priv->of_data == RENESAS_R9A07G043_PLIC)
> +		return irq_domain_translate_twocell(d, fwspec, hwirq, type);
> +
> +	return irq_domain_translate_onecell(d, fwspec, hwirq, type);
> +}
> +
>  static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  				 unsigned int nr_irqs, void *arg)
>  {
> @@ -206,7 +269,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  	unsigned int type;
>  	struct irq_fwspec *fwspec = arg;
>  
> -	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
> +	ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
>  	if (ret)
>  		return ret;
>  
> @@ -220,7 +283,7 @@ static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
>  }
>  
>  static const struct irq_domain_ops plic_irqdomain_ops = {
> -	.translate	= irq_domain_translate_onecell,
> +	.translate	= plic_irq_domain_translate,
>  	.alloc		= plic_irq_domain_alloc,
>  	.free		= irq_domain_free_irqs_top,
>  };
> @@ -293,6 +356,11 @@ static int __init plic_init(struct device_node *node,
>  	if (!priv)
>  		return -ENOMEM;
>  
> +	if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> +		priv->of_data = RENESAS_R9A07G043_PLIC;

This really should be a feature flag, passed in to plic_init, so it can be
enabled for whichever variants need it.

> +		plic_chip.name = "Renesas RZ/Five PLIC";
> +	}
> +
>  	priv->regs = of_iomap(node, 0);
>  	if (WARN_ON(!priv->regs)) {
>  		error = -EIO;
> @@ -411,5 +479,6 @@ static int __init plic_init(struct device_node *node,
>  }
>  
>  IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
> +IRQCHIP_DECLARE(renesas_r9a07g043_plic, "renesas,r9a07g043-plic", plic_init);
>  IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
>  IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */
> 


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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Marc,

On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> On Sun, 26 Jun 2022 10:38:18 +0100,
> "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > edge until the previous completion message has been received and
> > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > interrupts if not acknowledged in time.
> > > >
> > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > and without losing is that it needs to be acknowledged first and then
> > > > handler must be run so that we don't miss on the next edge-triggered
> > > > interrupt.
> > > >
> > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > support to change interrupt flow based on the interrupt type. It also
> > > > implements irq_ack and irq_set_type callbacks.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > >
> > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > This is way too long anyway (and same for the edge version), and you
> > > even sent me a patch to make that structure const...
> > >
> > My bad will drop this.
>
> And why you're at it, please turn this rather random 'of_data' into
> something like:
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index bb87e4c3b88e..cd1683b77caf 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -64,6 +64,10 @@ struct plic_priv {
>         struct cpumask lmask;
>         struct irq_domain *irqdomain;
>         void __iomem *regs;
> +       enum {
> +               VANILLA_PLIC,
> +               RENESAS_R9A07G043_PLIC,
> +       } flavour;
>  };
>
>  struct plic_handler {
>
> to give some structure to the whole thing, because I'm pretty sure
> we'll see more braindead implementations as time goes by.

What about using a feature flag (e.g. had_edge_irqs) instead?

> It almost feels like I've written this whole patch. Oh wait...

> Without deviation from the norm, progress is not possible.

How applicable ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Marc,

On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> On Sun, 26 Jun 2022 10:38:18 +0100,
> "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > edge until the previous completion message has been received and
> > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > interrupts if not acknowledged in time.
> > > >
> > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > and without losing is that it needs to be acknowledged first and then
> > > > handler must be run so that we don't miss on the next edge-triggered
> > > > interrupt.
> > > >
> > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > support to change interrupt flow based on the interrupt type. It also
> > > > implements irq_ack and irq_set_type callbacks.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > >
> > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > This is way too long anyway (and same for the edge version), and you
> > > even sent me a patch to make that structure const...
> > >
> > My bad will drop this.
>
> And why you're at it, please turn this rather random 'of_data' into
> something like:
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index bb87e4c3b88e..cd1683b77caf 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -64,6 +64,10 @@ struct plic_priv {
>         struct cpumask lmask;
>         struct irq_domain *irqdomain;
>         void __iomem *regs;
> +       enum {
> +               VANILLA_PLIC,
> +               RENESAS_R9A07G043_PLIC,
> +       } flavour;
>  };
>
>  struct plic_handler {
>
> to give some structure to the whole thing, because I'm pretty sure
> we'll see more braindead implementations as time goes by.

What about using a feature flag (e.g. had_edge_irqs) instead?

> It almost feels like I've written this whole patch. Oh wait...

> Without deviation from the norm, progress is not possible.

How applicable ;-)

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On Mon, 27 Jun 2022 09:53:13 +0100,
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> Hi Marc,
> 
> On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> > On Sun, 26 Jun 2022 10:38:18 +0100,
> > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > > edge until the previous completion message has been received and
> > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > > interrupts if not acknowledged in time.
> > > > >
> > > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > > and without losing is that it needs to be acknowledged first and then
> > > > > handler must be run so that we don't miss on the next edge-triggered
> > > > > interrupt.
> > > > >
> > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > > support to change interrupt flow based on the interrupt type. It also
> > > > > implements irq_ack and irq_set_type callbacks.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > > >
> > > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > > This is way too long anyway (and same for the edge version), and you
> > > > even sent me a patch to make that structure const...
> > > >
> > > My bad will drop this.
> >
> > And why you're at it, please turn this rather random 'of_data' into
> > something like:
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index bb87e4c3b88e..cd1683b77caf 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -64,6 +64,10 @@ struct plic_priv {
> >         struct cpumask lmask;
> >         struct irq_domain *irqdomain;
> >         void __iomem *regs;
> > +       enum {
> > +               VANILLA_PLIC,
> > +               RENESAS_R9A07G043_PLIC,
> > +       } flavour;
> >  };
> >
> >  struct plic_handler {
> >
> > to give some structure to the whole thing, because I'm pretty sure
> > we'll see more braindead implementations as time goes by.
> 
> What about using a feature flag (e.g. had_edge_irqs) instead?

Sure. Then make this an unsigned long, and have a set of quirk bits,
because I expect this to grow quickly.

>
> > It almost feels like I've written this whole patch. Oh wait...
> 
> > Without deviation from the norm, progress is not possible.
> 
> How applicable ;-)

I'm not sure there is any sign of progress here, and evolution
through random mutation has a pretty massive failure rate.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On Mon, 27 Jun 2022 09:53:13 +0100,
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> Hi Marc,
> 
> On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> > On Sun, 26 Jun 2022 10:38:18 +0100,
> > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > > edge until the previous completion message has been received and
> > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > > interrupts if not acknowledged in time.
> > > > >
> > > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > > and without losing is that it needs to be acknowledged first and then
> > > > > handler must be run so that we don't miss on the next edge-triggered
> > > > > interrupt.
> > > > >
> > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > > support to change interrupt flow based on the interrupt type. It also
> > > > > implements irq_ack and irq_set_type callbacks.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > > >
> > > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > > This is way too long anyway (and same for the edge version), and you
> > > > even sent me a patch to make that structure const...
> > > >
> > > My bad will drop this.
> >
> > And why you're at it, please turn this rather random 'of_data' into
> > something like:
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index bb87e4c3b88e..cd1683b77caf 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -64,6 +64,10 @@ struct plic_priv {
> >         struct cpumask lmask;
> >         struct irq_domain *irqdomain;
> >         void __iomem *regs;
> > +       enum {
> > +               VANILLA_PLIC,
> > +               RENESAS_R9A07G043_PLIC,
> > +       } flavour;
> >  };
> >
> >  struct plic_handler {
> >
> > to give some structure to the whole thing, because I'm pretty sure
> > we'll see more braindead implementations as time goes by.
> 
> What about using a feature flag (e.g. had_edge_irqs) instead?

Sure. Then make this an unsigned long, and have a set of quirk bits,
because I expect this to grow quickly.

>
> > It almost feels like I've written this whole patch. Oh wait...
> 
> > Without deviation from the norm, progress is not possible.
> 
> How applicable ;-)

I'm not sure there is any sign of progress here, and evolution
through random mutation has a pretty massive failure rate.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

Thank you for the review.

On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sun, 26 Jun 2022 01:43:25 +0100,
> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >
> > Document Renesas RZ/Five (R9A07G043) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2:
> > * Fixed binding doc
> > * Fixed review comments pointed by Krzysztof.
> >
> > RFC->v1:
> > * Fixed Review comments pointed by Geert and Rob
> > ---
> >  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
> >  1 file changed, 41 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index 27092c6a86c4..59df367d1e44 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -28,7 +28,10 @@ description:
> >
> >    While the PLIC supports both edge-triggered and level-triggered interrupts,
> >    interrupt handlers are oblivious to this distinction and therefore it is not
> > -  specified in the PLIC device-tree binding.
> > +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> > +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> > +  to specify the interrupt type as the flow for EDGE interrupts is different
> > +  compared to LEVEL interrupts.
> >
> >    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> >    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> > @@ -57,6 +60,7 @@ properties:
> >            - enum:
> >                - allwinner,sun20i-d1-plic
> >            - const: thead,c900-plic
> > +      - const: renesas,r9a07g043-plic
>
> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
> string actually reflect that? I'd rather see 'andes,nceplic100' once
> and for all instead of starting with Renesas, quickly followed by all
> the other licensees that will inevitably integrate the same IP (which
> isn't even specific to the AX45MP).
>
> This IP also comes with all sort of added (mis-)features, which may or
> may not be used in the future, and it would make sense to identify it
> specifically.
>
Agreed, I'll update it as above.

Cheers,
Prabhakar

Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

Thank you for the review.

On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On Sun, 26 Jun 2022 01:43:25 +0100,
> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >
> > Document Renesas RZ/Five (R9A07G043) SoC.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2:
> > * Fixed binding doc
> > * Fixed review comments pointed by Krzysztof.
> >
> > RFC->v1:
> > * Fixed Review comments pointed by Geert and Rob
> > ---
> >  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
> >  1 file changed, 41 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index 27092c6a86c4..59df367d1e44 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -28,7 +28,10 @@ description:
> >
> >    While the PLIC supports both edge-triggered and level-triggered interrupts,
> >    interrupt handlers are oblivious to this distinction and therefore it is not
> > -  specified in the PLIC device-tree binding.
> > +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> > +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> > +  to specify the interrupt type as the flow for EDGE interrupts is different
> > +  compared to LEVEL interrupts.
> >
> >    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> >    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> > @@ -57,6 +60,7 @@ properties:
> >            - enum:
> >                - allwinner,sun20i-d1-plic
> >            - const: thead,c900-plic
> > +      - const: renesas,r9a07g043-plic
>
> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
> string actually reflect that? I'd rather see 'andes,nceplic100' once
> and for all instead of starting with Renesas, quickly followed by all
> the other licensees that will inevitably integrate the same IP (which
> isn't even specific to the AX45MP).
>
> This IP also comes with all sort of added (mis-)features, which may or
> may not be used in the future, and it would make sense to identify it
> specifically.
>
Agreed, I'll update it as above.

Cheers,
Prabhakar

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Geert,

On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Marc,
>
> On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> > On Sun, 26 Jun 2022 10:38:18 +0100,
> > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > > edge until the previous completion message has been received and
> > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > > interrupts if not acknowledged in time.
> > > > >
> > > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > > and without losing is that it needs to be acknowledged first and then
> > > > > handler must be run so that we don't miss on the next edge-triggered
> > > > > interrupt.
> > > > >
> > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > > support to change interrupt flow based on the interrupt type. It also
> > > > > implements irq_ack and irq_set_type callbacks.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > > >
> > > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > > This is way too long anyway (and same for the edge version), and you
> > > > even sent me a patch to make that structure const...
> > > >
> > > My bad will drop this.
> >
> > And why you're at it, please turn this rather random 'of_data' into
> > something like:
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index bb87e4c3b88e..cd1683b77caf 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -64,6 +64,10 @@ struct plic_priv {
> >         struct cpumask lmask;
> >         struct irq_domain *irqdomain;
> >         void __iomem *regs;
> > +       enum {
> > +               VANILLA_PLIC,
> > +               RENESAS_R9A07G043_PLIC,
> > +       } flavour;
> >  };
> >
> >  struct plic_handler {
> >
> > to give some structure to the whole thing, because I'm pretty sure
> > we'll see more braindead implementations as time goes by.
>
> What about using a feature flag (e.g. had_edge_irqs) instead?
>

diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c
index 9f16833dcb41..247c3c98b655 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -60,13 +60,13 @@
 #define        PLIC_DISABLE_THRESHOLD          0x7
 #define        PLIC_ENABLE_THRESHOLD           0

+#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)

 struct plic_priv {
        struct cpumask lmask;
        struct irq_domain *irqdomain;
        void __iomem *regs;
+       u32 plic_quirks;
 };

What about something like above?

Cheers,
Prabhakar

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Geert,

On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Marc,
>
> On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> > On Sun, 26 Jun 2022 10:38:18 +0100,
> > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > > edge until the previous completion message has been received and
> > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > > interrupts if not acknowledged in time.
> > > > >
> > > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > > and without losing is that it needs to be acknowledged first and then
> > > > > handler must be run so that we don't miss on the next edge-triggered
> > > > > interrupt.
> > > > >
> > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > > support to change interrupt flow based on the interrupt type. It also
> > > > > implements irq_ack and irq_set_type callbacks.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > > >
> > > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > > This is way too long anyway (and same for the edge version), and you
> > > > even sent me a patch to make that structure const...
> > > >
> > > My bad will drop this.
> >
> > And why you're at it, please turn this rather random 'of_data' into
> > something like:
> >
> > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > index bb87e4c3b88e..cd1683b77caf 100644
> > --- a/drivers/irqchip/irq-sifive-plic.c
> > +++ b/drivers/irqchip/irq-sifive-plic.c
> > @@ -64,6 +64,10 @@ struct plic_priv {
> >         struct cpumask lmask;
> >         struct irq_domain *irqdomain;
> >         void __iomem *regs;
> > +       enum {
> > +               VANILLA_PLIC,
> > +               RENESAS_R9A07G043_PLIC,
> > +       } flavour;
> >  };
> >
> >  struct plic_handler {
> >
> > to give some structure to the whole thing, because I'm pretty sure
> > we'll see more braindead implementations as time goes by.
>
> What about using a feature flag (e.g. had_edge_irqs) instead?
>

diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c
index 9f16833dcb41..247c3c98b655 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -60,13 +60,13 @@
 #define        PLIC_DISABLE_THRESHOLD          0x7
 #define        PLIC_ENABLE_THRESHOLD           0

+#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)

 struct plic_priv {
        struct cpumask lmask;
        struct irq_domain *irqdomain;
        void __iomem *regs;
+       u32 plic_quirks;
 };

What about something like above?

Cheers,
Prabhakar

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, Jun 27, 2022 at 3:06 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> > > On Sun, 26 Jun 2022 10:38:18 +0100,
> > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > > > edge until the previous completion message has been received and
> > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > > > interrupts if not acknowledged in time.
> > > > > >
> > > > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > > > and without losing is that it needs to be acknowledged first and then
> > > > > > handler must be run so that we don't miss on the next edge-triggered
> > > > > > interrupt.
> > > > > >
> > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > > > support to change interrupt flow based on the interrupt type. It also
> > > > > > implements irq_ack and irq_set_type callbacks.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > > > >
> > > > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > > > This is way too long anyway (and same for the edge version), and you
> > > > > even sent me a patch to make that structure const...
> > > > >
> > > > My bad will drop this.
> > >
> > > And why you're at it, please turn this rather random 'of_data' into
> > > something like:
> > >
> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > > index bb87e4c3b88e..cd1683b77caf 100644
> > > --- a/drivers/irqchip/irq-sifive-plic.c
> > > +++ b/drivers/irqchip/irq-sifive-plic.c
> > > @@ -64,6 +64,10 @@ struct plic_priv {
> > >         struct cpumask lmask;
> > >         struct irq_domain *irqdomain;
> > >         void __iomem *regs;
> > > +       enum {
> > > +               VANILLA_PLIC,
> > > +               RENESAS_R9A07G043_PLIC,
> > > +       } flavour;
> > >  };
> > >
> > >  struct plic_handler {
> > >
> > > to give some structure to the whole thing, because I'm pretty sure
> > > we'll see more braindead implementations as time goes by.
> >
> > What about using a feature flag (e.g. had_edge_irqs) instead?
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c
> b/drivers/irqchip/irq-sifive-plic.c
> index 9f16833dcb41..247c3c98b655 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -60,13 +60,13 @@
>  #define        PLIC_DISABLE_THRESHOLD          0x7
>  #define        PLIC_ENABLE_THRESHOLD           0
>
> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>
>  struct plic_priv {
>         struct cpumask lmask;
>         struct irq_domain *irqdomain;
>         void __iomem *regs;
> +       u32 plic_quirks;
>  };
>
> What about something like above?

LGTM.

Marc suggested to make this unsigned long, but TBH, that won't make
much of a difference.  PLICs are present on RV32 SoCs, too, so you
cannot rely on having more than 32 bits anyway.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, Jun 27, 2022 at 3:06 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> > > On Sun, 26 Jun 2022 10:38:18 +0100,
> > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> > > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> > > > > > edge until the previous completion message has been received and
> > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> > > > > > interrupts if not acknowledged in time.
> > > > > >
> > > > > > So the workaround for edge-triggered interrupts to be handled correctly
> > > > > > and without losing is that it needs to be acknowledged first and then
> > > > > > handler must be run so that we don't miss on the next edge-triggered
> > > > > > interrupt.
> > > > > >
> > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> > > > > > support to change interrupt flow based on the interrupt type. It also
> > > > > > implements irq_ack and irq_set_type callbacks.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> > > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> > > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> > > > >
> > > > > NAK. The irq_chip structure isn't the place for platform marketing.
> > > > > This is way too long anyway (and same for the edge version), and you
> > > > > even sent me a patch to make that structure const...
> > > > >
> > > > My bad will drop this.
> > >
> > > And why you're at it, please turn this rather random 'of_data' into
> > > something like:
> > >
> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> > > index bb87e4c3b88e..cd1683b77caf 100644
> > > --- a/drivers/irqchip/irq-sifive-plic.c
> > > +++ b/drivers/irqchip/irq-sifive-plic.c
> > > @@ -64,6 +64,10 @@ struct plic_priv {
> > >         struct cpumask lmask;
> > >         struct irq_domain *irqdomain;
> > >         void __iomem *regs;
> > > +       enum {
> > > +               VANILLA_PLIC,
> > > +               RENESAS_R9A07G043_PLIC,
> > > +       } flavour;
> > >  };
> > >
> > >  struct plic_handler {
> > >
> > > to give some structure to the whole thing, because I'm pretty sure
> > > we'll see more braindead implementations as time goes by.
> >
> > What about using a feature flag (e.g. had_edge_irqs) instead?
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c
> b/drivers/irqchip/irq-sifive-plic.c
> index 9f16833dcb41..247c3c98b655 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -60,13 +60,13 @@
>  #define        PLIC_DISABLE_THRESHOLD          0x7
>  #define        PLIC_ENABLE_THRESHOLD           0
>
> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>
>  struct plic_priv {
>         struct cpumask lmask;
>         struct irq_domain *irqdomain;
>         void __iomem *regs;
> +       u32 plic_quirks;
>  };
>
> What about something like above?

LGTM.

Marc suggested to make this unsigned long, but TBH, that won't make
much of a difference.  PLICs are present on RV32 SoCs, too, so you
cannot rely on having more than 32 bits anyway.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On 2022-06-27 14:12, Geert Uytterhoeven wrote:
> Hi Prabhakar,
> 
> On Mon, Jun 27, 2022 at 3:06 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
>> On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven 
>> <geert@linux-m68k.org> wrote:
>> > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
>> > > On Sun, 26 Jun 2022 10:38:18 +0100,
>> > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
>> > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
>> > > > > On Sun, 26 Jun 2022 01:43:26 +0100,
>> > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>> > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
>> > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
>> > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
>> > > > > > edge until the previous completion message has been received and
>> > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
>> > > > > > interrupts if not acknowledged in time.
>> > > > > >
>> > > > > > So the workaround for edge-triggered interrupts to be handled correctly
>> > > > > > and without losing is that it needs to be acknowledged first and then
>> > > > > > handler must be run so that we don't miss on the next edge-triggered
>> > > > > > interrupt.
>> > > > > >
>> > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
>> > > > > > support to change interrupt flow based on the interrupt type. It also
>> > > > > > implements irq_ack and irq_set_type callbacks.
>> > > > > >
>> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> >
>> > > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
>> > > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
>> > > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
>> > > > >
>> > > > > NAK. The irq_chip structure isn't the place for platform marketing.
>> > > > > This is way too long anyway (and same for the edge version), and you
>> > > > > even sent me a patch to make that structure const...
>> > > > >
>> > > > My bad will drop this.
>> > >
>> > > And why you're at it, please turn this rather random 'of_data' into
>> > > something like:
>> > >
>> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
>> > > index bb87e4c3b88e..cd1683b77caf 100644
>> > > --- a/drivers/irqchip/irq-sifive-plic.c
>> > > +++ b/drivers/irqchip/irq-sifive-plic.c
>> > > @@ -64,6 +64,10 @@ struct plic_priv {
>> > >         struct cpumask lmask;
>> > >         struct irq_domain *irqdomain;
>> > >         void __iomem *regs;
>> > > +       enum {
>> > > +               VANILLA_PLIC,
>> > > +               RENESAS_R9A07G043_PLIC,
>> > > +       } flavour;
>> > >  };
>> > >
>> > >  struct plic_handler {
>> > >
>> > > to give some structure to the whole thing, because I'm pretty sure
>> > > we'll see more braindead implementations as time goes by.
>> >
>> > What about using a feature flag (e.g. had_edge_irqs) instead?
>> 
>> diff --git a/drivers/irqchip/irq-sifive-plic.c
>> b/drivers/irqchip/irq-sifive-plic.c
>> index 9f16833dcb41..247c3c98b655 100644
>> --- a/drivers/irqchip/irq-sifive-plic.c
>> +++ b/drivers/irqchip/irq-sifive-plic.c
>> @@ -60,13 +60,13 @@
>>  #define        PLIC_DISABLE_THRESHOLD          0x7
>>  #define        PLIC_ENABLE_THRESHOLD           0
>> 
>> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>> 
>>  struct plic_priv {
>>         struct cpumask lmask;
>>         struct irq_domain *irqdomain;
>>         void __iomem *regs;
>> +       u32 plic_quirks;
>>  };
>> 
>> What about something like above?
> 
> LGTM.
> 
> Marc suggested to make this unsigned long, but TBH, that won't make
> much of a difference.  PLICs are present on RV32 SoCs, too, so you
> cannot rely on having more than 32 bits anyway.

But it will make a difference on a 64bit platform, as we want to
use test_bit() and co to check for features.

         M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On 2022-06-27 14:12, Geert Uytterhoeven wrote:
> Hi Prabhakar,
> 
> On Mon, Jun 27, 2022 at 3:06 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
>> On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven 
>> <geert@linux-m68k.org> wrote:
>> > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
>> > > On Sun, 26 Jun 2022 10:38:18 +0100,
>> > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
>> > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
>> > > > > On Sun, 26 Jun 2022 01:43:26 +0100,
>> > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>> > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
>> > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
>> > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
>> > > > > > edge until the previous completion message has been received and
>> > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
>> > > > > > interrupts if not acknowledged in time.
>> > > > > >
>> > > > > > So the workaround for edge-triggered interrupts to be handled correctly
>> > > > > > and without losing is that it needs to be acknowledged first and then
>> > > > > > handler must be run so that we don't miss on the next edge-triggered
>> > > > > > interrupt.
>> > > > > >
>> > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
>> > > > > > support to change interrupt flow based on the interrupt type. It also
>> > > > > > implements irq_ack and irq_set_type callbacks.
>> > > > > >
>> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> >
>> > > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
>> > > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
>> > > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
>> > > > >
>> > > > > NAK. The irq_chip structure isn't the place for platform marketing.
>> > > > > This is way too long anyway (and same for the edge version), and you
>> > > > > even sent me a patch to make that structure const...
>> > > > >
>> > > > My bad will drop this.
>> > >
>> > > And why you're at it, please turn this rather random 'of_data' into
>> > > something like:
>> > >
>> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
>> > > index bb87e4c3b88e..cd1683b77caf 100644
>> > > --- a/drivers/irqchip/irq-sifive-plic.c
>> > > +++ b/drivers/irqchip/irq-sifive-plic.c
>> > > @@ -64,6 +64,10 @@ struct plic_priv {
>> > >         struct cpumask lmask;
>> > >         struct irq_domain *irqdomain;
>> > >         void __iomem *regs;
>> > > +       enum {
>> > > +               VANILLA_PLIC,
>> > > +               RENESAS_R9A07G043_PLIC,
>> > > +       } flavour;
>> > >  };
>> > >
>> > >  struct plic_handler {
>> > >
>> > > to give some structure to the whole thing, because I'm pretty sure
>> > > we'll see more braindead implementations as time goes by.
>> >
>> > What about using a feature flag (e.g. had_edge_irqs) instead?
>> 
>> diff --git a/drivers/irqchip/irq-sifive-plic.c
>> b/drivers/irqchip/irq-sifive-plic.c
>> index 9f16833dcb41..247c3c98b655 100644
>> --- a/drivers/irqchip/irq-sifive-plic.c
>> +++ b/drivers/irqchip/irq-sifive-plic.c
>> @@ -60,13 +60,13 @@
>>  #define        PLIC_DISABLE_THRESHOLD          0x7
>>  #define        PLIC_ENABLE_THRESHOLD           0
>> 
>> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>> 
>>  struct plic_priv {
>>         struct cpumask lmask;
>>         struct irq_domain *irqdomain;
>>         void __iomem *regs;
>> +       u32 plic_quirks;
>>  };
>> 
>> What about something like above?
> 
> LGTM.
> 
> Marc suggested to make this unsigned long, but TBH, that won't make
> much of a difference.  PLICs are present on RV32 SoCs, too, so you
> cannot rely on having more than 32 bits anyway.

But it will make a difference on a 64bit platform, as we want to
use test_bit() and co to check for features.

         M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

On Mon, Jun 27, 2022 at 2:53 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2022-06-27 14:12, Geert Uytterhoeven wrote:
> > Hi Prabhakar,
> >
> > On Mon, Jun 27, 2022 at 3:06 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> >> On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven
> >> <geert@linux-m68k.org> wrote:
> >> > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> >> > > On Sun, 26 Jun 2022 10:38:18 +0100,
> >> > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> >> > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> >> > > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> >> > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >> > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> >> > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> >> > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> >> > > > > > edge until the previous completion message has been received and
> >> > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> >> > > > > > interrupts if not acknowledged in time.
> >> > > > > >
> >> > > > > > So the workaround for edge-triggered interrupts to be handled correctly
> >> > > > > > and without losing is that it needs to be acknowledged first and then
> >> > > > > > handler must be run so that we don't miss on the next edge-triggered
> >> > > > > > interrupt.
> >> > > > > >
> >> > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> >> > > > > > support to change interrupt flow based on the interrupt type. It also
> >> > > > > > implements irq_ack and irq_set_type callbacks.
> >> > > > > >
> >> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >> >
> >> > > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> >> > > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> >> > > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> >> > > > >
> >> > > > > NAK. The irq_chip structure isn't the place for platform marketing.
> >> > > > > This is way too long anyway (and same for the edge version), and you
> >> > > > > even sent me a patch to make that structure const...
> >> > > > >
> >> > > > My bad will drop this.
> >> > >
> >> > > And why you're at it, please turn this rather random 'of_data' into
> >> > > something like:
> >> > >
> >> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> >> > > index bb87e4c3b88e..cd1683b77caf 100644
> >> > > --- a/drivers/irqchip/irq-sifive-plic.c
> >> > > +++ b/drivers/irqchip/irq-sifive-plic.c
> >> > > @@ -64,6 +64,10 @@ struct plic_priv {
> >> > >         struct cpumask lmask;
> >> > >         struct irq_domain *irqdomain;
> >> > >         void __iomem *regs;
> >> > > +       enum {
> >> > > +               VANILLA_PLIC,
> >> > > +               RENESAS_R9A07G043_PLIC,
> >> > > +       } flavour;
> >> > >  };
> >> > >
> >> > >  struct plic_handler {
> >> > >
> >> > > to give some structure to the whole thing, because I'm pretty sure
> >> > > we'll see more braindead implementations as time goes by.
> >> >
> >> > What about using a feature flag (e.g. had_edge_irqs) instead?
> >>
> >> diff --git a/drivers/irqchip/irq-sifive-plic.c
> >> b/drivers/irqchip/irq-sifive-plic.c
> >> index 9f16833dcb41..247c3c98b655 100644
> >> --- a/drivers/irqchip/irq-sifive-plic.c
> >> +++ b/drivers/irqchip/irq-sifive-plic.c
> >> @@ -60,13 +60,13 @@
> >>  #define        PLIC_DISABLE_THRESHOLD          0x7
> >>  #define        PLIC_ENABLE_THRESHOLD           0
> >>
> >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
> >>
> >>  struct plic_priv {
> >>         struct cpumask lmask;
> >>         struct irq_domain *irqdomain;
> >>         void __iomem *regs;
> >> +       u32 plic_quirks;
> >>  };
> >>
> >> What about something like above?
> >
> > LGTM.
> >
> > Marc suggested to make this unsigned long, but TBH, that won't make
> > much of a difference.  PLICs are present on RV32 SoCs, too, so you
> > cannot rely on having more than 32 bits anyway.
>
> But it will make a difference on a 64bit platform, as we want to
> use test_bit() and co to check for features.
>
Ok will change that to unsigned long and use the test_bit/set_bit instead.

Cheers,
Prabhakar

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

On Mon, Jun 27, 2022 at 2:53 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2022-06-27 14:12, Geert Uytterhoeven wrote:
> > Hi Prabhakar,
> >
> > On Mon, Jun 27, 2022 at 3:06 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> >> On Mon, Jun 27, 2022 at 9:53 AM Geert Uytterhoeven
> >> <geert@linux-m68k.org> wrote:
> >> > On Sun, Jun 26, 2022 at 2:19 PM Marc Zyngier <maz@kernel.org> wrote:
> >> > > On Sun, 26 Jun 2022 10:38:18 +0100,
> >> > > "Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> >> > > > On Sun, Jun 26, 2022 at 9:56 AM Marc Zyngier <maz@kernel.org> wrote:
> >> > > > > On Sun, 26 Jun 2022 01:43:26 +0100,
> >> > > > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >> > > > > > The Renesas RZ/Five SoC has a RISC-V AX45MP AndesCore with NCEPLIC100. The
> >> > > > > > NCEPLIC100 supports both edge-triggered and level-triggered interrupts. In
> >> > > > > > case of edge-triggered interrupts NCEPLIC100 ignores the next interrupt
> >> > > > > > edge until the previous completion message has been received and
> >> > > > > > NCEPLIC100 doesn't support pending interrupt counter, hence losing the
> >> > > > > > interrupts if not acknowledged in time.
> >> > > > > >
> >> > > > > > So the workaround for edge-triggered interrupts to be handled correctly
> >> > > > > > and without losing is that it needs to be acknowledged first and then
> >> > > > > > handler must be run so that we don't miss on the next edge-triggered
> >> > > > > > interrupt.
> >> > > > > >
> >> > > > > > This patch adds a new compatible string for Renesas RZ/Five SoC and adds
> >> > > > > > support to change interrupt flow based on the interrupt type. It also
> >> > > > > > implements irq_ack and irq_set_type callbacks.
> >> > > > > >
> >> > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >> >
> >> > > > > > +     if (of_device_is_compatible(node, "renesas,r9a07g043-plic")) {
> >> > > > > > +             priv->of_data = RENESAS_R9A07G043_PLIC;
> >> > > > > > +             plic_chip.name = "Renesas RZ/Five PLIC";
> >> > > > >
> >> > > > > NAK. The irq_chip structure isn't the place for platform marketing.
> >> > > > > This is way too long anyway (and same for the edge version), and you
> >> > > > > even sent me a patch to make that structure const...
> >> > > > >
> >> > > > My bad will drop this.
> >> > >
> >> > > And why you're at it, please turn this rather random 'of_data' into
> >> > > something like:
> >> > >
> >> > > diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> >> > > index bb87e4c3b88e..cd1683b77caf 100644
> >> > > --- a/drivers/irqchip/irq-sifive-plic.c
> >> > > +++ b/drivers/irqchip/irq-sifive-plic.c
> >> > > @@ -64,6 +64,10 @@ struct plic_priv {
> >> > >         struct cpumask lmask;
> >> > >         struct irq_domain *irqdomain;
> >> > >         void __iomem *regs;
> >> > > +       enum {
> >> > > +               VANILLA_PLIC,
> >> > > +               RENESAS_R9A07G043_PLIC,
> >> > > +       } flavour;
> >> > >  };
> >> > >
> >> > >  struct plic_handler {
> >> > >
> >> > > to give some structure to the whole thing, because I'm pretty sure
> >> > > we'll see more braindead implementations as time goes by.
> >> >
> >> > What about using a feature flag (e.g. had_edge_irqs) instead?
> >>
> >> diff --git a/drivers/irqchip/irq-sifive-plic.c
> >> b/drivers/irqchip/irq-sifive-plic.c
> >> index 9f16833dcb41..247c3c98b655 100644
> >> --- a/drivers/irqchip/irq-sifive-plic.c
> >> +++ b/drivers/irqchip/irq-sifive-plic.c
> >> @@ -60,13 +60,13 @@
> >>  #define        PLIC_DISABLE_THRESHOLD          0x7
> >>  #define        PLIC_ENABLE_THRESHOLD           0
> >>
> >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
> >>
> >>  struct plic_priv {
> >>         struct cpumask lmask;
> >>         struct irq_domain *irqdomain;
> >>         void __iomem *regs;
> >> +       u32 plic_quirks;
> >>  };
> >>
> >> What about something like above?
> >
> > LGTM.
> >
> > Marc suggested to make this unsigned long, but TBH, that won't make
> > much of a difference.  PLICs are present on RV32 SoCs, too, so you
> > cannot rely on having more than 32 bits anyway.
>
> But it will make a difference on a 64bit platform, as we want to
> use test_bit() and co to check for features.
>
Ok will change that to unsigned long and use the test_bit/set_bit instead.

Cheers,
Prabhakar

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Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Marc Zyngier]

On 2022-06-27 13:27, Lad, Prabhakar wrote:
> Hi Marc,
> 
> Thank you for the review.
> 
> On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <maz@kernel.org> wrote:
>> 
>> On Sun, 26 Jun 2022 01:43:25 +0100,
>> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>> >
>> > Document Renesas RZ/Five (R9A07G043) SoC.
>> >
>> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> > ---
>> > v1->v2:
>> > * Fixed binding doc
>> > * Fixed review comments pointed by Krzysztof.
>> >
>> > RFC->v1:
>> > * Fixed Review comments pointed by Geert and Rob
>> > ---
>> >  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
>> >  1 file changed, 41 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > index 27092c6a86c4..59df367d1e44 100644
>> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > @@ -28,7 +28,10 @@ description:
>> >
>> >    While the PLIC supports both edge-triggered and level-triggered interrupts,
>> >    interrupt handlers are oblivious to this distinction and therefore it is not
>> > -  specified in the PLIC device-tree binding.
>> > +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
>> > +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
>> > +  to specify the interrupt type as the flow for EDGE interrupts is different
>> > +  compared to LEVEL interrupts.
>> >
>> >    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
>> >    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
>> > @@ -57,6 +60,7 @@ properties:
>> >            - enum:
>> >                - allwinner,sun20i-d1-plic
>> >            - const: thead,c900-plic
>> > +      - const: renesas,r9a07g043-plic
>> 
>> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
>> string actually reflect that? I'd rather see 'andes,nceplic100' once
>> and for all instead of starting with Renesas, quickly followed by all
>> the other licensees that will inevitably integrate the same IP (which
>> isn't even specific to the AX45MP).
>> 
>> This IP also comes with all sort of added (mis-)features, which may or
>> may not be used in the future, and it would make sense to identify it
>> specifically.
>> 
> Agreed, I'll update it as above.

Please synchronise with Samuel to have a common series that fixes
both the Renesas and Thead platforms.

Thanks,

          M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Marc Zyngier]

On 2022-06-27 13:27, Lad, Prabhakar wrote:
> Hi Marc,
> 
> Thank you for the review.
> 
> On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <maz@kernel.org> wrote:
>> 
>> On Sun, 26 Jun 2022 01:43:25 +0100,
>> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>> >
>> > Document Renesas RZ/Five (R9A07G043) SoC.
>> >
>> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>> > ---
>> > v1->v2:
>> > * Fixed binding doc
>> > * Fixed review comments pointed by Krzysztof.
>> >
>> > RFC->v1:
>> > * Fixed Review comments pointed by Geert and Rob
>> > ---
>> >  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
>> >  1 file changed, 41 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > index 27092c6a86c4..59df367d1e44 100644
>> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
>> > @@ -28,7 +28,10 @@ description:
>> >
>> >    While the PLIC supports both edge-triggered and level-triggered interrupts,
>> >    interrupt handlers are oblivious to this distinction and therefore it is not
>> > -  specified in the PLIC device-tree binding.
>> > +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
>> > +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
>> > +  to specify the interrupt type as the flow for EDGE interrupts is different
>> > +  compared to LEVEL interrupts.
>> >
>> >    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
>> >    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
>> > @@ -57,6 +60,7 @@ properties:
>> >            - enum:
>> >                - allwinner,sun20i-d1-plic
>> >            - const: thead,c900-plic
>> > +      - const: renesas,r9a07g043-plic
>> 
>> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
>> string actually reflect that? I'd rather see 'andes,nceplic100' once
>> and for all instead of starting with Renesas, quickly followed by all
>> the other licensees that will inevitably integrate the same IP (which
>> isn't even specific to the AX45MP).
>> 
>> This IP also comes with all sort of added (mis-)features, which may or
>> may not be used in the future, and it would make sense to identify it
>> specifically.
>> 
> Agreed, I'll update it as above.

Please synchronise with Samuel to have a common series that fixes
both the Renesas and Thead platforms.

Thanks,

          M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

On Mon, Jun 27, 2022 at 3:22 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2022-06-27 13:27, Lad, Prabhakar wrote:
> > Hi Marc,
> >
> > Thank you for the review.
> >
> > On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <maz@kernel.org> wrote:
> >>
> >> On Sun, 26 Jun 2022 01:43:25 +0100,
> >> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >> >
> >> > Document Renesas RZ/Five (R9A07G043) SoC.
> >> >
> >> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >> > ---
> >> > v1->v2:
> >> > * Fixed binding doc
> >> > * Fixed review comments pointed by Krzysztof.
> >> >
> >> > RFC->v1:
> >> > * Fixed Review comments pointed by Geert and Rob
> >> > ---
> >> >  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
> >> >  1 file changed, 41 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > index 27092c6a86c4..59df367d1e44 100644
> >> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > @@ -28,7 +28,10 @@ description:
> >> >
> >> >    While the PLIC supports both edge-triggered and level-triggered interrupts,
> >> >    interrupt handlers are oblivious to this distinction and therefore it is not
> >> > -  specified in the PLIC device-tree binding.
> >> > +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> >> > +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> >> > +  to specify the interrupt type as the flow for EDGE interrupts is different
> >> > +  compared to LEVEL interrupts.
> >> >
> >> >    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> >> >    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> >> > @@ -57,6 +60,7 @@ properties:
> >> >            - enum:
> >> >                - allwinner,sun20i-d1-plic
> >> >            - const: thead,c900-plic
> >> > +      - const: renesas,r9a07g043-plic
> >>
> >> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
> >> string actually reflect that? I'd rather see 'andes,nceplic100' once
> >> and for all instead of starting with Renesas, quickly followed by all
> >> the other licensees that will inevitably integrate the same IP (which
> >> isn't even specific to the AX45MP).
> >>
> >> This IP also comes with all sort of added (mis-)features, which may or
> >> may not be used in the future, and it would make sense to identify it
> >> specifically.
> >>
> > Agreed, I'll update it as above.
>
> Please synchronise with Samuel to have a common series that fixes
> both the Renesas and Thead platforms.
>
Yes Ive dropped an email to Samuel.

Cheers,
Prabhakar

Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC

[Lad, Prabhakar]

Hi Marc,

On Mon, Jun 27, 2022 at 3:22 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2022-06-27 13:27, Lad, Prabhakar wrote:
> > Hi Marc,
> >
> > Thank you for the review.
> >
> > On Sun, Jun 26, 2022 at 1:35 PM Marc Zyngier <maz@kernel.org> wrote:
> >>
> >> On Sun, 26 Jun 2022 01:43:25 +0100,
> >> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >> >
> >> > Document Renesas RZ/Five (R9A07G043) SoC.
> >> >
> >> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >> > ---
> >> > v1->v2:
> >> > * Fixed binding doc
> >> > * Fixed review comments pointed by Krzysztof.
> >> >
> >> > RFC->v1:
> >> > * Fixed Review comments pointed by Geert and Rob
> >> > ---
> >> >  .../sifive,plic-1.0.0.yaml                    | 44 +++++++++++++++++--
> >> >  1 file changed, 41 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > index 27092c6a86c4..59df367d1e44 100644
> >> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> >> > @@ -28,7 +28,10 @@ description:
> >> >
> >> >    While the PLIC supports both edge-triggered and level-triggered interrupts,
> >> >    interrupt handlers are oblivious to this distinction and therefore it is not
> >> > -  specified in the PLIC device-tree binding.
> >> > +  specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> >> > +  but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> >> > +  to specify the interrupt type as the flow for EDGE interrupts is different
> >> > +  compared to LEVEL interrupts.
> >> >
> >> >    While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> >> >    "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> >> > @@ -57,6 +60,7 @@ properties:
> >> >            - enum:
> >> >                - allwinner,sun20i-d1-plic
> >> >            - const: thead,c900-plic
> >> > +      - const: renesas,r9a07g043-plic
> >>
> >> Since it is the NCEPLIC100 that is broken, shouldn't the compatible
> >> string actually reflect that? I'd rather see 'andes,nceplic100' once
> >> and for all instead of starting with Renesas, quickly followed by all
> >> the other licensees that will inevitably integrate the same IP (which
> >> isn't even specific to the AX45MP).
> >>
> >> This IP also comes with all sort of added (mis-)features, which may or
> >> may not be used in the future, and it would make sense to identify it
> >> specifically.
> >>
> > Agreed, I'll update it as above.
>
> Please synchronise with Samuel to have a common series that fixes
> both the Renesas and Thead platforms.
>
Yes Ive dropped an email to Samuel.

Cheers,
Prabhakar

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Pavel Machek]

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Hi!

> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
> > >>
> > >>  struct plic_priv {
> > >>         struct cpumask lmask;
> > >>         struct irq_domain *irqdomain;
> > >>         void __iomem *regs;
> > >> +       u32 plic_quirks;
> > >>  };
> > >>
> > >> What about something like above?
> > >
> > > LGTM.
> > >
> > > Marc suggested to make this unsigned long, but TBH, that won't make
> > > much of a difference.  PLICs are present on RV32 SoCs, too, so you
> > > cannot rely on having more than 32 bits anyway.
> >
> > But it will make a difference on a 64bit platform, as we want to
> > use test_bit() and co to check for features.
> >
> Ok will change that to unsigned long and use the test_bit/set_bit instead.

Is there good enough reason for that? test_bit/... are when you need
atomicity, and that's not the case here. Plain old & ... should be
enough.

Best regards,
								Pavel
-- 
People of Russia, stop Putin before his war on Ukraine escalates.

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Pavel Machek]

[-- Attachment #1.1: Type: text/plain, Size: 1004 bytes --]

Hi!

> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
> > >>
> > >>  struct plic_priv {
> > >>         struct cpumask lmask;
> > >>         struct irq_domain *irqdomain;
> > >>         void __iomem *regs;
> > >> +       u32 plic_quirks;
> > >>  };
> > >>
> > >> What about something like above?
> > >
> > > LGTM.
> > >
> > > Marc suggested to make this unsigned long, but TBH, that won't make
> > > much of a difference.  PLICs are present on RV32 SoCs, too, so you
> > > cannot rely on having more than 32 bits anyway.
> >
> > But it will make a difference on a 64bit platform, as we want to
> > use test_bit() and co to check for features.
> >
> Ok will change that to unsigned long and use the test_bit/set_bit instead.

Is there good enough reason for that? test_bit/... are when you need
atomicity, and that's not the case here. Plain old & ... should be
enough.

Best regards,
								Pavel
-- 
People of Russia, stop Putin before his war on Ukraine escalates.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]

[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On 2022-06-29 14:41, Pavel Machek wrote:
> Hi!
> 
>> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>> > >>
>> > >>  struct plic_priv {
>> > >>         struct cpumask lmask;
>> > >>         struct irq_domain *irqdomain;
>> > >>         void __iomem *regs;
>> > >> +       u32 plic_quirks;
>> > >>  };
>> > >>
>> > >> What about something like above?
>> > >
>> > > LGTM.
>> > >
>> > > Marc suggested to make this unsigned long, but TBH, that won't make
>> > > much of a difference.  PLICs are present on RV32 SoCs, too, so you
>> > > cannot rely on having more than 32 bits anyway.
>> >
>> > But it will make a difference on a 64bit platform, as we want to
>> > use test_bit() and co to check for features.
>> >
>> Ok will change that to unsigned long and use the test_bit/set_bit 
>> instead.
> 
> Is there good enough reason for that? test_bit/... are when you need
> atomicity, and that's not the case here. Plain old & ... should be
> enough.

On any save architecture, '&' and test_bit() are the same thing.
Only RMW operations require atomicity.

'unsigned long' is is.

         M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas RZ/Five SoC

[Marc Zyngier]

On 2022-06-29 14:41, Pavel Machek wrote:
> Hi!
> 
>> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT      BIT(0)
>> > >>
>> > >>  struct plic_priv {
>> > >>         struct cpumask lmask;
>> > >>         struct irq_domain *irqdomain;
>> > >>         void __iomem *regs;
>> > >> +       u32 plic_quirks;
>> > >>  };
>> > >>
>> > >> What about something like above?
>> > >
>> > > LGTM.
>> > >
>> > > Marc suggested to make this unsigned long, but TBH, that won't make
>> > > much of a difference.  PLICs are present on RV32 SoCs, too, so you
>> > > cannot rely on having more than 32 bits anyway.
>> >
>> > But it will make a difference on a 64bit platform, as we want to
>> > use test_bit() and co to check for features.
>> >
>> Ok will change that to unsigned long and use the test_bit/set_bit 
>> instead.
> 
> Is there good enough reason for that? test_bit/... are when you need
> atomicity, and that's not the case here. Plain old & ... should be
> enough.

On any save architecture, '&' and test_bit() are the same thing.
Only RMW operations require atomicity.

'unsigned long' is is.

         M.
-- 
Jazz is not dead. It just smells funny...

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