From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6EFBC43334 for ; Tue, 28 Jun 2022 15:26:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346552AbiF1P0H (ORCPT ); Tue, 28 Jun 2022 11:26:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230499AbiF1P0G (ORCPT ); Tue, 28 Jun 2022 11:26:06 -0400 Received: from mail-io1-f45.google.com (mail-io1-f45.google.com [209.85.166.45]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09B742DA9D; Tue, 28 Jun 2022 08:26:06 -0700 (PDT) Received: by mail-io1-f45.google.com with SMTP id u20so13204462iob.8; Tue, 28 Jun 2022 08:26:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=wVoUetZ5S/GqO2CHeSuZD5HjqLM10h5uZxs1HR13hfg=; b=hllCHjeYk/PZ7+/WyqC1MfqxXQ9ewqwhA6ZXUBM+25j5duk2wN0pXwb2EveaHJ2ALI MZm08Rq7GqNUcBN31vHPEbeAYcHATm3d1p58cgIfRlfB2hLWrYf8lcyPSnq3KSfXrqcR rHBlanjcYDd+gImPiIdivVXXuUeNj8WGzNOQBte+qLxcUQlIi67ESRoblUzaQMMHq4iW pqvSJLzlK0LSd0p34TpDNt5hgppfws8LRgrJP+GhfZ+OXfY0IkOyYAFZU4yfGGchZtnf yD2BiupWhxVhEsnRy/lrtOiMeCO0DGNMLFzaLETZyR35GcfUupSKp14Jbtyurt2u5I8y m2uw== X-Gm-Message-State: AJIora8vjwLcQRxm33+vSw9jjsDpnCCfPLP7wceI4R2UhvDR/3WMiSke ZozJohOZiabnmUOMnYumBA== X-Google-Smtp-Source: AGRyM1u30z6rjSQP/yfjddK3j5eb9UHQa30g9hrzhKsueFxERdQlxns3zeN/rJtosCIDlaE+/J+6ew== X-Received: by 2002:a05:6638:14c3:b0:331:8153:e5b with SMTP id l3-20020a05663814c300b0033181530e5bmr11835574jak.114.1656429965253; Tue, 28 Jun 2022 08:26:05 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id y20-20020a6bd814000000b006751347e61bsm5482552iob.27.2022.06.28.08.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 08:26:04 -0700 (PDT) Received: (nullmailer pid 491422 invoked by uid 1000); Tue, 28 Jun 2022 15:26:01 -0000 Date: Tue, 28 Jun 2022 09:26:01 -0600 From: Rob Herring To: Serge Semin Cc: Conor Dooley , David Airlie , Daniel Vetter , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , Eugeniy Paltsev , Vinod Koul , Liam Girdwood , Mark Brown , Daniel Lezcano , Palmer Dabbelt , Palmer Dabbelt , Thomas Gleixner , Paul Walmsley , Albert Ou , Conor Dooley , Masahiro Yamada , Damien Le Moal , Geert Uytterhoeven , Niklas Cassel , Dillon Min , Heng Sia , Jose Abreu , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, alsa-devel@alsa-project.org, linux-spi@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 04/16] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width Message-ID: <20220628152601.GA465684-robh@kernel.org> References: <20220627194003.2395484-1-mail@conchuod.ie> <20220627194003.2395484-5-mail@conchuod.ie> <20220627202149.624eu7w2gzw7jchd@mobilestation> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220627202149.624eu7w2gzw7jchd@mobilestation> Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On Mon, Jun 27, 2022 at 11:21:49PM +0300, Serge Semin wrote: > On Mon, Jun 27, 2022 at 08:39:52PM +0100, Conor Dooley wrote: > > From: Conor Dooley > > > > Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the > > Canaan k210 is wired up for a width of 4. > > Quoting Serge: > > The modern DW APB SSI controllers of v.4.* and newer also support the > > enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core > > version is auto-detected at run-time there is no way to create a > > DT-schema correctly constraining the Rx/Tx SPI bus widths. > > /endquote > > > > As such, drop the restriction on only supporting a bus width of 1. > > > > Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ > > Signed-off-by: Conor Dooley > > --- > > Serge, I dropped your R-b when I swapped to the default > > property since it changed the enum. > > --- > > Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 6 ------ > > 1 file changed, 6 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > index e25d44c218f2..0a43d6e0ef91 100644 > > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > @@ -143,12 +143,6 @@ patternProperties: > > minimum: 0 > > maximum: 3 > > > > > - spi-rx-bus-width: > > - const: 1 > > - > > - spi-tx-bus-width: > > - const: 1 > > - > > My comment was: > > > > You can just use a more relaxed constraint "enum: [1 2 4 8]" here > > > > > > 8 too? sure. > Then Rob said: > > Then no constraints needed because the common definition already has > > this presumably. > > IMO preserving the device-specific constraints even if they match the > generic ones has some maintainability benefits. What if you get to > discover a new HW which supports Hexal mode? x16? Wouldn't we be back to parallel NOR and the problems with parallel buses? > Then you would have > needed to update the common schema constraints. But that would have > caused permitting the unsupported bus-mode for all the schemas, which > isn't correct. So as I see it the explicit bus-width enumeration would > be ok to have here. But I'll leave it for Rob to make a final > decision. Assuming a new width does appear, it's just a matter of time before the DW block has a new rev supporting it too, so there's 2 places to update. Also, a given platform may pinout less than the block supports, so you can't ever be 100% sure an out of range value is in a DT. But either way is okay with me. If you do keep constraints, you only need 'maximum: 8'. Acked-by: Rob Herring Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 274F7C43334 for ; Tue, 28 Jun 2022 15:26:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WSz8gKhyR+RVYTO1i/SNBM02X3AFpiaMwnng0Sys7pU=; b=BhKi8bjtqpOis9 y2qMPi5i+uX678pAMifZdwfMSY3GM+UlsfDr73wrgDcOU3b/8XsPW6RPxJ2UpeagQ230cX5WwT4Ph x5H+y7uRSh/R3N9tdYDz3QxWrtvRb2GcwGWEKNZPPs8i3QdB5+/xKZ7NmjJzJithfp4xJobcl4v/Y cGCVXpt9g6ftfbRegDSRfP+h/lqigPd8nkrOipBZEYOyXrj5Q8TMAXguHNQGqAUJucVQVxF0DRSGI aP3UoNcZTP/rOMz3HO7QL+++VNWHtLxVkeuCYBReFpB425p/iF7r3tS1ZqjIvZl/qtrp1+3yK1ppB JVB67W6HF0nyKppTf2ZA==; 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Tue, 28 Jun 2022 08:26:05 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id y20-20020a6bd814000000b006751347e61bsm5482552iob.27.2022.06.28.08.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 08:26:04 -0700 (PDT) Received: (nullmailer pid 491422 invoked by uid 1000); Tue, 28 Jun 2022 15:26:01 -0000 Date: Tue, 28 Jun 2022 09:26:01 -0600 From: Rob Herring To: Serge Semin Cc: Conor Dooley , David Airlie , Daniel Vetter , Krzysztof Kozlowski , Thierry Reding , Sam Ravnborg , Eugeniy Paltsev , Vinod Koul , Liam Girdwood , Mark Brown , Daniel Lezcano , Palmer Dabbelt , Palmer Dabbelt , Thomas Gleixner , Paul Walmsley , Albert Ou , Conor Dooley , Masahiro Yamada , Damien Le Moal , Geert Uytterhoeven , Niklas Cassel , Dillon Min , Heng Sia , Jose Abreu , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, alsa-devel@alsa-project.org, linux-spi@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v2 04/16] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width Message-ID: <20220628152601.GA465684-robh@kernel.org> References: <20220627194003.2395484-1-mail@conchuod.ie> <20220627194003.2395484-5-mail@conchuod.ie> <20220627202149.624eu7w2gzw7jchd@mobilestation> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220627202149.624eu7w2gzw7jchd@mobilestation> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220628_082606_977193_4A0794DB X-CRM114-Status: GOOD ( 27.71 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Mon, Jun 27, 2022 at 11:21:49PM +0300, Serge Semin wrote: > On Mon, Jun 27, 2022 at 08:39:52PM +0100, Conor Dooley wrote: > > From: Conor Dooley > > > > Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the > > Canaan k210 is wired up for a width of 4. > > Quoting Serge: > > The modern DW APB SSI controllers of v.4.* and newer also support the > > enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core > > version is auto-detected at run-time there is no way to create a > > DT-schema correctly constraining the Rx/Tx SPI bus widths. > > /endquote > > > > As such, drop the restriction on only supporting a bus width of 1. > > > > Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ > > Signed-off-by: Conor Dooley > > --- > > Serge, I dropped your R-b when I swapped to the default > > property since it changed the enum. > > --- > > Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 6 ------ > > 1 file changed, 6 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > index e25d44c218f2..0a43d6e0ef91 100644 > > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > @@ -143,12 +143,6 @@ patternProperties: > > minimum: 0 > > maximum: 3 > > > > > - spi-rx-bus-width: > > - const: 1 > > - > > - spi-tx-bus-width: > > - const: 1 > > - > > My comment was: > > > > You can just use a more relaxed constraint "enum: [1 2 4 8]" here > > > > > > 8 too? sure. > Then Rob said: > > Then no constraints needed because the common definition already has > > this presumably. > > IMO preserving the device-specific constraints even if they match the > generic ones has some maintainability benefits. What if you get to > discover a new HW which supports Hexal mode? x16? Wouldn't we be back to parallel NOR and the problems with parallel buses? > Then you would have > needed to update the common schema constraints. But that would have > caused permitting the unsupported bus-mode for all the schemas, which > isn't correct. So as I see it the explicit bus-width enumeration would > be ok to have here. But I'll leave it for Rob to make a final > decision. Assuming a new width does appear, it's just a matter of time before the DW block has a new rev supporting it too, so there's 2 places to update. Also, a given platform may pinout less than the block supports, so you can't ever be 100% sure an out of range value is in a DT. But either way is okay with me. If you do keep constraints, you only need 'maximum: 8'. Acked-by: Rob Herring Rob _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25A34CCA479 for ; Tue, 28 Jun 2022 15:26:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 38FB3113255; Tue, 28 Jun 2022 15:26:07 +0000 (UTC) Received: from mail-io1-f43.google.com (mail-io1-f43.google.com [209.85.166.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id EB055113255 for ; Tue, 28 Jun 2022 15:26:05 +0000 (UTC) Received: by mail-io1-f43.google.com with SMTP id s17so13206375iob.7 for ; Tue, 28 Jun 2022 08:26:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=wVoUetZ5S/GqO2CHeSuZD5HjqLM10h5uZxs1HR13hfg=; b=P/a3tKYAubROiXNXkFsv39+y6s47F4pirzbYJO4pY2aNh+DsW/YRl37YQw8wKxrZLY fksOsB3OUkWgobaFThf38HMyv9GA8eCL1JfuZLSAnoIu7n+r8I4KhiLUZoCkdwleiFln JqTxOqREbt8WpkHQbQFS9PTpIIYpn0mGqenCvMg13CG+kaPbWLmmiObcrmx7wD0Cmf2s MFPlbRfpWPqTHMNn9g2PyZuz9W1ADZB9T3nlM24ewLv5oBcbDvChyjlGgWjNUePOhHd1 +PtBd7osQjCFFEUJ8bJTuOwwmuE894ax6iHHCPRwvo/QUVGFo8PFjyELqEDY74O829P3 wdUA== X-Gm-Message-State: AJIora/MQhIHsollA7pWHs7LEK0t3RQLrgMHMU5aaXkTeJ7iMOtyTCrK vEA5PFTOFFqz15Pg59p06g== X-Google-Smtp-Source: AGRyM1u30z6rjSQP/yfjddK3j5eb9UHQa30g9hrzhKsueFxERdQlxns3zeN/rJtosCIDlaE+/J+6ew== X-Received: by 2002:a05:6638:14c3:b0:331:8153:e5b with SMTP id l3-20020a05663814c300b0033181530e5bmr11835574jak.114.1656429965253; Tue, 28 Jun 2022 08:26:05 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.253]) by smtp.gmail.com with ESMTPSA id y20-20020a6bd814000000b006751347e61bsm5482552iob.27.2022.06.28.08.26.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jun 2022 08:26:04 -0700 (PDT) Received: (nullmailer pid 491422 invoked by uid 1000); Tue, 28 Jun 2022 15:26:01 -0000 Date: Tue, 28 Jun 2022 09:26:01 -0600 From: Rob Herring To: Serge Semin Subject: Re: [PATCH v2 04/16] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width Message-ID: <20220628152601.GA465684-robh@kernel.org> References: <20220627194003.2395484-1-mail@conchuod.ie> <20220627194003.2395484-5-mail@conchuod.ie> <20220627202149.624eu7w2gzw7jchd@mobilestation> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220627202149.624eu7w2gzw7jchd@mobilestation> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Niklas Cassel , alsa-devel@alsa-project.org, David Airlie , Palmer Dabbelt , linux-kernel@vger.kernel.org, Conor Dooley , Thierry Reding , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Sam Ravnborg , Damien Le Moal , Daniel Lezcano , Jose Abreu , Geert Uytterhoeven , Eugeniy Paltsev , devicetree@vger.kernel.org, Albert Ou , Mark Brown , dri-devel@lists.freedesktop.org, Paul Walmsley , Conor Dooley , Thomas Gleixner , Dillon Min , Liam Girdwood , Heng Sia , linux-spi@vger.kernel.org, Vinod Koul , Palmer Dabbelt , dmaengine@vger.kernel.org, Masahiro Yamada Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, Jun 27, 2022 at 11:21:49PM +0300, Serge Semin wrote: > On Mon, Jun 27, 2022 at 08:39:52PM +0100, Conor Dooley wrote: > > From: Conor Dooley > > > > Most users of dw-apb-ssi use spi-{r,t}x-bus-width of 1, however the > > Canaan k210 is wired up for a width of 4. > > Quoting Serge: > > The modern DW APB SSI controllers of v.4.* and newer also support the > > enhanced SPI Modes too (Dual, Quad and Octal). Since the IP-core > > version is auto-detected at run-time there is no way to create a > > DT-schema correctly constraining the Rx/Tx SPI bus widths. > > /endquote > > > > As such, drop the restriction on only supporting a bus width of 1. > > > > Link: https://lore.kernel.org/all/20220620205654.g7fyipwytbww5757@mobilestation/ > > Signed-off-by: Conor Dooley > > --- > > Serge, I dropped your R-b when I swapped to the default > > property since it changed the enum. > > --- > > Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 6 ------ > > 1 file changed, 6 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > index e25d44c218f2..0a43d6e0ef91 100644 > > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml > > @@ -143,12 +143,6 @@ patternProperties: > > minimum: 0 > > maximum: 3 > > > > > - spi-rx-bus-width: > > - const: 1 > > - > > - spi-tx-bus-width: > > - const: 1 > > - > > My comment was: > > > > You can just use a more relaxed constraint "enum: [1 2 4 8]" here > > > > > > 8 too? sure. > Then Rob said: > > Then no constraints needed because the common definition already has > > this presumably. > > IMO preserving the device-specific constraints even if they match the > generic ones has some maintainability benefits. What if you get to > discover a new HW which supports Hexal mode? x16? Wouldn't we be back to parallel NOR and the problems with parallel buses? > Then you would have > needed to update the common schema constraints. But that would have > caused permitting the unsupported bus-mode for all the schemas, which > isn't correct. So as I see it the explicit bus-width enumeration would > be ok to have here. But I'll leave it for Rob to make a final > decision. Assuming a new width does appear, it's just a matter of time before the DW block has a new rev supporting it too, so there's 2 places to update. Also, a given platform may pinout less than the block supports, so you can't ever be 100% sure an out of range value is in a DT. But either way is okay with me. If you do keep constraints, you only need 'maximum: 8'. Acked-by: Rob Herring Rob