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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Joey Gouly <joey.gouly@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v6 08/27] arm64/sysreg: Align pointer auth enumeration defines with architecture
Date: Wed, 29 Jun 2022 11:28:15 +0100	[thread overview]
Message-ID: <20220629102834.36569-9-broonie@kernel.org> (raw)
In-Reply-To: <20220629102834.36569-1-broonie@kernel.org>

The defines used for the pointer authentication feature enumerations do not
follow the naming convention we've decided to use where we name things
after the architecture feature that introduced. Prepare for generating the
defines for the ISA ID registers by updating to use the feature names.
No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 34 ++++++++++++++++-----------------
 arch/arm64/kernel/cpufeature.c  | 24 +++++++++++------------
 2 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index ae86b422ac74..9a7e7b61d3ea 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -721,21 +721,21 @@
 #define ID_AA64ISAR1_DPB_SHIFT		0
 
 #define ID_AA64ISAR1_APA_NI			0x0
-#define ID_AA64ISAR1_APA_ARCHITECTED		0x1
+#define ID_AA64ISAR1_APA_PAuth			0x1
 #define ID_AA64ISAR1_APA_ARCH_EPAC		0x2
-#define ID_AA64ISAR1_APA_ARCH_EPAC2		0x3
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC	0x4
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR1_APA_Pauth2			0x3
+#define ID_AA64ISAR1_APA_FPAC			0x4
+#define ID_AA64ISAR1_APA_FPACCOMBINE		0x5
 #define ID_AA64ISAR1_API_NI			0x0
-#define ID_AA64ISAR1_API_IMP_DEF		0x1
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC		0x2
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2		0x3
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC	0x4
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR1_API_PAuth			0x1
+#define ID_AA64ISAR1_API_EPAC			0x2
+#define ID_AA64ISAR1_API_PAuth2			0x3
+#define ID_AA64ISAR1_API_FPAC			0x4
+#define ID_AA64ISAR1_API_FPACCOMBINE		0x5
 #define ID_AA64ISAR1_GPA_NI			0x0
-#define ID_AA64ISAR1_GPA_ARCHITECTED		0x1
+#define ID_AA64ISAR1_GPA_IMP			0x1
 #define ID_AA64ISAR1_GPI_NI			0x0
-#define ID_AA64ISAR1_GPI_IMP_DEF		0x1
+#define ID_AA64ISAR1_GPI_IMP			0x1
 
 /* id_aa64isar2 */
 #define ID_AA64ISAR2_CLEARBHB_SHIFT	28
@@ -755,14 +755,14 @@
 #define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
 
 #define ID_AA64ISAR2_APA3_NI			0x0
-#define ID_AA64ISAR2_APA3_ARCHITECTED		0x1
-#define ID_AA64ISAR2_APA3_ARCH_EPAC		0x2
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2		0x3
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC	0x4
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR2_APA3_PAuth			0x1
+#define ID_AA64ISAR2_APA3_EPAC			0x2
+#define ID_AA64ISAR2_APA3_PAuth2		0x3
+#define ID_AA64ISAR2_APA3_FPAC			0x4
+#define ID_AA64ISAR2_APA3_FPACCOMBINE		0x5
 
 #define ID_AA64ISAR2_GPA3_NI			0x0
-#define ID_AA64ISAR2_GPA3_ARCHITECTED		0x1
+#define ID_AA64ISAR2_GPA3_IMP			0x1
 
 /* id_aa64pfr0 */
 #define ID_AA64PFR0_CSV3_SHIFT		60
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 7d838b5f7e20..838b3dcd8473 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2317,7 +2317,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_APA_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR1_APA_PAuth,
 		.matches = has_address_auth_cpucap,
 	},
 	{
@@ -2328,7 +2328,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR2_APA3_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR2_APA3_PAuth,
 		.matches = has_address_auth_cpucap,
 	},
 	{
@@ -2339,7 +2339,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_API_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_API_IMP_DEF,
+		.min_field_value = ID_AA64ISAR1_API_PAuth,
 		.matches = has_address_auth_cpucap,
 	},
 	{
@@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_GPA_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR1_GPA_IMP,
 		.matches = has_cpuid_feature,
 	},
 	{
@@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR2_GPA3_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR2_GPA3_IMP,
 		.matches = has_cpuid_feature,
 	},
 	{
@@ -2377,7 +2377,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_GPI_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
+		.min_field_value = ID_AA64ISAR1_GPI_IMP,
 		.matches = has_cpuid_feature,
 	},
 	{
@@ -2562,15 +2562,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
 				  4, FTR_UNSIGNED,
-				  ID_AA64ISAR1_APA_ARCHITECTED)
+				  ID_AA64ISAR1_APA_PAuth)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED)
+				  4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
+				  4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth)
 	},
 	{},
 };
@@ -2578,15 +2578,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
+				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED)
+				  4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
+				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP)
 	},
 	{},
 };
-- 
2.30.2


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  parent reply	other threads:[~2022-06-29 10:36 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-29 10:28 [PATCH v6 00/27] arm64/sysreg: More system register generation Mark Brown
2022-06-29 10:28 ` [PATCH v6 01/27] arm64/cpuinfo: Remove refrences to reserved cache type Mark Brown
2022-07-04 13:04   ` Will Deacon
2022-07-04 15:49     ` Mark Brown
2022-06-29 10:28 ` [PATCH v6 02/27] arm64/sysreg: Allow leading blanks on comments in sysreg file Mark Brown
2022-06-29 10:28 ` [PATCH v6 03/27] arm64/sysreg: Add LINKER_SCRIPT guards for sysreg.h Mark Brown
2022-07-04 13:03   ` Will Deacon
2022-07-04 15:28     ` Mark Brown
2022-07-04 16:39       ` Will Deacon
2022-06-29 10:28 ` [PATCH v6 04/27] arm64/sysreg: Add SYS_FIELD_GET() helper Mark Brown
2022-06-29 10:28 ` [PATCH v6 05/27] arm64/sysreg: Standardise naming for CTR_EL0 fields Mark Brown
2022-06-29 10:28 ` [PATCH v6 06/27] arm64/sysreg: Standardise naming for DCZID_EL0 field names Mark Brown
2022-06-29 10:28 ` [PATCH v6 07/27] arm64/mte: Standardise GMID field name definitions Mark Brown
2022-06-29 10:28 ` Mark Brown [this message]
2022-06-29 10:28 ` [PATCH v6 09/27] arm64/sysreg: Make BHB clear feature defines match the architecture Mark Brown
2022-06-29 10:28 ` [PATCH v6 10/27] arm64/sysreg: Standardise naming for WFxT defines Mark Brown
2022-06-29 10:28 ` [PATCH v6 11/27] arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums Mark Brown
2022-06-29 10:28 ` [PATCH v6 12/27] arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields Mark Brown
2022-06-29 10:28 ` [PATCH v6 13/27] arm64/sysreg: Remove defines for RPRES enumeration Mark Brown
2022-06-29 10:28 ` [PATCH v6 14/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names Mark Brown
2022-06-29 10:28 ` [PATCH v6 15/27] arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 16/27] arm64/sysreg: Convert CTR_EL0 to automatic generation Mark Brown
2022-06-29 10:28 ` [PATCH v6 17/27] arm64/sysreg: Convert DCZID_EL0 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 18/27] arm64/sysreg: Convert GMID " Mark Brown
2022-06-29 10:28 ` [PATCH v6 19/27] arm64/sysreg: Convert ID_AA64ISAR1_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 20/27] arm64/sysreg: Convert ID_AA64ISAR2_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 21/27] arm64/sysreg: Convert LORSA_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 22/27] arm64/sysreg: Convert LOREA_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 23/27] arm64/sysreg: Convert LORN_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 24/27] arm64/sysreg: Convert LORC_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 25/27] arm64/sysreg: Convert LORID_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 26/27] arm64/sysreg: Convert ID_AA64SMFR0_EL1 " Mark Brown
2022-06-29 10:28 ` [PATCH v6 27/27] arm64/sysreg: Convert ID_AA64ZFR0_EL1 " Mark Brown

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