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[110.174.58.111]) by smtp.gmail.com with ESMTPSA id u27-20020a62d45b000000b0050dc7628148sm11267647pfl.34.2022.06.29.04.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 04:25:23 -0700 (PDT) Date: Wed, 29 Jun 2022 19:25:19 +0800 From: Kent Gibson To: =?utf-8?B?SmnFmcOt?= Prchal Cc: Andy Shevchenko , "open list:GPIO SUBSYSTEM" , Bartosz Golaszewski Subject: Re: [libgpiod] feature request: output state read and sustain Message-ID: <20220629112519.GA30910@sol> References: <48129be0-f29d-96ae-cec3-2b4a2ee10aa8@aksignal.cz> <20220325160146.GA49114@sol> <1d43c967-e3c9-21a8-3040-2db54ba85bdf@aksignal.cz> <20220328080841.GA14353@sol> <757ac53e-07bb-1ffa-2734-08c1c321ff0e@aksignal.cz> <20220629072353.GA18684@sol> <20220629104757.GA29289@sol> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, Jun 29, 2022 at 01:17:54PM +0200, Jiří Prchal wrote: > > > On 29. 06. 22 12:47, Kent Gibson wrote: > > On Wed, Jun 29, 2022 at 12:27:13PM +0200, Andy Shevchenko wrote: > > > On Wed, Jun 29, 2022 at 11:27 AM Jiří Prchal wrote: > > > > On 29. 06. 22 9:23, Kent Gibson wrote: > > > > > On Tue, Jun 28, 2022 at 03:08:20PM +0200, Jiří Prchal wrote: > > > > > > > > > using new libgpiod / chardev driver, is there any way to get state of > > > > > > output? I mean one process sets it for example to 1 and another process > > > > > > reads this output state for example to show that on web page. > > > > > > I'm not sure it's guaranteed to read output back. Some (b0rken?) GPIO > > > chips may not allow this on H/W level and when reading they always > > > will get the value of Input Buffer (now imagine if the line is > > > configured as Output with Input being disconnected from the physical > > > pin). > > > > > > > Agreed. Userspace should know the value they set the output to, and so > > have no need to read it back. GPIO is not NVM. > Not NVM, bat RAM and it keeps their data untill reset, after reset it has specific value (usually 0) > I haven't seen HW without possibility of reading back output register, but I don't say there couldn't be such one. > No, no it is not RAM. And I have seen hardware where you can't read back the output. And so has Andy apparently. That is the problem - there is lots of hardware out there and we are trying to provide a consistent interface to inconsistent hardware. Cheers, Kent.