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From: Sudeep Holla <sudeep.holla@arm.com>
To: Conor.Dooley@microchip.com
Cc: linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org,
	atishp@atishpatra.org, atishp@rivosinc.com,
	vincent.guittot@linaro.org, dietmar.eggemann@arm.com,
	wangqing@vivo.com, robh+dt@kernel.org, rafael@kernel.org,
	ionela.voinescu@arm.com, pierre.gondois@arm.com,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, gshan@redhat.com,
	Valentina.FernandezAlanis@microchip.com
Subject: Re: [PATCH v5 09/19] arch_topology: Use the last level cache information from the cacheinfo
Date: Wed, 29 Jun 2022 19:33:48 +0100	[thread overview]
Message-ID: <20220629183348.ga7gbcsba57dzf2t@bogus> (raw)
In-Reply-To: <3656a067-cc3f-fd5b-e339-5925a856cce1@microchip.com>

On Wed, Jun 29, 2022 at 06:18:25PM +0000, Conor.Dooley@microchip.com wrote:
> On 29/06/2022 18:49, Conor.Dooley@microchip.com wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 27/06/2022 17:50, Sudeep Holla wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> The cacheinfo is now initialised early along with the CPU topology
> >> initialisation. Instead of relying on the LLC ID information parsed
> >> separately only with ACPI PPTT elsewhere, migrate to use the similar
> >> information from the cacheinfo.
> >>
> >> This is generic for both DT and ACPI systems. The ACPI LLC ID information
> >> parsed separately can now be removed from arch specific code.
> > 
> > Hey Sudeep,
> > I bisected broken boot on PolarFire SoC to this patch in next-20220629 :/
> > I suspect the issue is a missing "next-level-cache" in the the dt:
> > arch/riscv/boot/dts/microchip/mpfs.dtsi
> > 
> > Adding next-level-cache = <&cctrllr> fixes the boot.
>

If the above is missing, even the existing cacheinfo will be incorrect on
that system. But we must end up with L1 as LLC, I need to check if that
breaks the boot.

> No, no it doesn't. Not sure what I was thinking there.
> Prob tested that on the the last commit that bisect tested
> rather than the one it pointed out the problem was with.
>

So can I assume the pointed commit is where the boot breaks ?

> Either way, boot is broken in -next.
>

OK, that's bad. 

> > Not sure what the resolution here is, old devicetrees are meant to keep
> > booting, right?
> >

Ideally yes. But with this, I assume the cacheinfo to userspace is also broken
on this platform and I guess that needs fixing which can happen with DT update
only.

--
Regards,
Sudeep

WARNING: multiple messages have this Message-ID (diff)
From: Sudeep Holla <sudeep.holla@arm.com>
To: Conor.Dooley@microchip.com
Cc: linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org,
	atishp@atishpatra.org, atishp@rivosinc.com,
	vincent.guittot@linaro.org, dietmar.eggemann@arm.com,
	wangqing@vivo.com, robh+dt@kernel.org, rafael@kernel.org,
	ionela.voinescu@arm.com, pierre.gondois@arm.com,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, gshan@redhat.com,
	Valentina.FernandezAlanis@microchip.com
Subject: Re: [PATCH v5 09/19] arch_topology: Use the last level cache information from the cacheinfo
Date: Wed, 29 Jun 2022 19:33:48 +0100	[thread overview]
Message-ID: <20220629183348.ga7gbcsba57dzf2t@bogus> (raw)
In-Reply-To: <3656a067-cc3f-fd5b-e339-5925a856cce1@microchip.com>

On Wed, Jun 29, 2022 at 06:18:25PM +0000, Conor.Dooley@microchip.com wrote:
> On 29/06/2022 18:49, Conor.Dooley@microchip.com wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 27/06/2022 17:50, Sudeep Holla wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> The cacheinfo is now initialised early along with the CPU topology
> >> initialisation. Instead of relying on the LLC ID information parsed
> >> separately only with ACPI PPTT elsewhere, migrate to use the similar
> >> information from the cacheinfo.
> >>
> >> This is generic for both DT and ACPI systems. The ACPI LLC ID information
> >> parsed separately can now be removed from arch specific code.
> > 
> > Hey Sudeep,
> > I bisected broken boot on PolarFire SoC to this patch in next-20220629 :/
> > I suspect the issue is a missing "next-level-cache" in the the dt:
> > arch/riscv/boot/dts/microchip/mpfs.dtsi
> > 
> > Adding next-level-cache = <&cctrllr> fixes the boot.
>

If the above is missing, even the existing cacheinfo will be incorrect on
that system. But we must end up with L1 as LLC, I need to check if that
breaks the boot.

> No, no it doesn't. Not sure what I was thinking there.
> Prob tested that on the the last commit that bisect tested
> rather than the one it pointed out the problem was with.
>

So can I assume the pointed commit is where the boot breaks ?

> Either way, boot is broken in -next.
>

OK, that's bad. 

> > Not sure what the resolution here is, old devicetrees are meant to keep
> > booting, right?
> >

Ideally yes. But with this, I assume the cacheinfo to userspace is also broken
on this platform and I guess that needs fixing which can happen with DT update
only.

--
Regards,
Sudeep

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Sudeep Holla <sudeep.holla@arm.com>
To: Conor.Dooley@microchip.com
Cc: linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org,
	atishp@atishpatra.org, atishp@rivosinc.com,
	vincent.guittot@linaro.org, dietmar.eggemann@arm.com,
	wangqing@vivo.com, robh+dt@kernel.org, rafael@kernel.org,
	ionela.voinescu@arm.com, pierre.gondois@arm.com,
	linux-arm-kernel@lists.infradead.org,
	linux-riscv@lists.infradead.org, gshan@redhat.com,
	Valentina.FernandezAlanis@microchip.com
Subject: Re: [PATCH v5 09/19] arch_topology: Use the last level cache information from the cacheinfo
Date: Wed, 29 Jun 2022 19:33:48 +0100	[thread overview]
Message-ID: <20220629183348.ga7gbcsba57dzf2t@bogus> (raw)
In-Reply-To: <3656a067-cc3f-fd5b-e339-5925a856cce1@microchip.com>

On Wed, Jun 29, 2022 at 06:18:25PM +0000, Conor.Dooley@microchip.com wrote:
> On 29/06/2022 18:49, Conor.Dooley@microchip.com wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > 
> > On 27/06/2022 17:50, Sudeep Holla wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>
> >> The cacheinfo is now initialised early along with the CPU topology
> >> initialisation. Instead of relying on the LLC ID information parsed
> >> separately only with ACPI PPTT elsewhere, migrate to use the similar
> >> information from the cacheinfo.
> >>
> >> This is generic for both DT and ACPI systems. The ACPI LLC ID information
> >> parsed separately can now be removed from arch specific code.
> > 
> > Hey Sudeep,
> > I bisected broken boot on PolarFire SoC to this patch in next-20220629 :/
> > I suspect the issue is a missing "next-level-cache" in the the dt:
> > arch/riscv/boot/dts/microchip/mpfs.dtsi
> > 
> > Adding next-level-cache = <&cctrllr> fixes the boot.
>

If the above is missing, even the existing cacheinfo will be incorrect on
that system. But we must end up with L1 as LLC, I need to check if that
breaks the boot.

> No, no it doesn't. Not sure what I was thinking there.
> Prob tested that on the the last commit that bisect tested
> rather than the one it pointed out the problem was with.
>

So can I assume the pointed commit is where the boot breaks ?

> Either way, boot is broken in -next.
>

OK, that's bad. 

> > Not sure what the resolution here is, old devicetrees are meant to keep
> > booting, right?
> >

Ideally yes. But with this, I assume the cacheinfo to userspace is also broken
on this platform and I guess that needs fixing which can happen with DT update
only.

--
Regards,
Sudeep

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-06-29 18:35 UTC|newest]

Thread overview: 144+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-27 16:50 [PATCH v5 00/19] arch_topology: Updates to add socket support and fix cluster ids Sudeep Holla
2022-06-27 16:50 ` Sudeep Holla
2022-06-27 16:50 ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 01/19] ACPI: PPTT: Use table offset as fw_token instead of virtual address Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 02/19] cacheinfo: Use of_cpu_device_node_get instead cpu_dev->of_node Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 03/19] cacheinfo: Add helper to access any cache index for a given CPU Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 04/19] cacheinfo: Move cache_leaves_are_shared out of CONFIG_OF Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 05/19] cacheinfo: Add support to check if last level cache(LLC) is valid or shared Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 06/19] cacheinfo: Allow early detection and population of cache attributes Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 07/19] cacheinfo: Use cache identifiers to check if the caches are shared if available Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 08/19] arch_topology: Add support to parse and detect cache attributes Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 09/19] arch_topology: Use the last level cache information from the cacheinfo Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-29 17:49   ` Conor.Dooley
2022-06-29 17:49     ` Conor.Dooley
2022-06-29 17:49     ` Conor.Dooley
2022-06-29 18:18     ` Conor.Dooley
2022-06-29 18:18       ` Conor.Dooley
2022-06-29 18:18       ` Conor.Dooley
2022-06-29 18:33       ` Sudeep Holla [this message]
2022-06-29 18:33         ` Sudeep Holla
2022-06-29 18:33         ` Sudeep Holla
2022-06-29 18:42       ` Sudeep Holla
2022-06-29 18:42         ` Sudeep Holla
2022-06-29 18:42         ` Sudeep Holla
2022-06-29 19:39         ` Conor.Dooley
2022-06-29 19:39           ` Conor.Dooley
2022-06-29 19:39           ` Conor.Dooley
2022-06-29 19:54           ` Sudeep Holla
2022-06-29 19:54             ` Sudeep Holla
2022-06-29 19:54             ` Sudeep Holla
2022-06-29 20:32             ` Conor.Dooley
2022-06-29 20:32               ` Conor.Dooley
2022-06-29 20:32               ` Conor.Dooley
2022-06-29 23:25               ` Conor.Dooley
2022-06-29 23:25                 ` Conor.Dooley
2022-06-29 23:25                 ` Conor.Dooley
2022-06-30 10:39                 ` Sudeep Holla
2022-06-30 10:39                   ` Sudeep Holla
2022-06-30 10:39                   ` Sudeep Holla
2022-06-30 16:37                   ` Conor.Dooley
2022-06-30 16:37                     ` Conor.Dooley
2022-06-30 16:37                     ` Conor.Dooley
2022-06-30 17:35                     ` Sudeep Holla
2022-06-30 17:35                       ` Sudeep Holla
2022-06-30 17:35                       ` Sudeep Holla
2022-06-30 19:20                       ` Conor.Dooley
2022-06-30 19:20                         ` Conor.Dooley
2022-06-30 19:20                         ` Conor.Dooley
2022-06-30 20:07                         ` Sudeep Holla
2022-06-30 20:07                           ` Sudeep Holla
2022-06-30 20:07                           ` Sudeep Holla
2022-06-30 20:13                           ` Conor.Dooley
2022-06-30 20:13                             ` Conor.Dooley
2022-06-30 20:13                             ` Conor.Dooley
2022-06-30 20:21                             ` Sudeep Holla
2022-06-30 20:21                               ` Sudeep Holla
2022-06-30 20:21                               ` Sudeep Holla
2022-06-30 22:07                               ` Conor.Dooley
2022-06-30 22:07                                 ` Conor.Dooley
2022-06-30 22:07                                 ` Conor.Dooley
2022-07-01 11:11                                 ` Sudeep Holla
2022-07-01 11:11                                   ` Sudeep Holla
2022-07-01 11:11                                   ` Sudeep Holla
2022-07-01 14:47                                   ` Conor.Dooley
2022-07-01 14:47                                     ` Conor.Dooley
2022-07-01 14:47                                     ` Conor.Dooley
2022-06-29 18:47       ` Sudeep Holla
2022-06-29 18:47         ` Sudeep Holla
2022-06-29 18:47         ` Sudeep Holla
2022-06-29 18:56         ` Conor.Dooley
2022-06-29 18:56           ` Conor.Dooley
2022-06-29 18:56           ` Conor.Dooley
2022-06-29 19:12           ` Sudeep Holla
2022-06-29 19:12             ` Sudeep Holla
2022-06-29 19:12             ` Sudeep Holla
2022-06-29 19:25             ` Conor.Dooley
2022-06-29 19:25               ` Conor.Dooley
2022-06-29 19:25               ` Conor.Dooley
2022-06-29 19:43               ` Sudeep Holla
2022-06-29 19:43                 ` Sudeep Holla
2022-06-29 19:43                 ` Sudeep Holla
2022-06-29 19:52                 ` Conor.Dooley
2022-06-29 19:52                   ` Conor.Dooley
2022-06-29 19:52                   ` Conor.Dooley
2022-06-29 18:29     ` Sudeep Holla
2022-06-29 18:29       ` Sudeep Holla
2022-06-29 18:29       ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 10/19] arm64: topology: Remove redundant setting of llc_id in CPU topology Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 11/19] arch_topology: Drop LLC identifier stash from the " Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 12/19] arch_topology: Set thread sibling cpumask only within the cluster Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 13/19] arch_topology: Check for non-negative value rather than -1 for IDs validity Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 14/19] arch_topology: Avoid parsing through all the CPUs once a outlier CPU is found Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 15/19] arch_topology: Don't set cluster identifier as physical package identifier Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 16/19] arch_topology: Limit span of cpu_clustergroup_mask() Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-28 10:28   ` Vincent Guittot
2022-06-28 10:28     ` Vincent Guittot
2022-06-28 10:28     ` Vincent Guittot
2022-06-27 16:50 ` [PATCH v5 17/19] arch_topology: Set cluster identifier in each core/thread from /cpu-map Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 18/19] arch_topology: Add support for parsing sockets in /cpu-map Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50 ` [PATCH v5 19/19] arch_topology: Warn that topology for nested clusters is not supported Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-27 16:50   ` Sudeep Holla
2022-06-29 13:06 ` [PATCH] ACPI: Remove the unused find_acpi_cpu_cache_topology() Sudeep Holla
2022-06-29 13:06   ` Sudeep Holla
2022-06-29 13:06   ` Sudeep Holla
2022-06-29 13:50   ` Rafael J. Wysocki
2022-06-29 13:50     ` Rafael J. Wysocki
2022-06-29 13:50     ` Rafael J. Wysocki

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