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From: Ard Biesheuvel <ardb@kernel.org>
To: linux-arm-kernel@lists.infradead.org
Cc: "Ard Biesheuvel" <ardb@kernel.org>,
	"Will Deacon" <will@kernel.org>, "Marc Zyngier" <maz@kernel.org>,
	"Pierre-Clément Tosi" <ptosi@google.com>,
	"Quentin Perret" <qperret@google.com>,
	"Mark Rutland" <mark.rutland@arm.com>
Subject: [PATCH 0/6] arm64: efi: boot with MMU and caches on if possible
Date: Thu, 30 Jun 2022 16:42:24 +0200	[thread overview]
Message-ID: <20220630144230.2332555-1-ardb@kernel.org> (raw)

This small series is what remains now that much of the prerequisite
changes that are shared with other work have landed. This is a follow-up
to [0], and implements the necessary changes that allow the EFI stub to
enter the kernel proper with MMU and caches enabled.

This is possible because the EFI spec mandates that all of memory is
mapped, and so we can rely on this mapping to set up the initial ID map,
instead of taking down the MMU first, and populating those page tables
using non-cacheable accesses that require special care in terms of cache
coherency. This also means that there is no need to clean the executable
image to the point of coherency (with the exception of the contents of
.idmap.text, which contains the code that switches from the firmware's
ID map to the kernel one)

Given that the image will typically be mapped by the firmware according
to the section descriptors in the PE/COFF header (R-X for .text and
.rodata, RW- for .data and .bss), this also has a slight robustness
advantage.

Note that this does not update the documented boot protocol [yet],
although any loader could take advantage of this, and load the kernel
image at any 64k aligned physical offset, and enter the image with the
MMU still enabled, either at EL2 or EL1.

[0] https://lore.kernel.org/linux-arm-kernel/20220330154205.2483167-1-ardb@kernel.org/

Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Pierre-Clément Tosi <ptosi@google.com>
Cc: Quentin Perret <qperret@google.com>
Cc: Mark Rutland <mark.rutland@arm.com>

Ard Biesheuvel (6):
  arm64: lds: reduce effective minimum image alignment to 64k
  arm64: kernel: move ID map out of .text mapping
  arm64: head: record the MMU state at primary entry
  arm64: head: avoid cache invalidation when entering with the MMU on
  arm64: head: clean the ID map page to the PoC
  arm64: efi/libstub: enter with the MMU on if executing in place

 arch/arm64/include/asm/efi.h              |  7 ---
 arch/arm64/kernel/efi-entry.S             |  4 ++
 arch/arm64/kernel/head.S                  | 45 ++++++++++++++++++--
 arch/arm64/kernel/vmlinux.lds.S           | 13 +++++-
 arch/arm64/mm/proc.S                      |  2 -
 drivers/firmware/efi/libstub/arm64-stub.c |  2 +-
 include/linux/efi.h                       |  6 +--
 7 files changed, 58 insertions(+), 21 deletions(-)

-- 
2.35.1


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             reply	other threads:[~2022-06-30 14:43 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-30 14:42 Ard Biesheuvel [this message]
2022-06-30 14:42 ` [PATCH 1/6] arm64: lds: reduce effective minimum image alignment to 64k Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 2/6] arm64: kernel: move ID map out of .text mapping Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 3/6] arm64: head: record the MMU state at primary entry Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 4/6] arm64: head: avoid cache invalidation when entering with the MMU on Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 5/6] arm64: head: clean the ID map page to the PoC Ard Biesheuvel
2022-06-30 14:42 ` [PATCH 6/6] arm64: efi/libstub: enter with the MMU on if executing in place Ard Biesheuvel

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