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envelope-from=prvs=176813b30=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Anup Patel The latest AIA draft v0.3.0 defines a relatively simpler scheme for default priority assignments where: 1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use and have implementation specific default priority. 2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended (not mandatory) priority assignments. We update the default priority table and hviprio mapping as-per above. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 2 +- target/riscv/cpu_helper.c | 134 ++++++++++++++++++-------------------- 2 files changed, 66 insertions(+), 70 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 157d7069f6..6be5a9e9f0 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -774,7 +774,7 @@ typedef enum RISCVException { #define IPRIO_IRQ_BITS 8 #define IPRIO_MMAXIPRIO 255 #define IPRIO_DEFAULT_UPPER 4 -#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 24) +#define IPRIO_DEFAULT_MIDDLE (IPRIO_DEFAULT_UPPER + 12) #define IPRIO_DEFAULT_M IPRIO_DEFAULT_MIDDLE #define IPRIO_DEFAULT_S (IPRIO_DEFAULT_M + 3) #define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_S + 3) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index be28615e23..59b3680b1b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -168,17 +168,17 @@ void riscv_cpu_update_mask(CPURISCVState *env) * 14 " * 15 " * 16 " - * 18 Debug/trace interrupt - * 20 (Reserved interrupt) + * 17 " + * 18 " + * 19 " + * 20 " + * 21 " * 22 " - * 24 " - * 26 " - * 28 " - * 30 (Reserved for standard reporting of bus or system errors) + * 23 " */ =20 static const int hviprio_index2irq[] =3D { - 0, 1, 4, 5, 8, 13, 14, 15, 16, 18, 20, 22, 24, 26, 28, 30 }; + 0, 1, 4, 5, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 }; static const int hviprio_index2rdzero[] =3D { 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; =20 @@ -207,50 +207,60 @@ int riscv_cpu_hviprio_index2irq(int index, int *out= _irq, int *out_rdzero) * Default | * Priority | Major Interrupt Numbers * ---------------------------------------------------------------- - * Highest | 63 (3f), 62 (3e), 31 (1f), 30 (1e), 61 (3d), 60 (3c), - * | 59 (3b), 58 (3a), 29 (1d), 28 (1c), 57 (39), 56 (38), - * | 55 (37), 54 (36), 27 (1b), 26 (1a), 53 (35), 52 (34), - * | 51 (33), 50 (32), 25 (19), 24 (18), 49 (31), 48 (30) + * Highest | 47, 23, 46, 45, 22, 44, + * | 43, 21, 42, 41, 20, 40 * | * | 11 (0b), 3 (03), 7 (07) * | 9 (09), 1 (01), 5 (05) * | 12 (0c) * | 10 (0a), 2 (02), 6 (06) * | - * | 47 (2f), 46 (2e), 23 (17), 22 (16), 45 (2d), 44 (2c), - * | 43 (2b), 42 (2a), 21 (15), 20 (14), 41 (29), 40 (28), - * | 39 (27), 38 (26), 19 (13), 18 (12), 37 (25), 36 (24), - * Lowest | 35 (23), 34 (22), 17 (11), 16 (10), 33 (21), 32 (20) + * | 39, 19, 38, 37, 18, 36, + * Lowest | 35, 17, 34, 33, 16, 32 * ---------------------------------------------------------------- */ static const uint8_t default_iprio[64] =3D { - [63] =3D IPRIO_DEFAULT_UPPER, - [62] =3D IPRIO_DEFAULT_UPPER + 1, - [31] =3D IPRIO_DEFAULT_UPPER + 2, - [30] =3D IPRIO_DEFAULT_UPPER + 3, - [61] =3D IPRIO_DEFAULT_UPPER + 4, - [60] =3D IPRIO_DEFAULT_UPPER + 5, - - [59] =3D IPRIO_DEFAULT_UPPER + 6, - [58] =3D IPRIO_DEFAULT_UPPER + 7, - [29] =3D IPRIO_DEFAULT_UPPER + 8, - [28] =3D IPRIO_DEFAULT_UPPER + 9, - [57] =3D IPRIO_DEFAULT_UPPER + 10, - [56] =3D IPRIO_DEFAULT_UPPER + 11, - - [55] =3D IPRIO_DEFAULT_UPPER + 12, - [54] =3D IPRIO_DEFAULT_UPPER + 13, - [27] =3D IPRIO_DEFAULT_UPPER + 14, - [26] =3D IPRIO_DEFAULT_UPPER + 15, - [53] =3D IPRIO_DEFAULT_UPPER + 16, - [52] =3D IPRIO_DEFAULT_UPPER + 17, - - [51] =3D IPRIO_DEFAULT_UPPER + 18, - [50] =3D IPRIO_DEFAULT_UPPER + 19, - [25] =3D IPRIO_DEFAULT_UPPER + 20, - [24] =3D IPRIO_DEFAULT_UPPER + 21, - [49] =3D IPRIO_DEFAULT_UPPER + 22, - [48] =3D IPRIO_DEFAULT_UPPER + 23, + /* Custom interrupts 48 to 63 */ + [63] =3D IPRIO_MMAXIPRIO, + [62] =3D IPRIO_MMAXIPRIO, + [61] =3D IPRIO_MMAXIPRIO, + [60] =3D IPRIO_MMAXIPRIO, + [59] =3D IPRIO_MMAXIPRIO, + [58] =3D IPRIO_MMAXIPRIO, + [57] =3D IPRIO_MMAXIPRIO, + [56] =3D IPRIO_MMAXIPRIO, + [55] =3D IPRIO_MMAXIPRIO, + [54] =3D IPRIO_MMAXIPRIO, + [53] =3D IPRIO_MMAXIPRIO, + [52] =3D IPRIO_MMAXIPRIO, + [51] =3D IPRIO_MMAXIPRIO, + [50] =3D IPRIO_MMAXIPRIO, + [49] =3D IPRIO_MMAXIPRIO, + [48] =3D IPRIO_MMAXIPRIO, + + /* Custom interrupts 24 to 31 */ + [31] =3D IPRIO_MMAXIPRIO, + [30] =3D IPRIO_MMAXIPRIO, + [29] =3D IPRIO_MMAXIPRIO, + [28] =3D IPRIO_MMAXIPRIO, + [27] =3D IPRIO_MMAXIPRIO, + [26] =3D IPRIO_MMAXIPRIO, + [25] =3D IPRIO_MMAXIPRIO, + [24] =3D IPRIO_MMAXIPRIO, + + [47] =3D IPRIO_DEFAULT_UPPER, + [23] =3D IPRIO_DEFAULT_UPPER + 1, + [46] =3D IPRIO_DEFAULT_UPPER + 2, + [45] =3D IPRIO_DEFAULT_UPPER + 3, + [22] =3D IPRIO_DEFAULT_UPPER + 4, + [44] =3D IPRIO_DEFAULT_UPPER + 5, + + [43] =3D IPRIO_DEFAULT_UPPER + 6, + [21] =3D IPRIO_DEFAULT_UPPER + 7, + [42] =3D IPRIO_DEFAULT_UPPER + 8, + [41] =3D IPRIO_DEFAULT_UPPER + 9, + [20] =3D IPRIO_DEFAULT_UPPER + 10, + [40] =3D IPRIO_DEFAULT_UPPER + 11, =20 [11] =3D IPRIO_DEFAULT_M, [3] =3D IPRIO_DEFAULT_M + 1, @@ -266,33 +276,19 @@ static const uint8_t default_iprio[64] =3D { [2] =3D IPRIO_DEFAULT_VS + 1, [6] =3D IPRIO_DEFAULT_VS + 2, =20 - [47] =3D IPRIO_DEFAULT_LOWER, - [46] =3D IPRIO_DEFAULT_LOWER + 1, - [23] =3D IPRIO_DEFAULT_LOWER + 2, - [22] =3D IPRIO_DEFAULT_LOWER + 3, - [45] =3D IPRIO_DEFAULT_LOWER + 4, - [44] =3D IPRIO_DEFAULT_LOWER + 5, - - [43] =3D IPRIO_DEFAULT_LOWER + 6, - [42] =3D IPRIO_DEFAULT_LOWER + 7, - [21] =3D IPRIO_DEFAULT_LOWER + 8, - [20] =3D IPRIO_DEFAULT_LOWER + 9, - [41] =3D IPRIO_DEFAULT_LOWER + 10, - [40] =3D IPRIO_DEFAULT_LOWER + 11, - - [39] =3D IPRIO_DEFAULT_LOWER + 12, - [38] =3D IPRIO_DEFAULT_LOWER + 13, - [19] =3D IPRIO_DEFAULT_LOWER + 14, - [18] =3D IPRIO_DEFAULT_LOWER + 15, - [37] =3D IPRIO_DEFAULT_LOWER + 16, - [36] =3D IPRIO_DEFAULT_LOWER + 17, - - [35] =3D IPRIO_DEFAULT_LOWER + 18, - [34] =3D IPRIO_DEFAULT_LOWER + 19, - [17] =3D IPRIO_DEFAULT_LOWER + 20, - [16] =3D IPRIO_DEFAULT_LOWER + 21, - [33] =3D IPRIO_DEFAULT_LOWER + 22, - [32] =3D IPRIO_DEFAULT_LOWER + 23, + [39] =3D IPRIO_DEFAULT_LOWER, + [19] =3D IPRIO_DEFAULT_LOWER + 1, + [38] =3D IPRIO_DEFAULT_LOWER + 2, + [37] =3D IPRIO_DEFAULT_LOWER + 3, + [18] =3D IPRIO_DEFAULT_LOWER + 4, + [36] =3D IPRIO_DEFAULT_LOWER + 5, + + [35] =3D IPRIO_DEFAULT_LOWER + 6, + [17] =3D IPRIO_DEFAULT_LOWER + 7, + [34] =3D IPRIO_DEFAULT_LOWER + 8, + [33] =3D IPRIO_DEFAULT_LOWER + 9, + [16] =3D IPRIO_DEFAULT_LOWER + 10, + [32] =3D IPRIO_DEFAULT_LOWER + 11, }; =20 uint8_t riscv_cpu_default_priority(int irq) --=20 2.36.1