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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 01/62] accel/tcg: Introduce PageEntryExtra
Date: Sun,  3 Jul 2022 13:53:18 +0530	[thread overview]
Message-ID: <20220703082419.770989-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220703082419.770989-1-richard.henderson@linaro.org>

Add an optional structure, controlled by TARGET_PAGE_ENTRY_EXTRA,
that allows arbitrary extra data to be saved in the TLB for a
given page.  Set it with tlb_set_page_with_extra() and fetch it
with probe_access_extra().

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/cpu-defs.h |  5 +++
 include/exec/exec-all.h | 26 +++++++++++++--
 include/qemu/typedefs.h |  1 +
 accel/tcg/cputlb.c      | 73 ++++++++++++++++++++++++++++++-----------
 4 files changed, 84 insertions(+), 21 deletions(-)

diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index ba3cd32a1e..f14586e219 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -76,6 +76,10 @@ typedef uint64_t target_ulong;
 
 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
 
+#ifndef TARGET_PAGE_ENTRY_EXTRA
+struct PageEntryExtra { };
+#endif
+
 /* use a fully associative victim tlb of 8 entries */
 #define CPU_VTLB_SIZE 8
 
@@ -148,6 +152,7 @@ typedef struct CPUIOTLBEntry {
      */
     hwaddr addr;
     MemTxAttrs attrs;
+    PageEntryExtra extra;
 } CPUIOTLBEntry;
 
 /*
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 311e5fb422..2c036de3d8 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -259,11 +259,12 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
                                                unsigned bits);
 
 /**
- * tlb_set_page_with_attrs:
+ * tlb_set_page_with_extra:
  * @cpu: CPU to add this TLB entry for
  * @vaddr: virtual address of page to add entry for
  * @paddr: physical address of the page
  * @attrs: memory transaction attributes
+ * @extra: cpu specific extra information
  * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
  * @mmu_idx: MMU index to insert TLB entry for
  * @size: size of the page in bytes
@@ -279,11 +280,25 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
  * At most one entry for a given virtual address is permitted. Only a
  * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
  * used by tlb_flush_page.
+ *
+ * The @extra information is target-specific, and may be retrieved
+ * by calling probe_access_extra().
+ */
+void tlb_set_page_with_extra(CPUState *cpu, target_ulong vaddr, hwaddr paddr,
+                             MemTxAttrs attrs, PageEntryExtra extra,
+                             int prot, int mmu_idx, target_ulong size);
+
+/**
+ * tlb_set_page_with_attrs:
+ *
+ * This function is equivalent to calling tlb_set_page_with_extra()
+ * with an @extra argument of all zeros.
  */
 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
                              hwaddr paddr, MemTxAttrs attrs,
                              int prot, int mmu_idx, target_ulong size);
-/* tlb_set_page:
+/**
+ * tlb_set_page:
  *
  * This function is equivalent to calling tlb_set_page_with_attrs()
  * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
@@ -435,6 +450,13 @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
                        MMUAccessType access_type, int mmu_idx,
                        bool nonfault, void **phost, uintptr_t retaddr);
 
+#ifdef CONFIG_SOFTMMU
+int probe_access_extra(CPUArchState *env, target_ulong addr,
+                       MMUAccessType access_type, int mmu_idx,
+                       bool nonfault, void **phost, MemTxAttrs *pattrs,
+                       PageEntryExtra *pextra, uintptr_t retaddr);
+#endif
+
 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 
 /* Estimated block size for TB allocation.  */
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 42f4ceb701..a4de3bb07c 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -82,6 +82,7 @@ typedef struct NodeInfo NodeInfo;
 typedef struct NumaNodeMem NumaNodeMem;
 typedef struct Object Object;
 typedef struct ObjectClass ObjectClass;
+typedef struct PageEntryExtra PageEntryExtra;
 typedef struct PCIBridge PCIBridge;
 typedef struct PCIBus PCIBus;
 typedef struct PCIDevice PCIDevice;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f90f4312ea..05555961c9 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1095,16 +1095,21 @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
     env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask;
 }
 
-/* Add a new TLB entry. At most one entry for a given virtual address
+/*
+ * Add a new TLB entry. At most one entry for a given virtual address
  * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
  * supplied size is only used by tlb_flush_page.
  *
  * Called from TCG-generated code, which is under an RCU read-side
  * critical section.
+ *
+ * Returns a pointer to the iotlb entry, with env_tlb(env)->c.lock
+ * still locked, for final additions to the iotlb entry.  The caller
+ * must unlock the lock.
  */
-void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
-                             hwaddr paddr, MemTxAttrs attrs, int prot,
-                             int mmu_idx, target_ulong size)
+void tlb_set_page_with_extra(CPUState *cpu, target_ulong vaddr, hwaddr paddr,
+                             MemTxAttrs attrs, PageEntryExtra extra,
+                             int prot, int mmu_idx, target_ulong size)
 {
     CPUArchState *env = cpu->env_ptr;
     CPUTLB *tlb = env_tlb(env);
@@ -1238,6 +1243,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
      */
     desc->iotlb[index].addr = iotlb - vaddr_page;
     desc->iotlb[index].attrs = attrs;
+    desc->iotlb[index].extra = extra;
 
     /* Now calculate the new entry */
     tn.addend = addend - vaddr_page;
@@ -1272,7 +1278,23 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
     qemu_spin_unlock(&tlb->c.lock);
 }
 
-/* Add a new TLB entry, but without specifying the memory
+/*
+ * Add a new TLB entry, specifying the memory transaction
+ * attributes to be used.
+ */
+void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
+                             hwaddr paddr, MemTxAttrs attrs, int prot,
+                             int mmu_idx, target_ulong size)
+{
+    PageEntryExtra extra;
+
+    memset(&extra, 0, sizeof(extra));
+    tlb_set_page_with_extra(cpu, vaddr, paddr, attrs, extra,
+                            prot, mmu_idx, size);
+}
+
+/*
+ * Add a new TLB entry, but without specifying the memory
  * transaction attributes to be used.
  */
 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
@@ -1633,25 +1655,38 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
     return flags;
 }
 
+int probe_access_extra(CPUArchState *env, target_ulong addr,
+                       MMUAccessType access_type, int mmu_idx,
+                       bool nonfault, void **phost, MemTxAttrs *pattrs,
+                       PageEntryExtra *pextra, uintptr_t retaddr)
+{
+    int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
+                                      nonfault, phost, retaddr);
+
+    if (likely(!(flags & TLB_INVALID_MASK))) {
+        uintptr_t index = tlb_index(env, mmu_idx, addr);
+        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
+
+        /* Handle clean RAM pages.  */
+        if (unlikely(flags & TLB_NOTDIRTY)) {
+            notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
+            flags &= ~TLB_NOTDIRTY;
+        }
+        *pattrs = iotlbentry->attrs;
+        *pextra = iotlbentry->extra;
+    }
+    return flags;
+}
+
 int probe_access_flags(CPUArchState *env, target_ulong addr,
                        MMUAccessType access_type, int mmu_idx,
                        bool nonfault, void **phost, uintptr_t retaddr)
 {
-    int flags;
+    MemTxAttrs attrs;
+    PageEntryExtra extra;
 
-    flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
-                                  nonfault, phost, retaddr);
-
-    /* Handle clean RAM pages.  */
-    if (unlikely(flags & TLB_NOTDIRTY)) {
-        uintptr_t index = tlb_index(env, mmu_idx, addr);
-        CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
-
-        notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
-        flags &= ~TLB_NOTDIRTY;
-    }
-
-    return flags;
+    return probe_access_extra(env, addr, access_type, mmu_idx, nonfault,
+                              phost, &attrs, &extra, retaddr);
 }
 
 void *probe_access(CPUArchState *env, target_ulong addr, int size,
-- 
2.34.1



  reply	other threads:[~2022-07-03  8:26 UTC|newest]

Thread overview: 100+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-03  8:23 [PATCH 00/62] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-07-03  8:23 ` Richard Henderson [this message]
2022-07-04 15:28   ` [PATCH 01/62] accel/tcg: Introduce PageEntryExtra Peter Maydell
2022-07-05  0:35     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 02/62] target/arm: Enable PageEntryExtra Richard Henderson
2022-07-04 15:22   ` Peter Maydell
2022-07-05  1:01     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 03/62] target/arm: Fix MTE check in sve_ldnfff1_r Richard Henderson
2022-07-05 12:05   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 04/62] target/arm: Record tagged bit for user-only in sve_probe_page Richard Henderson
2022-07-05 12:09   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 05/62] target/arm: Use PageEntryExtra for MTE Richard Henderson
2022-07-05 12:47   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 06/62] target/arm: Use PageEntryExtra for BTI Richard Henderson
2022-07-05 14:12   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 07/62] include/exec: Remove target_tlb_bitN from MemTxAttrs Richard Henderson
2022-07-05 14:12   ` Peter Maydell
2022-07-03  8:23 ` [PATCH 08/62] target/arm: Create GetPhysAddrResult Richard Henderson
2022-08-10 13:02   ` Alex Bennée
2022-08-19 17:31     ` Richard Henderson
2022-07-03  8:23 ` [PATCH 09/62] target/arm: Fix ipa_secure in get_phys_addr Richard Henderson
2022-07-03  8:23 ` [PATCH 10/62] target/arm: Use GetPhysAddrResult in get_phys_addr_lpae Richard Henderson
2022-08-10 13:04   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 11/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v6 Richard Henderson
2022-08-10 13:04   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 12/62] target/arm: Use GetPhysAddrResult in get_phys_addr_v5 Richard Henderson
2022-08-10 13:05   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 13/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav5 Richard Henderson
2022-08-10 13:05   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 14/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav7 Richard Henderson
2022-08-10 13:06   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 15/62] target/arm: Use GetPhysAddrResult in get_phys_addr_pmsav8 Richard Henderson
2022-08-10 13:06   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 16/62] target/arm: Use GetPhysAddrResult in pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:09   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 17/62] target/arm: Remove is_subpage argument to pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:11   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 18/62] target/arm: Add is_secure parameter to v8m_security_lookup Richard Henderson
2022-08-10 13:13   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 19/62] target/arm: Add is_secure parameter to pmsav8_mpu_lookup Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 20/62] target/arm: Add is_secure parameter to get_phys_addr_v5 Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 21/62] target/arm: Add is_secure parameter to get_phys_addr_v6 Richard Henderson
2022-08-10 13:15   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 22/62] target/arm: Add secure parameter to get_phys_addr_pmsav8 Richard Henderson
2022-08-10 13:16   ` Alex Bennée
2022-08-10 15:33     ` Richard Henderson
2022-08-10 18:46       ` Alex Bennée
2022-07-03  8:23 ` [PATCH 23/62] target/arm: Add is_secure parameter to pmsav7_use_background_region Richard Henderson
2022-08-10 13:17   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 24/62] target/arm: Add is_secure parameter to get_phys_addr_lpae Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 25/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav7 Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 26/62] target/arm: Add is_secure parameter to regime_translation_disabled Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 27/62] target/arm: Add is_secure parameter to get_phys_addr_pmsav5 Richard Henderson
2022-08-10 13:18   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 28/62] target/arm: Split out get_phys_addr_with_secure Richard Henderson
2022-07-03  8:23 ` [PATCH 29/62] target/arm: Add is_secure parameter to v7m_read_half_insn Richard Henderson
2022-08-10 13:27   ` Alex Bennée
2022-07-03  8:23 ` [PATCH 30/62] target/arm: Add TBFLAG_M32.SECURE Richard Henderson
2022-07-03  8:23 ` [PATCH 31/62] target/arm: Merge regime_is_secure into get_phys_addr Richard Henderson
2022-07-03  8:23 ` [PATCH 32/62] target/arm: Add is_secure parameter to do_ats_write Richard Henderson
2022-07-03  8:23 ` [PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes Richard Henderson
2022-07-03  8:23 ` [PATCH 34/62] target/arm: Reorg regime_translation_disabled Richard Henderson
2022-07-03  8:23 ` [PATCH 35/62] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M Richard Henderson
2022-07-03  8:23 ` [PATCH 36/62] target/arm: Introduce arm_hcr_el2_eff_secstate Richard Henderson
2022-07-03  8:23 ` [PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate Richard Henderson
2022-07-03  8:23 ` [PATCH 38/62] target/arm: Fix S2 disabled check " Richard Henderson
2022-07-03  8:23 ` [PATCH 39/62] target/arm: Remove env argument from combined_attrs_fwb Richard Henderson
2022-07-03  8:23 ` [PATCH 40/62] target/arm: Pass HCR to attribute subroutines Richard Henderson
2022-07-03  8:23 ` [PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1 Richard Henderson
2022-07-03  8:23 ` [PATCH 42/62] target/arm: Split out get_phys_addr_disabled Richard Henderson
2022-07-03  8:24 ` [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled Richard Henderson
2022-07-03  8:24 ` [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS} Richard Henderson
2022-07-03  8:24 ` [PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx Richard Henderson
2022-07-03  8:24 ` [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking Richard Henderson
2022-07-03  8:24 ` [PATCH 47/62] target/arm: Hoist check for disabled stage2 translation Richard Henderson
2022-07-03  8:24 ` [PATCH 48/62] target/arm: Split out get_phys_addr_twostage Richard Henderson
2022-07-03  8:24 ` [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines Richard Henderson
2022-07-03  8:24 ` [PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation Richard Henderson
2022-07-03  8:24 ` [PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate Richard Henderson
2022-07-03  8:24 ` [PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS Richard Henderson
2022-07-03  8:24 ` [PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters Richard Henderson
2022-07-03  8:24 ` [PATCH 54/62] target/arm: Split out S1TranslateResult type Richard Henderson
2022-07-03  8:24 ` [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult Richard Henderson
2022-07-03  8:24 ` [PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Richard Henderson
2022-07-03  8:24 ` [PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate Richard Henderson
2022-07-03  8:24 ` [PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae Richard Henderson
2022-07-03  8:24 ` [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae Richard Henderson
2022-07-03  8:24 ` [PATCH 60/62] target/arm: Don't shift attrs " Richard Henderson
2022-07-03  8:24 ` [PATCH 61/62] target/arm: Consider GP an attribute " Richard Henderson
2022-07-03  8:24 ` [PATCH 62/62] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-07-04 14:54 ` [PATCH 00/62] " Peter Maydell
2022-07-04 14:58   ` Richard Henderson
2022-07-04 15:57     ` Peter Maydell
2022-08-12 16:31 ` Peter Maydell
2022-08-12 17:54   ` Richard Henderson

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