From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40E7EC433EF for ; Wed, 6 Jul 2022 14:37:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230232AbiGFOhH (ORCPT ); Wed, 6 Jul 2022 10:37:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229792AbiGFOhG (ORCPT ); Wed, 6 Jul 2022 10:37:06 -0400 Received: from mail-io1-f48.google.com (mail-io1-f48.google.com [209.85.166.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0149022511; Wed, 6 Jul 2022 07:37:03 -0700 (PDT) Received: by mail-io1-f48.google.com with SMTP id r133so14177222iod.3; Wed, 06 Jul 2022 07:37:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=BO6eBhC7unEc5DAXkBz59T47rbusdIS+hGohLImKruE=; b=QKJcI6Bp0B1eSaw6DDpE2N/PfwBMZcWH4b9q4+dWtH9UGM6uJMhF16yeh7nJqDdkzq sZi8i0Z7FZqlmGOLA9UJitHnjiqsooO9Z47uohW3LNmnGQXf848j4rRN/WJYueSGsUtk YJ03ojbBdp6Jz4rHZMres3hTSJwJsy8i1zOhepXz45l+yUhWO2uYCchf8j9zIhjP4dju 0NnSrz5J5Bt56mN2NllhCX6fEEPs8ObZrs2MM0D8m3Q/udiBwFTmSnvnp23XgfM0CEm9 H3LQAvngufkKodbP3VBc1YnDPpjoCSRNBLV7Ng057/aKEmuTdQitSbKp/aKDphDiDXnZ 1yWw== X-Gm-Message-State: AJIora8eAgZq1x2Q/3ZsHXPaM2aBkLX6QvPe/U9QTeD2o26fVqYN9TAE spJG6XzDBR7NRlIUXdYjEQ== X-Google-Smtp-Source: AGRyM1uwogNqbjjsWF2UgQe/CajDfMiG+sh6Ni2OjP0BX9xF2QmOazErflXLRz0+SMeIhacevi0Dxg== X-Received: by 2002:a05:6638:491a:b0:33e:f73f:b138 with SMTP id cx26-20020a056638491a00b0033ef73fb138mr4759038jab.21.1657118222100; Wed, 06 Jul 2022 07:37:02 -0700 (PDT) Received: from robh.at.kernel.org ([64.188.179.248]) by smtp.gmail.com with ESMTPSA id g18-20020a05663810f200b00339d5108b60sm15982358jae.17.2022.07.06.07.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Jul 2022 07:37:01 -0700 (PDT) Received: (nullmailer pid 5054 invoked by uid 1000); Wed, 06 Jul 2022 14:36:58 -0000 Date: Wed, 6 Jul 2022 08:36:58 -0600 From: Rob Herring To: "Viorel Suman (OSS)" Cc: Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Dmitry Torokhov , Srinivas Kandagatla , Dong Aisheng , Fabio Estevam , Shawn Guo , Stefan Agner , Pengutronix Kernel Team , Linus Walleij , Alessandro Zummo , Alexandre Belloni , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui , Wim Van Sebroeck , Guenter Roeck , Sascha Hauer , NXP Linux Team , Abel Vesa , Viorel Suman , Peng Fan , Mirela Rabulea , Liu Ying , Oliver Graute , Ming Qian , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-input@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-pm@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Abel Vesa Subject: Re: [PATCH v7 09/15] dt-bindings: firmware: Add fsl,scu yaml file Message-ID: <20220706143658.GA4191302-robh@kernel.org> References: <20220704161541.943696-1-viorel.suman@oss.nxp.com> <20220704161541.943696-10-viorel.suman@oss.nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220704161541.943696-10-viorel.suman@oss.nxp.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Mon, Jul 04, 2022 at 07:15:35PM +0300, Viorel Suman (OSS) wrote: > From: Abel Vesa > > In order to replace the fsl,scu txt file from bindings/arm/freescale, > we need to split it between the right subsystems. This patch adds the > fsl,scu.yaml in the firmware bindings folder. This one is only for > the main SCU node. The old txt file will be removed only after all > the child nodes have been properly switch to yaml. > > Signed-off-by: Abel Vesa > Signed-off-by: Viorel Suman > --- > .../bindings/arm/freescale/fsl,scu.txt | 96 ----------- > .../devicetree/bindings/firmware/fsl,scu.yaml | 160 ++++++++++++++++++ > 2 files changed, 160 insertions(+), 96 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml > > diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > deleted file mode 100644 > index e1cc72741f1f..000000000000 > --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > +++ /dev/null > @@ -1,96 +0,0 @@ > -NXP i.MX System Controller Firmware (SCFW) > --------------------------------------------------------------------- > - > -The System Controller Firmware (SCFW) is a low-level system function > -which runs on a dedicated Cortex-M core to provide power, clock, and > -resource management. It exists on some i.MX8 processors. e.g. i.MX8QM > -(QM, QP), and i.MX8QX (QXP, DX). > - > -The AP communicates with the SC using a multi-ported MU module found > -in the LSIO subsystem. The current definition of this MU module provides > -5 remote AP connections to the SC to support up to 5 execution environments > -(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces > -with the LSIO DSC IP bus. The SC firmware will communicate with this MU > -using the MSI bus. > - > -System Controller Device Node: > -============================================================ > - > -The scu node with the following properties shall be under the /firmware/ node. > - > -Required properties: > -------------------- > -- compatible: should be "fsl,imx-scu". > -- mbox-names: should include "tx0", "tx1", "tx2", "tx3", > - "rx0", "rx1", "rx2", "rx3"; > - include "gip3" if want to support general MU interrupt. > -- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for > - rx, and 1 optional MU channel for general interrupt. > - All MU channels must be in the same MU instance. > - Cross instances are not allowed. The MU instance can only > - be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need > - to make sure use the one which is not conflict with other > - execution environments. e.g. ATF. > - Note: > - Channel 0 must be "tx0" or "rx0". > - Channel 1 must be "tx1" or "rx1". > - Channel 2 must be "tx2" or "rx2". > - Channel 3 must be "tx3" or "rx3". > - General interrupt rx channel must be "gip3". > - e.g. > - mboxes = <&lsio_mu1 0 0 > - &lsio_mu1 0 1 > - &lsio_mu1 0 2 > - &lsio_mu1 0 3 > - &lsio_mu1 1 0 > - &lsio_mu1 1 1 > - &lsio_mu1 1 2 > - &lsio_mu1 1 3 > - &lsio_mu1 3 3>; > - See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml > - for detailed mailbox binding. > - > -Note: Each mu which supports general interrupt should have an alias correctly > -numbered in "aliases" node. > -e.g. > -aliases { > - mu1 = &lsio_mu1; > -}; > - > -i.MX SCU Client Device Node: > -============================================================ > - > -Client nodes are maintained as children of the relevant IMX-SCU device node. > - > -Example (imx8qxp): > -------------- > -aliases { > - mu1 = &lsio_mu1; > -}; > - > -lsio_mu1: mailbox@5d1c0000 { > - ... > - #mbox-cells = <2>; > -}; > - > -firmware { > - scu { > - compatible = "fsl,imx-scu"; > - mbox-names = "tx0", "tx1", "tx2", "tx3", > - "rx0", "rx1", "rx2", "rx3", > - "gip3"; > - mboxes = <&lsio_mu1 0 0 > - &lsio_mu1 0 1 > - &lsio_mu1 0 2 > - &lsio_mu1 0 3 > - &lsio_mu1 1 0 > - &lsio_mu1 1 1 > - &lsio_mu1 1 2 > - &lsio_mu1 1 3 > - &lsio_mu1 3 3>; > - }; > -}; > - > -serial@5a060000 { > - ... > -}; > diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml > new file mode 100644 > index 000000000000..c1f5b727352e > --- /dev/null > +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml > @@ -0,0 +1,160 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX System Controller Firmware (SCFW) > + > +maintainers: > + - Dong Aisheng > + > +description: System Controller Device Node The formatting here is not maintained unless you use a literal block ('|'). But I would just drop this first line. > + The System Controller Firmware (SCFW) is a low-level system function > + which runs on a dedicated Cortex-M core to provide power, clock, and > + resource management. It exists on some i.MX8 processors. e.g. i.MX8QM > + (QM, QP), and i.MX8QX (QXP, DX). > + The AP communicates with the SC using a multi-ported MU module found > + in the LSIO subsystem. The current definition of this MU module provides > + 5 remote AP connections to the SC to support up to 5 execution environments > + (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces > + with the LSIO DSC IP bus. The SC firmware will communicate with this MU > + using the MSI bus. > + > +properties: > + compatible: > + const: fsl,imx-scu > + > + clock-controller: > + description: > + Clock controller node that provides the clocks controlled by the SCU > + $ref: /schemas/clock/fsl,scu-clk.yaml > + > + ocotp: > + description: > + OCOTP controller node provided by the SCU > + $ref: /schemas/nvmem/fsl,scu-ocotp.yaml > + > + keys: > + description: > + Keys provided by the SCU > + $ref: /schemas/input/fsl,scu-key.yaml > + > + mboxes: > + description: | > + List of phandle of 4 MU channels for tx, 4 MU channels for > + rx, and 1 optional MU channel for general interrupt. > + All MU channels must be in the same MU instance. > + Cross instances are not allowed. The MU instance can only > + be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need > + to make sure use the one which is not conflict with other > + execution environments. e.g. ATF. > + minItems: 1 > + maxItems: 10 Based on the description, shouldn't this be: minItems: 8 maxItems: 9 > + > + mbox-names: > + description: > + include "gip3" if want to support general MU interrupt. What are all the other names? Needs to be a schema, not freeform text. > + minItems: 1 > + maxItems: 10 > + > + pinctrl: > + description: > + Pin controller provided by the SCU > + $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml > + > + power-controller: > + description: | > + Power domains controller node that provides the power domains > + controlled by the SCU > + $ref: /schemas/power/fsl,scu-pd.yaml > + > + rtc: > + description: > + RTC controller provided by the SCU > + $ref: /schemas/rtc/fsl,scu-rtc.yaml > + > + thermal-sensor: > + description: > + Thermal sensor provided by the SCU > + $ref: /schemas/thermal/fsl,scu-thermal.yaml > + > + watchdog: > + description: > + Watchdog controller provided by the SCU > + $ref: /schemas/watchdog/fsl,scu-wdt.yaml > + > +required: > + - compatible > + - mbox-names > + - mboxes > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + firmware { > + system-controller { > + compatible = "fsl,imx-scu"; > + mbox-names = "tx0", "tx1", "tx2", "tx3", > + "rx0", "rx1", "rx2", "rx3", > + "gip3"; > + mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3 > + &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3 > + &lsio_mu1 3 3>; > + > + clock-controller { > + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; > + #clock-cells = <2>; > + }; > + > + pinctrl { > + compatible = "fsl,imx8qxp-iomuxc"; > + > + pinctrl_lpuart0: lpuart0grp { > + fsl,pins = < > + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 > + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 > + >; > + }; > + }; > + > + ocotp { > + compatible = "fsl,imx8qxp-scu-ocotp"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + fec_mac0: mac@2c4 { > + reg = <0x2c4 6>; > + }; > + }; > + > + power-controller { > + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; > + #power-domain-cells = <1>; > + }; > + > + rtc { > + compatible = "fsl,imx8qxp-sc-rtc"; > + }; > + > + keys { > + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; > + linux,keycodes = ; > + }; > + > + watchdog { > + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; > + timeout-sec = <60>; > + }; > + > + thermal-sensor { > + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; > + #thermal-sensor-cells = <1>; > + }; > + }; > + }; > -- > 2.25.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E5B9C433EF for ; Wed, 6 Jul 2022 14:38:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Wed, 06 Jul 2022 07:37:01 -0700 (PDT) Received: (nullmailer pid 5054 invoked by uid 1000); Wed, 06 Jul 2022 14:36:58 -0000 Date: Wed, 6 Jul 2022 08:36:58 -0600 From: Rob Herring To: "Viorel Suman (OSS)" Cc: Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Dmitry Torokhov , Srinivas Kandagatla , Dong Aisheng , Fabio Estevam , Shawn Guo , Stefan Agner , Pengutronix Kernel Team , Linus Walleij , Alessandro Zummo , Alexandre Belloni , "Rafael J. Wysocki" , Daniel Lezcano , Amit Kucheria , Zhang Rui , Wim Van Sebroeck , Guenter Roeck , Sascha Hauer , NXP Linux Team , Abel Vesa , Viorel Suman , Peng Fan , Mirela Rabulea , Liu Ying , Oliver Graute , Ming Qian , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-input@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-pm@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Abel Vesa Subject: Re: [PATCH v7 09/15] dt-bindings: firmware: Add fsl,scu yaml file Message-ID: <20220706143658.GA4191302-robh@kernel.org> References: <20220704161541.943696-1-viorel.suman@oss.nxp.com> <20220704161541.943696-10-viorel.suman@oss.nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220704161541.943696-10-viorel.suman@oss.nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220706_073706_676428_E7E8BFB8 X-CRM114-Status: GOOD ( 34.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 04, 2022 at 07:15:35PM +0300, Viorel Suman (OSS) wrote: > From: Abel Vesa > > In order to replace the fsl,scu txt file from bindings/arm/freescale, > we need to split it between the right subsystems. This patch adds the > fsl,scu.yaml in the firmware bindings folder. This one is only for > the main SCU node. The old txt file will be removed only after all > the child nodes have been properly switch to yaml. > > Signed-off-by: Abel Vesa > Signed-off-by: Viorel Suman > --- > .../bindings/arm/freescale/fsl,scu.txt | 96 ----------- > .../devicetree/bindings/firmware/fsl,scu.yaml | 160 ++++++++++++++++++ > 2 files changed, 160 insertions(+), 96 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > create mode 100644 Documentation/devicetree/bindings/firmware/fsl,scu.yaml > > diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > deleted file mode 100644 > index e1cc72741f1f..000000000000 > --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt > +++ /dev/null > @@ -1,96 +0,0 @@ > -NXP i.MX System Controller Firmware (SCFW) > --------------------------------------------------------------------- > - > -The System Controller Firmware (SCFW) is a low-level system function > -which runs on a dedicated Cortex-M core to provide power, clock, and > -resource management. It exists on some i.MX8 processors. e.g. i.MX8QM > -(QM, QP), and i.MX8QX (QXP, DX). > - > -The AP communicates with the SC using a multi-ported MU module found > -in the LSIO subsystem. The current definition of this MU module provides > -5 remote AP connections to the SC to support up to 5 execution environments > -(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces > -with the LSIO DSC IP bus. The SC firmware will communicate with this MU > -using the MSI bus. > - > -System Controller Device Node: > -============================================================ > - > -The scu node with the following properties shall be under the /firmware/ node. > - > -Required properties: > -------------------- > -- compatible: should be "fsl,imx-scu". > -- mbox-names: should include "tx0", "tx1", "tx2", "tx3", > - "rx0", "rx1", "rx2", "rx3"; > - include "gip3" if want to support general MU interrupt. > -- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for > - rx, and 1 optional MU channel for general interrupt. > - All MU channels must be in the same MU instance. > - Cross instances are not allowed. The MU instance can only > - be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need > - to make sure use the one which is not conflict with other > - execution environments. e.g. ATF. > - Note: > - Channel 0 must be "tx0" or "rx0". > - Channel 1 must be "tx1" or "rx1". > - Channel 2 must be "tx2" or "rx2". > - Channel 3 must be "tx3" or "rx3". > - General interrupt rx channel must be "gip3". > - e.g. > - mboxes = <&lsio_mu1 0 0 > - &lsio_mu1 0 1 > - &lsio_mu1 0 2 > - &lsio_mu1 0 3 > - &lsio_mu1 1 0 > - &lsio_mu1 1 1 > - &lsio_mu1 1 2 > - &lsio_mu1 1 3 > - &lsio_mu1 3 3>; > - See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml > - for detailed mailbox binding. > - > -Note: Each mu which supports general interrupt should have an alias correctly > -numbered in "aliases" node. > -e.g. > -aliases { > - mu1 = &lsio_mu1; > -}; > - > -i.MX SCU Client Device Node: > -============================================================ > - > -Client nodes are maintained as children of the relevant IMX-SCU device node. > - > -Example (imx8qxp): > -------------- > -aliases { > - mu1 = &lsio_mu1; > -}; > - > -lsio_mu1: mailbox@5d1c0000 { > - ... > - #mbox-cells = <2>; > -}; > - > -firmware { > - scu { > - compatible = "fsl,imx-scu"; > - mbox-names = "tx0", "tx1", "tx2", "tx3", > - "rx0", "rx1", "rx2", "rx3", > - "gip3"; > - mboxes = <&lsio_mu1 0 0 > - &lsio_mu1 0 1 > - &lsio_mu1 0 2 > - &lsio_mu1 0 3 > - &lsio_mu1 1 0 > - &lsio_mu1 1 1 > - &lsio_mu1 1 2 > - &lsio_mu1 1 3 > - &lsio_mu1 3 3>; > - }; > -}; > - > -serial@5a060000 { > - ... > -}; > diff --git a/Documentation/devicetree/bindings/firmware/fsl,scu.yaml b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml > new file mode 100644 > index 000000000000..c1f5b727352e > --- /dev/null > +++ b/Documentation/devicetree/bindings/firmware/fsl,scu.yaml > @@ -0,0 +1,160 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX System Controller Firmware (SCFW) > + > +maintainers: > + - Dong Aisheng > + > +description: System Controller Device Node The formatting here is not maintained unless you use a literal block ('|'). But I would just drop this first line. > + The System Controller Firmware (SCFW) is a low-level system function > + which runs on a dedicated Cortex-M core to provide power, clock, and > + resource management. It exists on some i.MX8 processors. e.g. i.MX8QM > + (QM, QP), and i.MX8QX (QXP, DX). > + The AP communicates with the SC using a multi-ported MU module found > + in the LSIO subsystem. The current definition of this MU module provides > + 5 remote AP connections to the SC to support up to 5 execution environments > + (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces > + with the LSIO DSC IP bus. The SC firmware will communicate with this MU > + using the MSI bus. > + > +properties: > + compatible: > + const: fsl,imx-scu > + > + clock-controller: > + description: > + Clock controller node that provides the clocks controlled by the SCU > + $ref: /schemas/clock/fsl,scu-clk.yaml > + > + ocotp: > + description: > + OCOTP controller node provided by the SCU > + $ref: /schemas/nvmem/fsl,scu-ocotp.yaml > + > + keys: > + description: > + Keys provided by the SCU > + $ref: /schemas/input/fsl,scu-key.yaml > + > + mboxes: > + description: | > + List of phandle of 4 MU channels for tx, 4 MU channels for > + rx, and 1 optional MU channel for general interrupt. > + All MU channels must be in the same MU instance. > + Cross instances are not allowed. The MU instance can only > + be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need > + to make sure use the one which is not conflict with other > + execution environments. e.g. ATF. > + minItems: 1 > + maxItems: 10 Based on the description, shouldn't this be: minItems: 8 maxItems: 9 > + > + mbox-names: > + description: > + include "gip3" if want to support general MU interrupt. What are all the other names? Needs to be a schema, not freeform text. > + minItems: 1 > + maxItems: 10 > + > + pinctrl: > + description: > + Pin controller provided by the SCU > + $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml > + > + power-controller: > + description: | > + Power domains controller node that provides the power domains > + controlled by the SCU > + $ref: /schemas/power/fsl,scu-pd.yaml > + > + rtc: > + description: > + RTC controller provided by the SCU > + $ref: /schemas/rtc/fsl,scu-rtc.yaml > + > + thermal-sensor: > + description: > + Thermal sensor provided by the SCU > + $ref: /schemas/thermal/fsl,scu-thermal.yaml > + > + watchdog: > + description: > + Watchdog controller provided by the SCU > + $ref: /schemas/watchdog/fsl,scu-wdt.yaml > + > +required: > + - compatible > + - mbox-names > + - mboxes > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + firmware { > + system-controller { > + compatible = "fsl,imx-scu"; > + mbox-names = "tx0", "tx1", "tx2", "tx3", > + "rx0", "rx1", "rx2", "rx3", > + "gip3"; > + mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3 > + &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3 > + &lsio_mu1 3 3>; > + > + clock-controller { > + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; > + #clock-cells = <2>; > + }; > + > + pinctrl { > + compatible = "fsl,imx8qxp-iomuxc"; > + > + pinctrl_lpuart0: lpuart0grp { > + fsl,pins = < > + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 > + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 > + >; > + }; > + }; > + > + ocotp { > + compatible = "fsl,imx8qxp-scu-ocotp"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + fec_mac0: mac@2c4 { > + reg = <0x2c4 6>; > + }; > + }; > + > + power-controller { > + compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; > + #power-domain-cells = <1>; > + }; > + > + rtc { > + compatible = "fsl,imx8qxp-sc-rtc"; > + }; > + > + keys { > + compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; > + linux,keycodes = ; > + }; > + > + watchdog { > + compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; > + timeout-sec = <60>; > + }; > + > + thermal-sensor { > + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; > + #thermal-sensor-cells = <1>; > + }; > + }; > + }; > -- > 2.25.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel