From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99680CCA481 for ; Fri, 8 Jul 2022 11:57:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238217AbiGHL5h (ORCPT ); Fri, 8 Jul 2022 07:57:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238124AbiGHL5R (ORCPT ); Fri, 8 Jul 2022 07:57:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 497D59A6B9; Fri, 8 Jul 2022 04:57:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1657281437; x=1688817437; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fyYMzbEVBdCrRqau7PZBrDmY2vLx5Tjgwub2EQAW23A=; b=V4pIK31P2GgSzPzQ2PQcx7emhRHp1fWIvUxN7alBeOf66xOfX5NmWjSZ sbyJkDQsU+oYhyCXcOlUhRN8IQHJA/nQUbNNX7FkHXQXaMkImNqbFlWIF lUoDXe5pYP1KinU7nZudIA7nypelM2ltO+nJM+MArvtTAbHsF6ysLjoA1 HH+VHBy0JVTskugCbL2sy13+MqJK+0+z8mQpkDruUjWYSPt1Gp/5wscRE 8RSBXuHHY2Zz0DdQpmUysSNebMEfeXlPZYQdPiC6MgaQKmPY0TaW33qmk 1EaT3G+21I4eTo8nec11nI3wRmp/WouT9FO2BMsMp+j0jGA9KdN8QLWjY A==; X-IronPort-AV: E=Sophos;i="5.92,255,1650956400"; d="scan'208";a="171312680" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 08 Jul 2022 04:57:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 8 Jul 2022 04:57:16 -0700 Received: from kavya.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 8 Jul 2022 04:57:12 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , Subject: [PATCH v8 2/3] dt-bindings: mfd: atmel,sama5d2-flexcom: Add new compatible string for lan966x Date: Fri, 8 Jul 2022 09:56:18 -0200 Message-ID: <20220708115619.254073-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708115619.254073-1-kavyasree.kotagiri@microchip.com> References: <20220708115619.254073-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri --- v7 -> v8: - Changed compatible string to microchip,lan9668-flexcom. v6 -> v7: - Add #address-cells, #size-cells to flx3 example. v5 -> v6: - Removed spi node from flx3 example. v4 -> v5: - Fixed indentations and dt-schema errors. - No errors seen with 'make dt_binding_check'. v3 -> v4: - Added else condition to allOf:if:then. v2 -> v3: - Add reg property of lan966x missed in v2. v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index bfa7d340a198..568da7cb630c 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -18,9 +18,11 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan9668-flexcom reg: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 @@ -47,6 +49,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 20 + + microchip,flx-cs: + description: Flexcom chip selects. Here, value of '0' represents "cts" line + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents + "rts" line of flexcom USART or "cs1" line of flexcom SPI. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + patternProperties: "^serial@[0-9a-f]+$": type: object @@ -74,6 +97,31 @@ required: - ranges - atmel,flexcom-mode +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan9668-flexcom + + then: + properties: + reg: + items: + - description: Flexcom base registers map + - description: Flexcom shared registers map + required: + - microchip,flx-shrd-pins + - microchip,flx-cs + + else: + properties: + reg: + items: + - description: Flexcom base registers map + microchip,flx-shrd-pins: false + microchip,flx-cs: false + additionalProperties: false examples: @@ -89,4 +137,19 @@ examples: ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; }; + - | + #include + + flx3: flexcom@e0064000 { + compatible = "microchip,lan9668-flexcom"; + reg = <0xe0064000 0x100>, + <0xe2004180 0x8>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + atmel,flexcom-mode = <2>; + microchip,flx-shrd-pins = <9>; + microchip,flx-cs = <0>; + }; ... -- 2.25.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D956FC433EF for ; Fri, 8 Jul 2022 11:58:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 8 Jul 2022 04:57:12 -0700 From: Kavyasree Kotagiri To: , , , , , CC: , , , Subject: [PATCH v8 2/3] dt-bindings: mfd: atmel,sama5d2-flexcom: Add new compatible string for lan966x Date: Fri, 8 Jul 2022 09:56:18 -0200 Message-ID: <20220708115619.254073-3-kavyasree.kotagiri@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220708115619.254073-1-kavyasree.kotagiri@microchip.com> References: <20220708115619.254073-1-kavyasree.kotagiri@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220708_045717_453323_8B8C50D0 X-CRM114-Status: GOOD ( 10.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org LAN966x SoC flexcoms has two optional I/O lines. Namely, CS0 and CS1 in flexcom SPI mode. CTS and RTS in flexcom USART mode. These pins can be mapped to lan966x FLEXCOM_SHARED[0-20] pins and usage depends on functions being configured. Signed-off-by: Kavyasree Kotagiri --- v7 -> v8: - Changed compatible string to microchip,lan9668-flexcom. v6 -> v7: - Add #address-cells, #size-cells to flx3 example. v5 -> v6: - Removed spi node from flx3 example. v4 -> v5: - Fixed indentations and dt-schema errors. - No errors seen with 'make dt_binding_check'. v3 -> v4: - Added else condition to allOf:if:then. v2 -> v3: - Add reg property of lan966x missed in v2. v1 -> v2: - Use allOf:if:then for lan966x dt properties .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 65 ++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index bfa7d340a198..568da7cb630c 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -18,9 +18,11 @@ properties: compatible: enum: - atmel,sama5d2-flexcom + - microchip,lan9668-flexcom reg: - maxItems: 1 + minItems: 1 + maxItems: 2 clocks: maxItems: 1 @@ -47,6 +49,27 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [1, 2, 3] + microchip,flx-shrd-pins: + description: Specify the Flexcom shared pins to be used for flexcom + chip-selects. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 20 + + microchip,flx-cs: + description: Flexcom chip selects. Here, value of '0' represents "cts" line + of flexcom USART or "cs0" line of flexcom SPI and value of '1' represents + "rts" line of flexcom USART or "cs1" line of flexcom SPI. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + items: + minimum: 0 + maximum: 1 + patternProperties: "^serial@[0-9a-f]+$": type: object @@ -74,6 +97,31 @@ required: - ranges - atmel,flexcom-mode +allOf: + - if: + properties: + compatible: + contains: + const: microchip,lan9668-flexcom + + then: + properties: + reg: + items: + - description: Flexcom base registers map + - description: Flexcom shared registers map + required: + - microchip,flx-shrd-pins + - microchip,flx-cs + + else: + properties: + reg: + items: + - description: Flexcom base registers map + microchip,flx-shrd-pins: false + microchip,flx-cs: false + additionalProperties: false examples: @@ -89,4 +137,19 @@ examples: ranges = <0x0 0xf8034000 0x800>; atmel,flexcom-mode = <2>; }; + - | + #include + + flx3: flexcom@e0064000 { + compatible = "microchip,lan9668-flexcom"; + reg = <0xe0064000 0x100>, + <0xe2004180 0x8>; + clocks = <&flx0_clk>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + atmel,flexcom-mode = <2>; + microchip,flx-shrd-pins = <9>; + microchip,flx-cs = <0>; + }; ... -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel