From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6519C43334 for ; Tue, 12 Jul 2022 07:13:48 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 13B19840B3; Tue, 12 Jul 2022 09:13:12 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="gxanVrJR"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 864BC840C6; Tue, 12 Jul 2022 09:13:03 +0200 (CEST) Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 51538840F2 for ; Tue, 12 Jul 2022 09:12:59 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=sumit.garg@linaro.org Received: by mail-pf1-x436.google.com with SMTP id y141so6747550pfb.7 for ; Tue, 12 Jul 2022 00:12:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oIlvdV3mss24qZXBAlc7aq/UtP4U3DwiVb55YAQ4/8E=; b=gxanVrJRaly5pu0EMql6xBrUci0k9gj5d6VOsPkhPrwInlgkVB9ZqKFJRZYgbjLmhM GmNf6shv+JDXncij+Xx2s9Z7yea/xYHZZMejaZhWeWkiicf6DYbAFXzUHvK7K0DoUGmS SXyxx/fRG3dP5Pwl90dr7OpoAj1jrh0aA0p0gqzH/g5M6PGHPGl6WJXdYgdA4Cn/QIzW nP/AMo6c0K8JblwoUR0RJJafajac+hg9N5QcNfLXAm/KL41zeC8BdLMm8kpqMgmILwAE IQK0SXSp2U+FJjLXcMj7Vd14mPxvzuYkHhybw1bRGRa7X9RJUmY1lG8y+AgFs4qw7UA7 fcrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oIlvdV3mss24qZXBAlc7aq/UtP4U3DwiVb55YAQ4/8E=; b=7/bkOqSbXzC59NWf6zUJyFPkvtfM8cJp/vipHNKsB2iJC9w0MgwnVeC8mpGB4kXwNQ KRm68S128UaN9toBDQ/BeqSGx1m6W32BLYnaQLO9K3V1CKiY6rKaXwdijDOGadfaSehp 4C64Z26awhJZHaOS5r1YHA0AqMWVKriuvDewqVDzi/HwP2eyyeV/wq6o42Ifg08uOXCv /9LrSpt9a+58F4qcCDC9pvaZ9orcIVSv9fBYezWxro1eJXFwzRhnox554YlNVXmUT0sM V/2TG0I7f1Lk/bUiqxuUYBhEw0V+V0TYU7rDUeeSpLARct45JFDXtffLLZuoP4ygsPAJ Qk3g== X-Gm-Message-State: AJIora9+zsK9/hqhG2cSMWvfDlh8OMJFriOPEclCNvDiqSgQEu/l9PN3 ZaUP7E8W830khmatPBCY5FBCJldGRpWNlg== X-Google-Smtp-Source: AGRyM1uH0L/S7ejWIRSuWNnQ9P0t0gbdZGLTgtslyl4S/P0Gbt/7Hup0i5bs2BfjqeNMWS3l8SinIg== X-Received: by 2002:a05:6a00:24c1:b0:50d:33cf:811f with SMTP id d1-20020a056a0024c100b0050d33cf811fmr21922534pfv.78.1657609976981; Tue, 12 Jul 2022 00:12:56 -0700 (PDT) Received: from localhost.localdomain ([27.56.177.217]) by smtp.gmail.com with ESMTPSA id x10-20020a170902a38a00b001678ce9080dsm5928843pla.258.2022.07.12.00.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Jul 2022 00:12:56 -0700 (PDT) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, peng.fan@nxp.com, jh80.chung@samsung.com, sjg@chromium.org, trini@konsulko.com, dsankouski@gmail.com, stephan@gerhold.net, vinod.koul@linaro.org, nicolas.dechesne@linaro.org, mworsfold@impinj.com, daniel.thompson@linaro.org, pbrobinson@gmail.com, Sumit Garg Subject: [PATCH v3 7/9] pinctrl: qcom: Add pinctrl driver for QCS404 SoC Date: Tue, 12 Jul 2022 12:42:10 +0530 Message-Id: <20220712071212.2188390-8-sumit.garg@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220712071212.2188390-1-sumit.garg@linaro.org> References: <20220712071212.2188390-1-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Currently this pinctrl driver only supports BLSP UART2 specific pin configuration. Signed-off-by: Sumit Garg Reviewed-by: Ramon Fried --- arch/arm/mach-snapdragon/Makefile | 1 + arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 +++++++++++++++++++ arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 + arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 + 4 files changed, 58 insertions(+) create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 962855eb8c..cb8c1aa8d2 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -15,4 +15,5 @@ obj-y += dram.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o +obj-y += pinctrl-qcs404.o obj-$(CONFIG_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c new file mode 100644 index 0000000000..889ead0f57 --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm QCS404 pinctrl + * + * (C) Copyright 2022 Sumit Garg + */ + +#include "pinctrl-snapdragon.h" +#include + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); +static const char * const msm_pinctrl_pins[] = { + "SDC1_RCLK", + "SDC1_CLK", + "SDC1_CMD", + "SDC1_DATA", + "SDC2_CLK", + "SDC2_CMD", + "SDC2_DATA", +}; + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart2", 1}, +}; + +static const char *qcs404_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *qcs404_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector < 120) { + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; + } else { + return msm_pinctrl_pins[selector - 120]; + } +} + +static unsigned int qcs404_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data qcs404_data = { + .pin_count = 126, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = qcs404_get_function_name, + .get_function_mux = qcs404_get_function_mux, + .get_pin_name = qcs404_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index d1c560dd40..c2148a5d0a 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { #ifdef CONFIG_SDM845 { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, #endif + { .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data }, { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index ea524312a0..178ee01a41 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -28,5 +28,6 @@ struct pinctrl_function { extern struct msm_pinctrl_data apq8016_data; extern struct msm_pinctrl_data apq8096_data; extern struct msm_pinctrl_data sdm845_data; +extern struct msm_pinctrl_data qcs404_data; #endif -- 2.25.1