From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1C44BC433EF for ; Thu, 14 Jul 2022 16:55:48 +0000 (UTC) Received: from localhost ([::1]:52748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oC27v-0000g8-3T for qemu-devel@archiver.kernel.org; Thu, 14 Jul 2022 12:55:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oC0ER-0000nx-3z for qemu-devel@nongnu.org; Thu, 14 Jul 2022 10:54:23 -0400 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:25103) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1oC0EP-0002ne-1K for qemu-devel@nongnu.org; Thu, 14 Jul 2022 10:54:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1657810461; x=1689346461; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nDN70VngDogm92+w0oH8z5/YJRlAnwIUfP16hT/iRmQ=; b=ZKIsXUyD0N3MsVHwwV1TqVfRRZSPrkWtVgVnx39lEodU3AwxXyxJzzxg UhQKFSrrQWGFD0KGWOxvnaWfnSwjvy4EYYjHULTMGSP3E9CFTsz2BCFqo IEh7B+Q7nW7shJoRv7shQsjJuzYQtc7w+9CQBw729Yp6cI9xcqBKE2udC o=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 14 Jul 2022 07:54:17 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2022 07:54:17 -0700 Received: from nalasex01b.na.qualcomm.com (10.47.209.197) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Jul 2022 07:54:16 -0700 Received: from avd-de-lrx-6.eu.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Jul 2022 07:54:15 -0700 From: Tobias Roehmel To: CC: , =?UTF-8?q?Tobias=20R=C3=B6hmel?= Subject: [PATCH 03/11] target/arm: Add v8R MIDR register Date: Thu, 14 Jul 2022 16:53:47 +0200 Message-ID: <20220714145355.7225-4-quic_trohmel@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220714145355.7225-1-quic_trohmel@quicinc.com> References: <20220714145355.7225-1-quic_trohmel@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) Received-SPF: pass client-ip=199.106.114.38; envelope-from=quic_trohmel@quicinc.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 14 Jul 2022 12:46:12 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Tobias Röhmel This register is used by the ARM Cortex-R52. Signed-off-by: Tobias Röhmel --- target/arm/helper.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6457e6301c..bdf1df37d5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8201,6 +8201,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn = access_aa64_tid1, .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, }; + ARMCPRegInfo id_v8r_midr_cp_reginfo[] = { + { .name = "MIDR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY, + .access = PL1_R, .resetvalue = cpu->midr, + .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, + .readfn = midr_read, + .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), + .type = ARM_CP_OVERRIDE }, + }; ARMCPRegInfo id_cp_reginfo[] = { /* These are common to v8 and pre-v8 */ { .name = "CTR", @@ -8264,7 +8273,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) id_mpuir_reginfo.access = PL1_RW; id_tlbtr_reginfo.access = PL1_RW; } - if (arm_feature(env, ARM_FEATURE_V8)) { + if (arm_feature(env, ARM_FEATURE_V8_R)) { + define_arm_cp_regs(cpu, id_v8r_midr_cp_reginfo); + } else if (arm_feature(env, ARM_FEATURE_V8)) { define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); } else { define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); -- 2.25.1